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1. 发明授权

US06636980B1 System for launching data on a bus by using first clock for alternately selecting data from two data streams and using second clock for launching data thereafter 失效
标题翻译：用于通过使用第一时钟用于从两个数据流交替地选择数据并且之后使用第二时钟启动数据来在总线上启动数据的系统
公开(公告)号：US06636980B1
公开(公告)日：2003-10-21
申请号：US09377632
申请日：1999-08-19
申请人： Gilles Gervais , David George Caffo , James Nolan Hardage, Jr. , Stephen Douglas Weitzel
发明人： Gilles Gervais , David George Caffo , James Nolan Hardage, Jr. , Stephen Douglas Weitzel
IPC分类号： G06F106
CPC分类号： G06F13/4243
摘要： A bus interface apparatus and method are implemented. A pair of data streams is generated from the stream of data to be launched onto a data bus. Each stream is staged along a corresponding data path that includes a plurality of storage elements. Each path feeds an input of a multiplexer (MUX). The output of the MUX drives the bus, and the MUX selects a data value for launching onto the bus in response to a signal derived from an internal bus clock. The internal bus clock is also used to generate a bus clock that is output to the bus along with the data. The period of the bus clock may be a preselected multiple of the period of a processor clock. The data is staged along the two data streams in response to clocking signals derived from the processor clock. Each of the clocking signals is qualified by a corresponding hold signal, that, when asserted, holds the clocking signals in a predetermined state. The hold signals are generated in response to a plurality of control signals that are used to select the ratio of bus clock period to processor clock period. The bus interface may be asynchronously started in response to a signal from the startup logic in the central processing unit (CPU).
摘要翻译：实现总线接口装置和方法。从要发送到数据总线上的数据流生成一对数据流。每个流沿着包括多个存储元件的对应数据路径进行分级。每个路径馈送多路复用器（MUX）的输入。 MUX的输出驱动总线，并且MUX响应于从内部总线时钟导出的信号，选择用于发送到总线上的数据值。内部总线时钟也用于生成与数据一起输出到总线的总线时钟。总线时钟的周期可以是处理器时钟周期的预选倍数。响应于从处理器时钟导出的时钟信号，数据沿着两个数据流分段。每个时钟信号由相应的保持信号限定，当被断言时，将时钟信号保持在预定状态。响应于用于选择总线时钟周期与处理器时钟周期的比率的多个控制信号而产生保持信号。响应于来自中央处理单元（CPU）中的启动逻辑的信号，总线接口可以异步启动。

2. 发明授权

US5737636A Method and system for detecting bypass errors in a load/store unit of a superscalar processor 失效
标题翻译：用于检测超标量处理器的加载/存储单元中的旁路错误的方法和系统
公开(公告)号：US5737636A
公开(公告)日：1998-04-07
申请号：US591249
申请日：1996-01-18
申请人： David George Caffo , Christopher Anthony Freymuth
发明人： David George Caffo , Christopher Anthony Freymuth
IPC分类号： G06F9/38 , G06F12/08 , G06F13/16
CPC分类号： G06F9/3834 , G06F12/0802
摘要： A load queue is provided in a load/store unit of a superscalar processor that includes a real page number buffer for storing a real page number for each instruction entry in the load queue. The load queue also includes a real page number comparator coupled to the real page number buffer for comparing executing load instruction entries with queued load instruction entries in the load queue. The load queue further includes a cache line modified register coupled to the data cache. The cache line modified register marks the queued load instruction entries when a cache line of the data cache addressed by the queued load instruction entry has been modified. In a preferred embodiment, when the executing load instruction is out of program order with respect to one of the queued load instructions, and the modified cache line register has marked the queued load instruction, the load queue signals a sequencer unit to cancel the queued load instruction. The load queue further includes an instruction identification buffer coupled to a sequencer unit for storing an instruction identifier for each entry in the load queue and a program order comparator coupled to the instruction identification buffer. The program comparator compares the ordering of instruction entries in the load queue with the executing load or store instruction.
摘要翻译：在超标量处理器的加载/存储单元中提供加载队列，其包括用于存储加载队列中的每个指令条目的实际页号的实际页号缓冲器。加载队列还包括耦合到实际页号码缓冲器的实际页码比较器，用于将执行的加载指令条目与加载队列中的排队加载指令条目进行比较。加载队列还包括耦合到数据高速缓存的高速缓存线修改寄存器。高速缓存行修改的寄存器在排队的加载指令条目寻址的数据缓存的高速缓存行已被修改时标记排队的加载指令条目。在优选实施例中，当执行加载指令相对于排队的加载指令之一超出程序次序时，并且修改的高速缓存行寄存器已经标记了排队的加载指令，则加载队列发送定序器单元来取消排队的加载指令。加载队列还包括指令识别缓冲器，其耦合到定序器单元，用于存储加载队列中的每个条目的指令标识符以及耦合到指令识别缓冲器的程序顺序比较器。程序比较器将负载队列中的指令条目的顺序与执行的加载或存储指令进行比较。

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