专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06743688B1 High performance MOSFET with modulated channel gate thickness 失效
标题翻译：具有调制通道栅极厚度的高性能MOSFET
公开(公告)号：US06743688B1
公开(公告)日：2004-06-01
申请号：US09002964
申请日：1998-01-05
申请人： Mark I. Gardner , H. James Fulford , Charles E. May
发明人： Mark I. Gardner , H. James Fulford , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/265 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/518 , H01L29/66553 , H01L29/66583 , H01L29/78 , Y10S438/981
摘要： A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO2 growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO2, which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer. After forming the gate oxide layer, polysilicon is deposited onto the gate oxide. The semiconductor substrate can then be implanted to form doped drain and source regions. Spacers can then be placed over the drain and source regions and adjacent the ends of the sidewalls of the gate.
摘要翻译：具有第一厚度和第二厚度的栅极氧化物的半导体器件通过首先用氮离子注入半导体衬底的栅极区域的一部分，然后在栅极区域上形成栅极氧化物来形成。优选地，通过将栅极区域暴露于氧气环境来生长栅极氧化物。氮注入抑制氧气环境中的二氧化硅生长速率。因此，具有植入氮原子的栅极区域的部分将生长或形成诸如SiO 2的栅极氧化物层，其比栅极区域较少注入或未注入氮原子的部分更薄。可以沉积栅极氧化物层而不是生长栅极氧化物层。在形成栅极氧化物层之后，将多晶硅沉积到栅极氧化物上。然后可以注入半导体衬底以形成掺杂的漏极和源极区域。然后可以将间隔物放置在漏极和源极区域上并且邻近栅极的侧壁的端部。

2. 发明授权

US6127235A Method for making asymmetrical gate oxide thickness in channel MOSFET region 失效
标题翻译：在沟道MOSFET区域中制造不对称栅极氧化物厚度的方法
公开(公告)号：US6127235A
公开(公告)日：2000-10-03
申请号：US2656
申请日：1998-01-05
申请人： Mark I. Gardner , H. James Fulford , Charles E. May
发明人： Mark I. Gardner , H. James Fulford , Charles E. May
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/51
CPC分类号： H01L21/28176 , H01L21/28185 , H01L29/42368 , H01L29/518 , H01L29/66659 , H01L21/28114 , H01L21/28202 , H01L21/28211 , H01L29/42376
摘要： A semiconductor device has gate with a first material having a first dielectric constant adjacent the semiconductor substrate and a second material having a second dielectric constant adjacent the semiconductor substrate. A conductor, such as polysilicon, is then placed on the gate so that the first and second materials are sandwiched between the conductor and the semiconductor substrate. Since the dielectric constants of the two materials are different, the gate acts like a gate having a single dielectric with at least two thicknesses. One dielectric constant is larger than the other dielectric constant. The higher dielectric constant material is comprised of a single spacer located within the gate at the sidewall nearest the drain of the semiconductor device. A layer of silicon dioxide is positioned on the semiconductor substrate between the spacer and the other sidewall of the gate. The thickness of the spacers can be adjusted to optimize the performance of the semiconductor device.
摘要翻译：半导体器件具有栅极，第一材料具有邻近半导体衬底的第一介电常数和邻近半导体衬底的具有第二介电常数的第二材料。然后将诸如多晶硅的导体放置在栅极上，使得第一和第二材料夹在导体和半导体衬底之间。由于两种材料的介电常数不同，栅极的作用就像具有至少两个厚度的单个电介质的栅极。一个介电常数大于另一介电常数。较高的介电常数材料由最靠近半导体器件的漏极的侧壁处的栅极内的单个间隔件组成。二氧化硅层位于半导体衬底上的间隔件和栅极的另一个侧壁之间。可以调整间隔件的厚度以优化半导体器件的性能。

3. 发明授权

US06207485B1 Integration of high K spacers for dual gate oxide channel fabrication technique 失效
标题翻译：用于双栅极氧化物沟道制造技术的高K间隔物的集成
公开(公告)号：US06207485B1
公开(公告)日：2001-03-27
申请号：US09002725
申请日：1998-01-05
申请人： Mark I. Gardner , H. James Fulford , Charles E. May
发明人： Mark I. Gardner , H. James Fulford , Charles E. May
IPC分类号： H01L218238
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/518 , H01L29/66583
摘要： A semiconductor device has gate with a first material having a first dielectric constant adjacent the semiconductor substrate and a second material having a second dielectric constant adjacent the semiconductor substrate. A conductor, such as polysilicon, is then placed on the gate so that the first and second materials are sandwiched between the conductor and the semiconductor substrate. Since the dielectric constants of the two materials are different, the gate acts like a gate having a single dielectric with at least two thicknesses. This is due to the fact that each material has a dielectric constant that is different. One dielectric constant is larger than the other dielectric constant. The higher dielectric constant material is comprised of two spacers at the sidewalls of the gate. A layer of silicon dioxide is positioned on the semiconductor substrate between the spacers. The thickness of the spacers can be adjusted to optimize the performance of the semiconductor device.
摘要翻译：半导体器件具有栅极，第一材料具有邻近半导体衬底的第一介电常数和邻近半导体衬底的具有第二介电常数的第二材料。然后将诸如多晶硅的导体放置在栅极上，使得第一和第二材料夹在导体和半导体衬底之间。由于两种材料的介电常数不同，栅极的作用就像具有至少两个厚度的单个电介质的栅极。这是由于每种材料的介电常数不同。一个介电常数大于另一介电常数。较高介电常数材料由栅极侧壁上的两个间隔物组成。二氧化硅层位于半导体衬底上的间隔物之间。可以调整间隔件的厚度以优化半导体器件的性能。

4. 发明授权

US06767794B2 Method of making ultra thin oxide formation using selective etchback technique integrated with thin nitride layer for high performance MOSFET 失效
标题翻译：使用与用于高性能MOSFET的薄氮化物层集成的选择性回蚀技术制造超薄氧化物形成的方法
公开(公告)号：US06767794B2
公开(公告)日：2004-07-27
申请号：US09002724
申请日：1998-01-05
申请人： Mark I. Gardner , Michael Allen , H. James Fulford
发明人： Mark I. Gardner , Michael Allen , H. James Fulford
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/28211 , H01L21/3144 , H01L29/513 , H01L29/518
摘要： A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO2 growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO2, which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer. After forming the gate oxide layer, polysilicon is deposited onto the gate oxide. The semiconductor substrate can then be implanted to form doped drain and source regions. Spacers can then be placed over the drain and source regions and adjacent the ends of the sidewalls of the gate.
摘要翻译：具有第一厚度和第二厚度的栅极氧化物的半导体器件通过首先用氮离子注入半导体衬底的栅极区域的一部分，然后在栅极区域上形成栅极氧化物来形成。优选地，通过将栅极区域暴露于氧气环境来生长栅极氧化物。氮注入抑制氧气环境中的二氧化硅生长速率。因此，具有植入氮原子的栅极区域的部分将生长或形成诸如SiO 2的栅极氧化物层，其比栅极区域较少注入或未注入氮原子的部分更薄。可以沉积栅极氧化物层而不是生长栅极氧化物层。在形成栅极氧化物层之后，将多晶硅沉积到栅极氧化物上。然后可以注入半导体衬底以形成掺杂的漏极和源极区域。然后可以将间隔物放置在漏极和源极区域上并且邻近栅极的侧壁的端部。

5. 发明授权

US6054374A Method of scaling dielectric thickness in a semiconductor process with ion implantation 失效
标题翻译：使用离子注入在半导体工艺中缩放电介质厚度的方法
公开(公告)号：US6054374A
公开(公告)日：2000-04-25
申请号：US979599
申请日：1997-11-26
申请人： Mark I. Gardner , H. James Fulford, Jr.
发明人： Mark I. Gardner , H. James Fulford, Jr.
IPC分类号： H01L21/28 , H01L21/8234 , H01L21/265
CPC分类号： H01L21/8234 , H01L21/28167 , H01L21/28211
摘要： A semiconductor fabrication process including a method of controlling the gate dielectric film thickness without adjusting the oxidation recipe. A sacrificial dielectric layer is formed on an upper surface of a semiconductor substrate. An oxidation inhibiting species is then introduced into the semiconductor substrate. The sacrificial dielectric layer is then removed from the substrate and the substrate is immersed into an oxygen bearing ambient maintained at a recipe temperature for a recipe duration. Preferably, the recipe temperature is in the range of approximately 500 to 800.degree. C. and the recipe duration is in the range of approximately 2 to 20 minutes. The final thickness of the gate dielectric film is adjusted by altering a concentration of the oxidation inhibiting species within the semiconductor substrate. Preferably, the method of altering the concentration of the oxidation inhibiting species is accomplished by adjusting the dose of an implant used to introduced the oxidation inhibiting species into the semiconductor substrate.
摘要翻译：一种半导体制造工艺，包括在不调节氧化配方的情况下控制栅极电介质膜厚度的方法。牺牲电介质层形成在半导体衬底的上表面上。然后将氧化抑制物质引入半导体衬底。然后将牺牲介电层从基底上除去，并将基底浸入保持在配方温度下的配方持续时间的含氧环境中。优选地，配方温度在约500至800℃的范围内，配方持续时间在约2至20分钟的范围内。通过改变半导体衬底内的氧化抑制物质的浓度来调节栅介质膜的最终厚度。优选地，通过将用于引入氧化抑制物质的植入物的剂量调整到半导体衬底中来实现改变氧化抑制物质的浓度的方法。

6. 发明授权

US06040602A Formation of lightly doped regions under a gate 失效
标题翻译：在栅极下形成轻掺杂区域
公开(公告)号：US06040602A
公开(公告)日：2000-03-21
申请号：US993919
申请日：1997-12-18
申请人： H. James Fulford , Mark I. Gardner
发明人： H. James Fulford , Mark I. Gardner
IPC分类号： H01L21/336 , H01L29/78 , H01L29/76
CPC分类号： H01L29/66636 , H01L29/7834
摘要： The formation of lightly doped regions under a gate of a transistor is disclosed. In one embodiment of the invention, a method includes four steps. In the first step, a gate is formed over a semiconductor substrate. In the second step, the semiconductor substrate is etched. In the third step, a first ion implantation is applied. Finally, in the fourth step, a second ion implantation is applied, perpendicular to the substrate.
摘要翻译：公开了在晶体管的栅极下形成轻掺杂区域。在本发明的一个实施例中，一种方法包括四个步骤。在第一步骤中，在半导体衬底上形成栅极。在第二步骤中，蚀刻半导体衬底。在第三步骤中，应用第一离子注入。最后，在第四步骤中，施加垂直于衬底的第二离子注入。

7. 发明授权

US06258675B1 High K gate electrode 失效
标题翻译：高K栅电极
公开(公告)号：US06258675B1
公开(公告)日：2001-07-10
申请号：US08993766
申请日：1997-12-18
申请人： Mark I. Gardner , H. James Fulford
发明人： Mark I. Gardner , H. James Fulford
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6653
摘要： A semiconductor structure with a high-K insulative layer. An insulative layer is disposed on a silicon substrate and includes a first nitride layer and a high-K layer. A gate is disposed on the insulative layer. The insulative layer further includes sidewalls extending at least flush with corresponding sidewalls of the gate. Source and drain regions are disposed within the substrate adjacent to the insulative layer.
摘要翻译：具有高K绝缘层的半导体结构。绝缘层设置在硅衬底上，并且包括第一氮化物层和高K层。栅极设置在绝缘层上。绝缘层还包括至少与栅极的相应侧壁齐平的侧壁。源极和漏极区域设置在与绝缘层相邻的衬底内。

8. 发明授权

US06124175A Rapid thermal anneal with a gaseous dopant species 失效
标题翻译：快速热退火与气态掺杂物种
公开(公告)号：US06124175A
公开(公告)日：2000-09-26
申请号：US993998
申请日：1997-12-18
申请人： Mark I. Gardner , H. James Fulford
发明人： Mark I. Gardner , H. James Fulford
IPC分类号： H01L21/223 , H01L21/3115 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/66575 , H01L21/223 , H01L21/823418 , H01L21/31155
摘要： Rapid thermal anneal with a gaseous dopant species is disclosed. In one embodiment, a method includes three steps. In the first step, at least one gate is formed over a semiconductor substrate. In the second step, at least one spacer for each of the gates is formed, where each spacer is adjacent to an edge of its corresponding gate. In the third step, a rapid thermal anneal with a gaseous dopant species is performed to form source and drain regions within the substrate. Desirably, the source and drain regions meet the substrate underneath the gate at shallow junctions.
摘要翻译：公开了具有气态掺杂剂物质的快速热退火。在一个实施例中，一种方法包括三个步骤。在第一步骤中，在半导体衬底上形成至少一个栅极。在第二步骤中，形成用于每个栅极的至少一个间隔件，其中每个间隔件邻近其对应栅极的边缘。在第三步骤中，进行具有气态掺杂剂物质的快速热退火以在衬底内形成源区和漏区。理想地，源极和漏极区域在浅结点处与栅极下方的衬底相遇。

9. 发明授权

US6060733A Formation of lightly doped regions under a gate having a reduced gate oxide 失效
标题翻译：在具有还原的栅极氧化物的栅极下形成轻掺杂区域
公开(公告)号：US6060733A
公开(公告)日：2000-05-09
申请号：US993925
申请日：1997-12-18
申请人： Mark I. Gardner , H. James Fulford
发明人： Mark I. Gardner , H. James Fulford
IPC分类号： H01L21/265 , H01L21/336 , H01L29/72
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/2652 , H01L21/26586
摘要： The formation of lightly doped regions under a gate of a transistor that has a reduced gate oxide is disclosed. In one embodiment, a method includes four steps. In the first step, a gate is formed over a semiconductor substrate. In the second step, the gate oxide is etched to reduce the length of the gate oxide. In the third step, a first ion implantation is applied, at an angle other than perpendicular to the substrate. Finally, in the fourth step, a second ion implantation is applied, perpendicular to the substrate.
摘要翻译：公开了在具有还原栅极氧化物的晶体管的栅极下形成轻掺杂区域。在一个实施例中，一种方法包括四个步骤。在第一步骤中，在半导体衬底上形成栅极。在第二步骤中，蚀刻栅极氧化物以减小栅极氧化物的长度。在第三步骤中，以垂直于衬底的角度施加第一离子注入。最后，在第四步骤中，施加垂直于衬底的第二离子注入。

10. 发明授权

US06451657B1 Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant 失效
标题翻译：具有由横向扩散的氮植入物限定的超短沟道长度的晶体管
公开(公告)号：US06451657B1
公开(公告)日：2002-09-17
申请号：US09781044
申请日：2001-02-08
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L21/28132 , Y10S257/90
摘要： A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a lightly doped semiconductor substrate. A gate conductor layer is then deposited over the gate oxide layer. The upper surface of the gate conductor layer includes a future conductor area laterally bounded by a spaced pair of target areas, wherein the lateral distance between the spaced pair of target areas is preferably chosen at the photolithography threshold. Nitrogen is implanted into the spaced pair of target areas to form a spaced pair of nitrogen bearing regions within the gate conductor layer, thereby defining a nitrogen free region in the gate conductor layer. A thermal anneal reduces the width of the nitrogen free region. A variable thickness oxide layer is then grown over the entire semiconductor topography and anisotropically etched to form an oxide mask over the reduced-width nitrogen free region. Portions of the gate conductor layer not covered by the oxide mask are then removed, leaving the reduced-width nitrogen free region as a gate conductor having a width below the photolithography threshold.
摘要翻译：公开了一种用于制造具有小于使用普通光刻技术可分辨长度的沟道长度的晶体管的工艺。在轻掺杂的半导体衬底上形成栅氧化层。然后在栅极氧化物层上沉积栅极导体层。栅极导体层的上表面包括由间隔开的一对目标区域横向限定的未来导体区域，其中间隔开的一对目标区域之间的横向距离优选地以光刻阈值选择。将氮气注入到间隔开的一对目标区域中，以在栅极导体层内形成间隔开的一对含氮区域，从而在栅极导体层中限定无氮区域。热退火降低了无氮区域的宽度。然后在整个半导体拓扑上生长可变厚度的氧化物层，并进行各向异性蚀刻，以在较宽的无氮区域上形成氧化物掩模。然后去除不被氧化物掩模覆盖的栅极导体层的部分，留下宽度窄的无氮区域作为宽度低于光刻阈值的栅极导体。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式