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1. 发明授权

US5986313A Semiconductor device comprising MISFETS and method of manufacturing the same 失效
标题翻译：包括MISFET的半导体器件及其制造方法
公开(公告)号：US5986313A
公开(公告)日：1999-11-16
申请号：US988776
申请日：1997-12-11
申请人： Tetsuya Ueda , Takashi Uehara , Kousaku Yano , Satoshi Ueda
发明人： Tetsuya Ueda , Takashi Uehara , Kousaku Yano , Satoshi Ueda
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/417 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/6659 , H01L21/823475 , H01L29/41775 , H01L29/41783 , H01L29/66545
摘要： There is formed an isolation which surrounds an active region of a semiconductor substrate. Formed over the active region and on the isolation, respectively, are a gate electrode and two gate interconnections on both sides thereof. Between the gate electrode and the gate interconnections are located two first interspaces each of which is smaller in width than a specified value and a second interspace which is larger in width than the specified value and interposed between the two first interspaces. In forming side walls on both side faces of the gate electrode and gate interconnections by depositing an insulating film on the substrate, the first interspaces are buried with the insulating film. Thereafter, a metal film is deposited on the substrate, followed by chemical mechanical polishing till the gate electrode, gate interconnections, and side walls become exposed. By the process, withdrawn electrodes from a source/drain region for ccntact with the active region is formed by self alignment, while the withdrawn electrodes are insulated from the gate electrode and gate interconnections by the side walls.
摘要翻译：形成围绕半导体衬底的有源区的隔离。分别在有源区和隔离层上形成栅电极和两侧栅极互连。在栅极电极和栅极互连之间设置两个第一空间，每个空间的宽度小于指定值，第二空间的宽度大于指定值并插入在两个第一间隙之间。在通过在衬底上沉积绝缘膜来形成栅电极的两个侧面上的侧壁和栅极互连时，第一间隙被绝缘膜掩埋。然后，将金属膜沉积在基板上，然后进行化学机械抛光，直到栅极，栅极互连和侧壁变得暴露。通过该处理，通过自对准来形成用于与有源区域成反射的源极/漏极区域的引出电极，而引出的电极通过侧壁与栅电极和栅极互连绝缘。

2. 发明授权

US5733812A Semiconductor device with a field-effect transistor having a lower resistance impurity diffusion layer, and method of manufacturing the same 失效
标题翻译：具有具有较低电阻杂质扩散层的场效应晶体管的半导体器件及其制造方法
公开(公告)号：US5733812A
公开(公告)日：1998-03-31
申请号：US571131
申请日：1995-12-12
申请人： Tetsuya Ueda , Takashi Uehara , Kousaku Yano , Satoshi Ueda
发明人： Tetsuya Ueda , Takashi Uehara , Kousaku Yano , Satoshi Ueda
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/417 , H01L21/265
CPC分类号： H01L29/6659 , H01L21/823475 , H01L29/41775 , H01L29/41783 , H01L29/66545
摘要： There is formed an isolation which surrounds an active region of a semiconductor substrate. Formed over the active region and on the isolation, respectively, are a gate electrode and two gate interconnections on both sides thereof. Between the gate electrode and the gate interconnections are located two first interspaces each of which is smaller in width than a specified value and a second interspace which is larger in width than the specified value and interposed between the two first interspaces. In forming side walls on both side faces of the gate electrode and gate interconnections by depositing an insulating film on the substrate, the first interspaces are buried with the insulating film. Thereafter, a metal film is deposited on the substrate, followed by chemical mechanical polishing till the gate electrode, gate interconnections, and side walls become exposed. By the process, withdrawn electrodes from a source/drain region for contact with the active region is formed by self alignment, while the withdrawn electrodes are insulated from the gate electrode and gate interconnections by the side walls.
摘要翻译：形成围绕半导体衬底的有源区的隔离。分别在有源区和隔离层上形成栅电极和两侧栅极互连。在栅极电极和栅极互连之间设置两个第一空间，每个空间的宽度小于指定值，第二空间的宽度大于指定值并插入在两个第一间隙之间。在通过在衬底上沉积绝缘膜来形成栅电极的两个侧面上的侧壁和栅极互连时，第一间隙被绝缘膜掩埋。然后，将金属膜沉积在基板上，然后进行化学机械抛光，直到栅极，栅极互连和侧壁变得暴露。通过该处理，通过自对准形成来自用于与有源区接触的源极/漏极区域的引出电极，而引出的电极通过侧壁与栅电极和栅极互连绝缘。

3. 发明申请

US20070274139A1 Semiconductor memory device and semiconductor device 失效
标题翻译：半导体存储器件和半导体器件
公开(公告)号：US20070274139A1
公开(公告)日：2007-11-29
申请号：US11826751
申请日：2007-07-18
申请人： Masahiro Yamashita , Takashi Uehara , Mamoru Takaku , Hiroaki Nambu
发明人： Masahiro Yamashita , Takashi Uehara , Mamoru Takaku , Hiroaki Nambu
IPC分类号： G11C5/14
CPC分类号： G11C29/023 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028
摘要： A technology capable of improving the yield by the trimming of internal properties of a semiconductor device is provided. A semiconductor device is provided with an internal voltage step-down circuit and an internal voltage step-up circuit whose property values (internal voltage and others) are variable, a fuse circuit unit, a JTAG function unit 304 which inputs and retains signals from outside, a control circuit which perform logical operation based on an output signal of the fuse circuit unit and an output signal of the JTAG function unit, and the property values of the internal voltage step-down circuit and the internal voltage step-up circuit are controlled based on a result of the logical operation by the control circuit.
摘要翻译：提供了能够通过修整半导体器件的内部特性来提高产量的技术。半导体器件具有内部降压电路和其特性值（内部电压等）可变的内部升压电路，熔丝电路单元，输入并保持来自外部的信号的JTAG功能单元304 控制电路，其基于熔丝电路单元的输出信号和JTAG功能单元的输出信号进行逻辑运算，并且控制内部降压电路和内部升压电路的特性值基于控制电路的逻辑运算的结果。

4. 发明授权

US6143626A Method of manufacturing a semiconductor device using a trench isolation technique 失效
标题翻译：使用沟槽隔离技术制造半导体器件的方法
公开(公告)号：US6143626A
公开(公告)日：2000-11-07
申请号：US330068
申请日：1999-06-11
申请人： Toshiki Yabu , Takashi Uehara , Mizuki Segawa , Takashi Nakabayashi
发明人： Toshiki Yabu , Takashi Uehara , Mizuki Segawa , Takashi Nakabayashi
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229
摘要： On a semiconductor substrate are successively deposited a silicon dioxide film and a silicon nitride film. The silicon nitride film, the silicon dioxide film, and the semiconductor substrate are sequentially etched using a photoresist film with an opening corresponding to an isolation region, thereby forming a trench. After depositing a diffusion preventing film, there is deposited an insulating film for isolation having reflowability. Although a void is formed in the insulating film for isolation in the isolation region, the insulating film for isolation is caused to reflow, thereby eliminating the void. After that, the whole substrate is planarized by CMP so as to remove the silicon nitride film and the silicon dioxide film, followed by the formation of gate insulating films, gate electrodes, sidewalls, and source/drain regions in respective element formation regions. Thus, in a highly integrated semiconductor device having a trench isolation, degradation of reliability resulting from the opening of the void in the surface of isolation is prevented.
摘要翻译：在半导体衬底上依次沉积二氧化硅膜和氮化硅膜。使用具有对应于隔离区域的开口的光致抗蚀剂膜，依次蚀刻氮化硅膜，二氧化硅膜和半导体衬底，从而形成沟槽。在沉积防扩散膜之后，沉积具有可回流性的用于隔离的绝缘膜。虽然在隔离区域中用于隔离的绝缘膜中形成空隙，但是使用于隔离的绝缘膜回流，从而消除空隙。之后，通过CMP对整个基板进行平坦化，以除去氮化硅膜和二氧化硅膜，然后在各个元件形成区域中形成栅极绝缘膜，栅极电极，侧壁和源极/漏极区域。因此，在具有沟槽隔离的高度集成的半导体器件中，防止了由于隔离表面中的空隙的打开引起的可靠性降低。

5. 发明授权

US5498908A Semiconductor apparatus having an n-channel MOS transistor and a p-channel MOS transistor and method for manufacturing the semiconductor apparatus 失效
标题翻译：具有n沟道MOS晶体管和p沟道MOS晶体管的半导体装置及其制造方法
公开(公告)号：US5498908A
公开(公告)日：1996-03-12
申请号：US380460
申请日：1995-01-30
申请人： Takashi Nakabayashi , Takashi Uehara , Akihira Shinohara
发明人： Takashi Nakabayashi , Takashi Uehara , Akihira Shinohara
IPC分类号： H01L21/8238 , H01L29/49 , H01L29/76 , H01L23/48
CPC分类号： H01L21/823842 , H01L21/823871 , H01L29/4933
摘要： A semiconductor apparatus with MOS transistors for transmitting electrons from an n type source layer to an n type drain layer through a first channel region in an n-channel MOS transistor and transmitting holes from a p type source layer to a p type drain layer through a second channel region in a p-channel MOS transistor consists of a field oxide layer for separating the n-channel MOS transistor from the p-channel MOS transistor, an n type gate electrode mounted on a first gate oxide film arranged on the first channel region, a p type gate electrode mounted on a second gate oxide film arranged on the second channel region and positioned far away from the n type gate electrode to prevent impurities implanted into one of tile gate electrodes from diffusing into the other gate electrode, and a gate metal wiring connecting the gate electrodes through a gate contact hole to miniaturize the transistors.
摘要翻译：一种具有MOS晶体管的半导体器件，用于通过n沟道MOS晶体管中的第一沟道区将电子从n型源极层传输到n型漏极层，并且通过第二沟道将空穴从ap型源极层传输到ap型漏极层 p沟道MOS晶体管的区域由用于从p沟道MOS晶体管分离n沟道MOS晶体管的场氧化物层，安装在布置在第一沟道区上的第一栅氧化膜上的n型栅电极，型栅电极，其安装在布置在第二沟道区上并位于远离n型栅电极的第二栅极氧化膜上，以防止注入到一块瓦栅电极中的杂质扩散到另一栅电极中;栅极金属布线连接栅极通过栅极接触孔使晶体管小型化。

6. 发明授权

US5409847A Manufacturing method of CMOS transistor in which heat treatment at higher temperature is done prior to heat treatment at low temperature 失效
标题翻译：在低温下进行热处理之前，在较高温度下进行热处理的CMOS晶体管的制造方法
公开(公告)号：US5409847A
公开(公告)日：1995-04-25
申请号：US141727
申请日：1993-10-27
申请人： Mizuki Segawa , Yoshiaki Kato , Hiroaki Nakaoka , Takashi Nakabayashi , Atsushi Hori , Hiroshi Masuda , Ichiro Matsuo , Akihira Shinohara , Takashi Uehara , Mitsuo Yasuhira
发明人： Mizuki Segawa , Yoshiaki Kato , Hiroaki Nakaoka , Takashi Nakabayashi , Atsushi Hori , Hiroshi Masuda , Ichiro Matsuo , Akihira Shinohara , Takashi Uehara , Mitsuo Yasuhira
IPC分类号： H01L21/8238 , H01L21/265
CPC分类号： H01L21/823814 , Y10S148/147
摘要： Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.
摘要翻译： N沟道晶体管和P沟道晶体管的栅电极形成在半导体衬底上，栅极绝缘体在其间。在对栅电极进行第一热处理之后，使用N沟道晶体管的栅电极作为掩模来形成作为N沟道晶体管的源极或漏极的N型重掺杂扩散层。在比第一热处理的温度低的情况下对N型重掺杂扩散层进行第二次热处理之后，使用P型重掺杂扩散层作为P沟道晶体管的源极或漏极，形成为使用 P沟道晶体管的栅电极作为掩模。然后，在比第二热处理的温度低的温度下对P型重掺杂扩散层进行第三次热处理。

7. 发明授权

US3936595A Signal transmission system for transmitting programed information such as programed instruction 失效
标题翻译：用于发送编程信息的信号传输系统，如编程指令
公开(公告)号：US3936595A
公开(公告)日：1976-02-03
申请号：US392557
申请日：1973-08-29
申请人： Akio Yanagimachi , Takashi Uehara , Tetsuo Yamamoto , Hisakichi Yamane , Eiichi Sawabe , Takehiko Yoshino , Teruhiro Takezawa , Michio Masuda , Hiroaki Nabeyama , Masaaki Fukuda , Tatsuo Kayano
发明人： Akio Yanagimachi , Takashi Uehara , Tetsuo Yamamoto , Hisakichi Yamane , Eiichi Sawabe , Takehiko Yoshino , Teruhiro Takezawa , Michio Masuda , Hiroaki Nabeyama , Masaaki Fukuda , Tatsuo Kayano
IPC分类号： G09B5/06 , G09B5/12 , H04J3/16 , H04N1/00 , H04N7/025 , H04N7/03 , H04N7/035 , H04N7/08 , H04N7/081 , H04N7/12 , G09B7/04
CPC分类号： H04N1/00098 , G09B5/12 , H04J3/1605
摘要： A signal transmission system for transmitting programed information such as a programed instruction comprising at a transmitter end circuitry for producing a number of program materials and a control signal which is used at a receiver end to control the manner of sequentially connecting program materials in accordance with a response input of a student to construct at least one significant program. The system comprises at the receiver end circuitry for detecting the control signal, circuitry for extracting desired program materials in a desired sequence with the aid of the control signal in accordance with the response input of the student and apparatus for displaying the extracted desired program materials.
摘要翻译：一种用于发送诸如编程指令的编程信息的信号传输系统，所述编程信息包括在发射机端用于产生多个节目资料的电路，以及在接收机端使用的控制信号，以控制依次连接节目资料的方式一个学生的响应输入，以构建至少一个重要的程序。该系统包括在接收端，用于检测控制信号的电路，用于根据学生的响应输入和用于显示所提取的所需节目素材的设备借助于控制信号以期望的顺序提取所需节目素材的电路。

8. 发明授权

US09292988B2 Display and labeled article 有权
标题翻译：显示和标签文章
公开(公告)号：US09292988B2
公开(公告)日：2016-03-22
申请号：US13477739
申请日：2012-05-22
申请人： Manabu Watanabe , Mihoko Nagayoshi , Takashi Uehara , Hideki Ochiai
发明人： Manabu Watanabe , Mihoko Nagayoshi , Takashi Uehara , Hideki Ochiai
IPC分类号： G07D7/00 , G07D7/12 , C09D11/106 , D21H21/40 , D21H21/48 , G09F3/00 , B42D25/425 , B42D25/29 , B42D25/328 , B42D25/355 , B42D25/00 , G09F3/02 , B42D25/324
CPC分类号： G09F3/0292 , B42D25/00 , B42D25/29 , B42D25/324 , B42D25/328 , B42D25/355 , B42D25/369 , B42D25/425 , B42D2033/10 , B42D2033/16 , B42D2033/18 , B42D2033/20 , B42D2033/24 , B42D2033/26 , B42D2033/30 , B42D2033/32 , B42D2035/20 , B42D2035/24 , C09D11/106 , D21H21/40 , D21H21/48 , G02B5/003 , G02B5/1861 , G02B5/285 , G02B5/3016 , G07D7/003 , G07D7/12 , G09F2003/0277
摘要： A display includes a first optical effect layer including a first interface part, the first interface part being provided with recesses or protrusions arranged two-dimensionally at the minimum center-to-center distance of 200 nm to 500 nm, each of the recesses or protrusions having a forward-tapered shape, a reflective material layer covering at least a part of the first interface part, and a second optical effect layer including, at a position of a first portion of the first interface part that is covered with the reflective material layer, a portion that faces the reflective material layer with the first optical effect layer interposed therebetween or faces the first optical effect layer with the reflective material layer interposed therebetween, the second optical effect layer containing at least one of a cholesteric liquid crystal, a pearl pigment and a multilayer interference film.
摘要翻译：显示器包括：第一光学效应层，包括第一接口部分，第一接口部分设置有以200nm至500nm的最小中心至中心距离二维布置的凹部或突起，每个凹部或突起具有前锥形形状，覆盖所述第一界面部分的至少一部分的反射材料层和第二光学效应层，所述第二光学效应层包括在所述第一界面部分的被所述反射材料层覆盖的第一部分的位置处面向所述反射材料层的部分，其间插入有所述第一光学效应层，或者面对所述第一光学效应层，所述第一光学效应层插入在所述第一光学效应层之间，所述第二光学效应层包含胆甾型液晶，珍珠颜料和多层干涉膜。

9. 发明申请

US20090060558A1 IMAGE FORMING APPARATUS AND CONTROL METHOD THEREOF 有权
标题翻译：图像形成装置及其控制方法
公开(公告)号：US20090060558A1
公开(公告)日：2009-03-05
申请号：US12199426
申请日：2008-08-27
申请人： Takashi Uehara
发明人： Takashi Uehara
IPC分类号： G03G15/00
CPC分类号： G03G15/5004
摘要： An image forming apparatus which is capable of reducing the number of times a second member is separated from a first member upon entry into power-save mode, thereby minimizing failures of a separation unit. A pressure-roller separating mechanism is provided so as to abut and separate a pressure roller and a fixing roller against/from each other. The image forming apparatus is controlled to change to a power-save mode in which power consumption of the image forming apparatus is reduced. The pressure-roller separating mechanism is controlled to separate the pressure roller and the fixing roller from each other in the power-save mode based on a measurement result measured by a timer, and the power-save mode is maintained after the pressure roller and the fixing roller are separated from each other.
摘要翻译：一种图像形成装置，其能够减少在进入省电模式时第二构件与第一构件分离的次数，从而使分离单元的故障最小化。压辊分离机构设置成抵靠和分离加压辊和定影辊。控制图像形成装置转换成图像形成装置的功耗降低的省电模式。根据由定时器测量的测量结果，压力辊分离机构被控制为在节电模式下将压力辊和定影辊彼此分开，并且在压力辊和定影辊彼此分离。

10. 发明授权

US06967409B2 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US06967409B2
公开(公告)日：2005-11-22
申请号：US10454682
申请日：2003-06-05
申请人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
发明人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
IPC分类号： H01L21/336 , H01L21/762 , H01L29/40
CPC分类号： H01L29/6659 , H01L21/76224 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

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