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1. 发明授权

US5385867A Method for forming a multi-layer metallic wiring structure 失效
标题翻译：用于形成多层金属布线结构的方法
公开(公告)号：US5385867A
公开(公告)日：1995-01-31
申请号：US216968
申请日：1994-03-24
申请人： Tetsuya Ueda , Kousaku Yano , Tomoyasu Murakami , Michinari Yamanaka , Shuji Hirao , Noboru Nomura
发明人： Tetsuya Ueda , Kousaku Yano , Tomoyasu Murakami , Michinari Yamanaka , Shuji Hirao , Noboru Nomura
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L21/283 , H01L21/31
CPC分类号： H01L21/76847 , H01L21/76844 , H01L21/76877 , H01L21/76885 , H01L23/5226 , H01L2924/0002 , Y10S438/948
摘要： After accumulating a BPSG film layer on a silicon substrate, a first Al--Si--Cu film layer, a W film layer and a second Al--Si--Cu film layer are successively accumulated on this BPSG film layer. A resist pattern with wide-width and narrow-width pattern portions is formed on the second Al--Si--Cu film layer. The wide-width pattern portion is provided at a position corresponding to a contact for connecting a first-layer metallic wiring and a second-layer metallic wiring, while the narrow-width pattern portion is provided at a position corresponding to a wiring portion for the first-layer metallic wiring. After applying first etching on the second Al--Si--Cu film layer with a mask of the resist patter, second etching is applied on the W film layer. Thereafter, by applying third etching, the resist pattern remaining on the first-layer metallic wiring is removed and the first Al--Si--Cu film layer is transfigured into a tall metallic film portion and a short metallic film portion. After accumulating an inter-layer insulating film layer on the first Al--Si--Cu film layer, etchback is applied on this inter-layer insulating film layer until the top of the tall metallic film portion is bared. Then, the second-layer metallic wiring is formed on the inter-layer insulating film layer so that the second-layer metallic wiring is connected with the tall metallic film portion.
摘要翻译：在硅衬底上积累BPSG膜层之后，第一Al-Si-Cu膜层，W膜层和第二Al-Si-Cu膜层依次堆积在该BPSG膜层上。在第二Al-Si-Cu膜层上形成具有宽幅和窄宽图案部分的抗蚀剂图案。宽幅图形部分设置在与用于连接第一层金属布线和第二层金属布线的接触件相对应的位置处，而窄宽图案部分设置在与布线部分相对应的位置处第一层金属布线。在具有抗蚀剂图案的掩模的第二Al-Si-Cu膜层上施加第一蚀刻之后，在W膜层上施加第二蚀刻。此后，通过施加第三蚀刻，去除残留在第一层金属布线上的抗蚀剂图案，并将第一Al-Si-Cu膜层变形为高金属膜部分和短金属膜部分。在第一Al-Si-Cu膜层上积累层间绝缘膜层之后，在该层间绝缘膜层上施加回蚀，直到高金属膜部分的顶部露出。然后，在层间绝缘膜层上形成第二层金属布线，使得第二层金属布线与高金属膜部分连接。

2. 发明授权

US5312776A Method of preventing the corrosion of metallic wirings 失效
标题翻译：防止金属布线腐蚀的方法
公开(公告)号：US5312776A
公开(公告)日：1994-05-17
申请号：US977022
申请日：1992-11-16
申请人： Tomoyasu Murakami , Michinari Yamanaka , Kousaku Yano , Masayuki Endo , Noboru Nomura , Staoshi Ueda , Naoto Matsuo , Hiroshi Imai , Masafumi Kubota
发明人： Tomoyasu Murakami , Michinari Yamanaka , Kousaku Yano , Masayuki Endo , Noboru Nomura , Staoshi Ueda , Naoto Matsuo , Hiroshi Imai , Masafumi Kubota
IPC分类号： H01L21/02 , H01L21/3213 , H01L23/532 , H01L71/44
CPC分类号： H01L21/02071 , H01L23/5329 , H01L2924/0002 , Y10S148/131
摘要： According to the method of preventing the corrosion of metallic wirings of the present invention, aluminium alloy wirings are formed on the surface of a substrate with the use of photoresists, and the photoresists are then removed. Thereafter, HMDS (hexamethyl disilazine) serving as a surface-active agent or its derivative is supplied to the aluminium alloy wirings to form hydrophobic molecular layers on the lateral walls of the aluminium alloy wirings.
摘要翻译：根据本发明的防止金属配线的腐蚀的方法，使用光致抗蚀剂在基板的表面上形成铝合金布线，然后除去光致抗蚀剂。此后，将作为表面活性剂或其衍生物的HMDS（六甲基二硅嗪）供给到铝合金布线，以在铝合金布线的侧壁上形成疏水性分子层。

3. 发明授权

US5780908A Semiconductor apparatus with tungstein nitride 失效
标题翻译：具有氮化钨的半导体装置
公开(公告)号：US5780908A
公开(公告)日：1998-07-14
申请号：US751810
申请日：1996-11-19
申请人： Mitsuru Sekiguchi , Michinari Yamanaka
发明人： Mitsuru Sekiguchi , Michinari Yamanaka
IPC分类号： H01L21/285 , H01L21/768 , H01L23/532 , H01L29/45 , H01L23/02
CPC分类号： H01L21/76814 , H01L21/28568 , H01L21/76841 , H01L21/76849 , H01L21/76856 , H01L21/76864 , H01L23/53223 , H01L29/456 , H01L2924/0002 , Y10S257/924
摘要： Through exposure of the top surface of a tungsten film to plasma of a gas including nitrogen at a temperature of 550.degree. C. or less, a tungsten nitride layer having a structure in which nitrogen atoms and tungsten atoms are bonded is formed in an area in the vicinity of the surface of the tungsten film. Then, an aluminum alloy film is deposited on the tungsten film, thereby forming a metallic interconnection. Since the nitrogen atoms and the tungsten atoms are bonded in the tungsten nitride layer formed by such plasma nitridation, the tungsten nitric layer not only has a good barrier function to prevent the diffusion of other metal atoms but also can be formed in a small thickness. Accordingly, formation of an alloy layer with a high resistance otherwise caused due to counter diffusion during an annealing process and a junction leakage can be avoided.
摘要翻译：通过在550℃或更低的温度下将钨膜的顶表面暴露于包含氮气的气体的等离子体中，形成具有氮原子和钨原子结合的氮化钨层的区域钨膜表面附近。然后，在钨膜上沉积铝合金膜，从而形成金属互连。由于氮原子和钨原子结合在通过这种等离子体氮化形成的氮化钨层中，因此钨硝酸盐不仅具有良好的屏障功能，以防止其它金属原子的扩散，而且可以形成为小的厚度。因此，可以避免在退火处理期间由于反扩散而导致的具有高电阻的合金层的形成和结漏电。

4. 发明申请

US20070128871A1 Etching apparatus and etching method 审中-公开
标题翻译：蚀刻装置和蚀刻方法
公开(公告)号：US20070128871A1
公开(公告)日：2007-06-07
申请号：US11698870
申请日：2007-01-29
申请人： Michinari Yamanaka
发明人： Michinari Yamanaka
IPC分类号： C23F1/00 , H01L21/302
CPC分类号： H01J37/32082 , H01J37/32623 , H01J37/32642 , H01L21/31116 , H01L21/76802 , H01L21/76804
摘要： An etching apparatus includes a shield device provided on an electrode in a reaction chamber and surrounding an object to be etched. The shield device has a surface area according to an opening area ratio of the object to be etched.
摘要翻译：蚀刻装置包括设置在反应室中的电极上并围绕被蚀刻物体的屏蔽装置。屏蔽装置具有根据待蚀刻对象的开口面积比的表面积。

5. 发明授权

US07022619B2 Method for fabricating electronic device 失效
公开(公告)号：US07022619B2
公开(公告)日：2006-04-04
申请号：US10395182
申请日：2003-03-25
申请人： Michinari Yamanaka , Hiroshi Yuasa , Tetsuo Satake , Etsuyoshi Kobori , Takeshi Yamashita , Susumu Matsumoto
发明人： Michinari Yamanaka , Hiroshi Yuasa , Tetsuo Satake , Etsuyoshi Kobori , Takeshi Yamashita , Susumu Matsumoto
IPC分类号： H01L21/302 , H01L21/461 , H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76808 , H01L21/76826
摘要： After a hole is formed in a low dielectric constant film on a substrate, a protective film is formed on the wall surface of the hole or an electron acceptor is caused to be adsorbed by or implanted in the low dielectric constant film exposed at the wall surface of the hole. Otherwise, resist residue is left on the wall surface of the hole. Then, a resist pattern having an opening corresponding to a wire formation region including a region formed with the hole is formed by using a chemically amplified resist.

6. 发明授权

US06898851B2 Electronic device manufacturing method 失效
标题翻译：电子元件制造方法
公开(公告)号：US06898851B2
公开(公告)日：2005-05-31
申请号：US10717718
申请日：2003-11-21
申请人： Yasutaka Nishioka , Junjiro Sakai , Shingo Tomohisa , Susumu Matsumoto , Fumio Iwamoto , Michinari Yamanaka
发明人： Yasutaka Nishioka , Junjiro Sakai , Shingo Tomohisa , Susumu Matsumoto , Fumio Iwamoto , Michinari Yamanaka
IPC分类号： H01K3/10 , H01L21/768 , H05K3/10
CPC分类号： H01L21/76808 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165
摘要： It is an object to provide a semiconductor device having a buried multilayer wiring structure in which generation of a resolution defect of a resist pattern is suppressed and generation of a defective wiring caused by the resolution defect is reduced. After a via hole (7) reaching an etching stopper film (4) is formed, annealing is carried out at 300 to 400° C. with the via hole (7) opened. As an annealing method, it is possible to use both a method using a hot plate and a method using a heat treating furnace. In order to suppress an influence on a lower wiring (20) which has been manufactured, heating is carried out for a short time of approximately 5 to 10 minutes by using the hot plate. Consequently, a by-product staying in an interface of an upper protective film (6) and an interlayer dielectric film (5) having a low dielectric constant and a by-product staying in an interface of the etching stopper film (4) and the interlayer dielectric film (5) having a low dielectric constant are discharged so that an amount of the residual by-product can be decreased.
摘要翻译：本发明的目的是提供一种具有掩埋多层布线结构的半导体器件，其中抗蚀剂图案的分辨率缺陷的产生被抑制，并且由分辨率缺陷引起的缺陷布线的产生减少。在形成到达蚀刻停止膜（4）的通孔（7）之后，在通孔（7）打开的情况下，在300〜400℃进行退火。作为退火方法，可以使用使用热板的方法和使用热处理炉的方法。为了抑制对制造的下布线（20）的影响，通过使用热板进行约5〜10分钟的短时间的加热。因此，残留在上部保护膜（6）和具有低介电常数的副产物残留在蚀刻阻挡膜（4）的界面上的层间电介质膜（5）的界面中的副产物和排出具有低介电常数的层间绝缘膜（5），从而可以减少残留副产物的量。

7. 发明授权

US6008124A Semiconductor device having improved lamination-structure reliability for buried layers, silicide films and metal films, and a method for forming the same 失效
标题翻译：具有提高掩埋层，硅化物膜和金属膜的层叠结构可靠性的半导体器件及其形成方法
公开(公告)号：US6008124A
公开(公告)日：1999-12-28
申请号：US804461
申请日：1997-02-21
申请人： Mitsuru Sekiguchi , Michinari Yamanaka
发明人： Mitsuru Sekiguchi , Michinari Yamanaka
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/768 , H01L23/485 , H01L29/45 , H01L29/49 , H01L21/425 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76876 , H01L21/28052 , H01L21/28518 , H01L21/76841 , H01L21/76843 , H01L21/76856 , H01L21/76858 , H01L23/485 , H01L29/41783 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66575 , H01L2924/0002 , Y10S438/918
摘要： After formation of a connection hole or before deposition of an insulator film, a semiconductor device is placed onto a cathode of a plasma generator. A surface of a metal silicide film such as a silicide of titanium is exposed to a plasma of a nitrogen-containing gas at 550 degrees centigrade or less. As a result of such processing, a barrier compound layer, composed of a compound of nitrogen, oxygen, metal and silicon, is formed at a near-surface region of the metal silicide film of the titanium silicide film. Thereafter, while forming a buried layer from material superior in step coverage such as an Al--Ti compound and an aluminum alloy, reaction between the metal silicide film and the buried layer in a later annealing treatment can be avoided without depositing a barrier metal such as a titanium nitride/nitride film in the connection hole. Accordingly, contact resistance, sheet resistance and junction leakage can be reduced and reliability can be improved.
摘要翻译：在形成连接孔之后或在沉积绝缘膜之前，将半导体器件放置在等离子体发生器的阴极上。金属硅化物膜如钛硅化物的表面在550摄氏度以下暴露于含氮气体的等离子体。作为这种处理的结果，在硅化钛膜的金属硅化物膜的近表面区域处形成由氮，氧，金属和硅的化合物构成的阻挡化合物层。此后，在由Al-Ti化合物和铝合金等阶梯覆盖性优异的材料形成掩埋层的情况下，可以避免在稍后的退火处理中金属硅化物膜与掩埋层之间的反应，而不会形成诸如连接孔中的氮化钛/氮化物膜。因此，可以降低接触电阻，薄层电阻和结漏电，提高可靠性。

8. 发明授权

US5928528A Plasma treatment method and plasma treatment system 失效
标题翻译：等离子体处理方法和等离子体处理系统
公开(公告)号：US5928528A
公开(公告)日：1999-07-27
申请号：US921896
申请日：1997-09-02
申请人： Masafumi Kubota , Shigenori Hayashi , Michinari Yamanaka , Kenji Harafuji
发明人： Masafumi Kubota , Shigenori Hayashi , Michinari Yamanaka , Kenji Harafuji
IPC分类号： C23C14/34 , C23C16/50 , C23C16/511 , C23C16/515 , C23F4/00 , H01J37/32 , H01L21/203 , H01L21/205 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/3213 , H05H1/16
CPC分类号： H01J37/32706 , H01L21/31116 , H01L21/32137
摘要： A reactive gas supplied to a chamber 1 is put into plasma by supplying radio frequency power to the chamber 1 intermittently or while repeating high and low levels alternately and a specimen A in the chamber 1 is treated by the plasma. A positive pulse-like bias voltage synchronized with a period in which the radio frequency power is not supplied or a period in which low-level power is supplied is applied to the specimen A for preventing charging.
摘要翻译：通过间歇地向腔室1提供射频功率或者交替地重复高低电平，并且通过等离子体处理腔室1中的样本A，将供给到腔室1的反应气体投入等离子体。与未提供射频功率的时段同步的正脉冲状偏置电压或供给低电平电力的期间被施加到用于防止充电的检体A。

9. 发明授权

US07852892B2 Semiconductor laser device and method for manufacturing the same 有权
标题翻译：半导体激光装置及其制造方法
公开(公告)号：US07852892B2
公开(公告)日：2010-12-14
申请号：US11571112
申请日：2006-01-12
申请人： Hiroyuki Hosoi , Kouji Makita , Michinari Yamanaka
发明人： Hiroyuki Hosoi , Kouji Makita , Michinari Yamanaka
IPC分类号： H01S5/00
CPC分类号： H01S5/223
摘要： A ridge stripe semiconductor laser device includes a first conductivity type cladding layer 103, an active layer 104, a second conductivity type first cladding layer 105, a second conductivity type second cladding layer 108 in a ridge-shaped stripe for confining light in a horizontal transverse direction, and a current blocking layer 107 formed in a region except for at least a part on a ridge that are disposed on a semiconductor substrate 102. In a cross-section perpendicular to a stripe direction of the ridge, each of both lateral surfaces of the ridge includes a first surface 118 that is substantially perpendicular to a surface of the semiconductor substrate and extends downward from an upper end of the ridge, and a second surface 119 that is formed of a substantially linear skirt portion inclined surface that is inclined obliquely downward to an outside of the ridge in a skirt portion of the ridge. The first surface and the second surface are connected directly, or connected via a third intermediate surface. A (111) plane of a semiconductor constituting the second cladding layer is exposed to the second surface. The present invention provides a high power semiconductor laser device with a high kink level and a low operating current.
摘要翻译：脊条半导体激光器件包括第一导电型包覆层103，有源层104，第二导电型第一包层105，脊形条纹中的第二导电型第二覆层108，用于将光限制在水平横向方向和形成在除了设置在半导体衬底102上的脊上的至少一部分之外的区域中的电流阻挡层107.在垂直于脊的条纹方向的横截面中，脊包括基本上垂直于半导体衬底的表面并从脊的上端向下延伸的第一表面118和由倾斜向下倾斜的大致直线的裙部倾斜表面形成的第二表面119 到脊的裙部的脊的外侧。第一表面和第二表面直接连接或经由第三中间表面连接。构成第二包层的半导体的（111）面暴露于第二表面。本发明提供具有高扭结电平和低工作电流的高功率半导体激光器件。

10. 发明授权

US06859023B2 Evaluation method for evaluating insulating film, evaluation device therefor and method for manufacturing evaluation device 失效
标题翻译：绝缘膜评价方法，评价装置及评价装置的制造方法
公开(公告)号：US06859023B2
公开(公告)日：2005-02-22
申请号：US10218485
申请日：2002-08-15
申请人： Michinari Yamanaka , Takayuki Yamada , Hiroaki Nakaoka , Takeshi Yamashita
发明人： Michinari Yamanaka , Takayuki Yamada , Hiroaki Nakaoka , Takeshi Yamashita
IPC分类号： H01L21/66 , G01R31/00 , H01L21/00 , H01L23/58
CPC分类号： H01L22/14
摘要： A method for evaluating an insulating film includes: a first step of forming an insulating film on a semiconductor substrate including a p-n junction therein; a second step of selectively forming an electrode pattern on the insulating film; a third step of forming a measurement electrode on the insulating film so as to be electrically insulated from the electrode pattern; and a fourth step of applying a measurement voltage between the measurement electrode and the semiconductor substrate via the insulating film and measuring a leakage current leaking through the p-n junction so as to evaluate a damage to the insulating film or the semiconductor substrate.
摘要翻译：一种用于评价绝缘膜的方法包括：在包括p-n结的半导体衬底上形成绝缘膜的第一步骤; 在绝缘膜上选择性地形成电极图案的第二步骤; 在所述绝缘膜上形成测量电极以与所述电极图案电绝缘的第三步骤; 以及通过绝缘膜在测量电极和半导体衬底之间施加测量电压并测量通过p-n结泄漏的漏电流以评估对绝缘膜或半导体衬底的损坏的第四步骤。

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