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    • 3. 发明授权
    • Complementary metal-insulator-semiconductor devices
    • 互补金属 - 绝缘体 - 半导体器件
    • US5585659A
    • 1996-12-17
    • US320690
    • 1994-10-11
    • Toshio KobayashiYukio OkazakiMasayasu MiyakeHiroshi InokawaTakashi Morimoto
    • Toshio KobayashiYukio OkazakiMasayasu MiyakeHiroshi InokawaTakashi Morimoto
    • H01L27/092H01L21/8238H01L29/02H01L29/78H01L29/76
    • H01L21/823842
    • A method for fabricating semiconductor devices wherein polysilicon gates for complementary-type field-effect semiconductor devices are formed of polysilicon to which impurity doped simultaneously to the polysilicon deposition; the both gates having the dual N.sup.+ /P.sup.+ polysilicon gate structure, so that the both N- and P-channel transistors are formed as the surface-channel type ones; and therefore, the off-characteristic, the short channel effect, and the controllability of threshold voltage are progressed. More specifically, N- and P-channel MISFETs are provided on a common semiconductor substrate (1); N-type polysilicon (9) doped with N-type impurity is adopted as the gate electrode for the N-channel MISFET; P-type polysilicon (8) doped with P-type impurity is adopted as the gate electrode for the P-channel MISFET; and a narrow region preventing the mutual diffusion of impurities is provided between portions of respective polysilicon.
    • 一种用于制造半导体器件的方法,其中用于互补型场效应半导体器件的多晶硅栅极由同时掺杂到多晶硅沉积的杂质的多晶硅形成; 两个门具有双N + / P +多晶硅栅极结构,使得N沟道晶体管和P沟道晶体管形成为表面沟道​​型晶体管; 因此,进行关闭特性,短通道效应和阈值电压的可控性。 更具体地,在公共半导体衬底(1)上提供N沟道和P沟道MISFET。 采用N型杂质掺杂的N型多晶硅(9)作为N沟道MISFET的栅电极; 采用掺杂有P型杂质的P型多晶硅(8)作为P沟道MISFET的栅电极; 并且在各个多晶硅的部分之间设置防止杂质相互扩散的窄区域。
    • 6. 发明授权
    • Method for fabricating CMOS semiconductor devices
    • 制造CMOS半导体器件的方法
    • US5382532A
    • 1995-01-17
    • US946080
    • 1992-09-16
    • Toshio KobayashiYukio OkazakiMasayasu MiyakeHiroshi InokawaTakashi Morimoto
    • Toshio KobayashiYukio OkazakiMasayasu MiyakeHiroshi InokawaTakashi Morimoto
    • H01L27/092H01L21/8238H01L29/02H01L29/78H01L21/265
    • H01L21/823842
    • A method for fabricating semiconductor devices wherein polysilicon gates for complementary-type field-effect semiconductor devices are formed of polysilicon to which impurity doped simultaneously to the polysilicon deposition; the both gates having the dual N.sup.+ /P.sup.+ polysilicon gate structure, so that the both N- and P-channel transistors are formed as the surface-channel type ones; and therefore, the off-characteristic, the short channel effect, and the controllability of threshold voltage are progressed. More specifically, N- and P-channel MISFETs are provided on a common semiconductor substrate (1); N-type polysilicon (9) doped with N-type impurity is adopted as the gate electrode for the N-channel MISFET; P-type polysilicon (8) doped with P-type impurity is adopted as the gate electrode for the P-channel MISFET; and a narrow region preventing the mutual diffusion of impurities is provided between portions of respective polysilicon.
    • 一种用于制造半导体器件的方法,其中用于互补型场效应半导体器件的多晶硅栅极由同时掺杂到多晶硅沉积的杂质的多晶硅形成; 两个门具有双N + / P +多晶硅栅极结构,使得N沟道晶体管和P沟道晶体管形成为表面沟道​​型晶体管; 因此,进行关闭特性,短通道效应和阈值电压的可控性。 更具体地,在公共半导体衬底(1)上提供N沟道和P沟道MISFET。 采用N型杂质掺杂的N型多晶硅(9)作为N沟道MISFET的栅电极; 采用掺杂有P型杂质的P型多晶硅(8)作为P沟道MISFET的栅电极; 并且在各个多晶硅的部分之间设置防止杂质相互扩散的窄区域。