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1. 发明授权

US08969944B2 Semiconductor integrated circuit and method of producing the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US08969944B2
公开(公告)日：2015-03-03
申请号：US13697905
申请日：2011-05-13
申请人： Tetsuo Endoh , Seo Moon-Sik
发明人： Tetsuo Endoh , Seo Moon-Sik
IPC分类号： H01L29/792
CPC分类号： H01L27/11556 , G11C16/0425 , G11C16/0433 , G11C16/0483 , H01L27/088 , H01L27/11524 , H01L27/11551 , H01L29/42328 , H01L29/66477 , H01L29/66825 , H01L29/7883 , H01L29/7889
摘要： Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method of producing the semiconductor integrated circuit. A memory cell 1 in the semiconductor integrated circuit is provided with: a semiconductor pillar 2 that serves as a channel; a floating gate 5 that circumferentially covers the semiconductor pillar 2 via a tunnel insulation layer 6 on the outer circumference of the semiconductor pillar 2; and a control gate 4 that circumferentially covers the semiconductor pillar via an insulating layer 8 on the outer circumference of the semiconductor pillar 2, and that circumferentially covers the floating gate 5 via an insulating layer 7 on the outer circumference of the floating gate.
摘要翻译：提供了一种半导体集成电路，其使用在电池之间没有干扰的新颖的垂直MOS晶体管，其能够使短沟道效应最小化，不具有热电子注入，并且不需要形成浅结。还提供了一种制造半导体集成电路的方法。半导体集成电路中的存储单元1设置有：作为通道的半导体柱2; 通过半导体柱2的外周上的隧道绝缘层6周向地覆盖半导体柱2的浮动栅极5; 以及通过半导体柱2的外周上的绝缘层8周向地覆盖半导体柱的控制栅极4，并且经由浮动栅极的外周上的绝缘层7周向地覆盖浮置栅极5。

2. 发明申请

US20130119452A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF PRODUCING THE SAME 有权
公开(公告)号：US20130119452A1
公开(公告)日：2013-05-16
申请号：US13697905
申请日：2011-05-13
申请人： Tetsuo Endoh , Seo Moon-Sik
发明人： Tetsuo Endoh , Seo Moon-Sik
IPC分类号： H01L27/088 , H01L29/66
CPC分类号： H01L27/11556 , G11C16/0425 , G11C16/0433 , G11C16/0483 , H01L27/088 , H01L27/11524 , H01L27/11551 , H01L29/42328 , H01L29/66477 , H01L29/66825 , H01L29/7883 , H01L29/7889
摘要： Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method of producing the semiconductor integrated circuit. A memory cell 1 in the semiconductor integrated circuit is provided with: a semiconductor pillar 2 that serves as a channel; a floating gate 5 that circumferentially covers the semiconductor pillar 2 via a tunnel insulation layer 6 on the outer circumference of the semiconductor pillar 2; and a control gate 4 that circumferentially covers the semiconductor pillar via an insulating layer 8 on the outer circumference of the semiconductor pillar 2, and that circumferentially covers the floating gate 5 via an insulating layer 7 on the outer circumference of the floating gate.

3. 发明申请

US20100283097A1 MOS SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译： MOS半导体存储器件
公开(公告)号：US20100283097A1
公开(公告)日：2010-11-11
申请号：US12665534
申请日：2008-06-20
申请人： Tetsuo Endoh , Masayuki Kohno , Tatsuo Nishita , Minoru Honda , Toshio Nakanishi , Yoshihiro Hirota
发明人： Tetsuo Endoh , Masayuki Kohno , Tatsuo Nishita , Minoru Honda , Toshio Nakanishi , Yoshihiro Hirota
IPC分类号： H01L27/115 , H01L29/792
CPC分类号： H01L29/792 , C23C16/308 , C23C16/345 , G11C11/5628 , G11C16/0466 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/4234 , H01L29/513 , H01L29/7926
摘要： The invention provides a MOS semiconductor memory device that achieves excellent data retention characteristics while also achieving high-speed data write performance, low-power operation performance, and high reliability. A MOS semiconductor memory device 601 includes a first insulating film 111 and fifth insulating film 115 having large bandgaps 111a and 115a, a third insulating film 113 having the smallest bandgap 113a, and a second insulating film 112 and fourth insulating film 114 interposed between the third insulating film 113 and the first and fifth insulating films 111 and 115, respectively, and having intermediate bandgaps 112a and 114a.
摘要翻译：本发明提供一种实现优异的数据保持特性的MOS半导体存储器件，同时还实现了高速数据写入性能，低功率操作性能和高可靠性。 MOS半导体存储器件601包括具有较大带隙111a和115a的第一绝缘膜111和第五绝缘膜115，具有最小带隙113a的第三绝缘膜113和介于第三绝缘膜113之间的第二绝缘膜112和第四绝缘膜114。绝缘膜113和第一和第五绝缘膜111和115，并具有中间带隙112a和114a。

4. 发明授权

US06870215B2 Semiconductor memory and its production process 有权
标题翻译：半导体存储器及其生产过程
公开(公告)号：US06870215B2
公开(公告)日：2005-03-22
申请号：US10175259
申请日：2002-06-20
申请人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Noboru Takeuchi , Yoshihisa Wada , Kota Sato , Kazushi Kinoshita
发明人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Noboru Takeuchi , Yoshihisa Wada , Kota Sato , Kazushi Kinoshita
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H10L27/108
CPC分类号： H01L27/11553 , G11C16/0483 , H01L27/115
摘要： A semiconductor memory comprises: a first conductivity type semiconductor substrate and memory cells each constituted of an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein the memory cells are disposed in series, and the island-like semiconductor layer on which the memory cells are disposed has cross-sectional areas in a horizontal direction which vary stepwise.
摘要翻译：半导体存储器包括：第一导电型半导体衬底和各自由岛状半导体层，电荷存储层和控制栅极构成的存储单元，电荷存储层和控制栅极形成为完全或部分地环绕侧壁岛状半导体层，其中存储单元串联布置，并且其上设置有存储单元的岛状半导体层具有沿水平方向的横截面积，其逐步变化。

5. 发明授权

US06727544B2 Semiconductor memory including cell(s) with both charge storage layer(s) and control gate laterally surrounding island-like semiconductor layer 有权
标题翻译：半导体存储器包括具有两个电荷存储层的电池和控制栅极横向周围的岛状半导体层
公开(公告)号：US06727544B2
公开(公告)日：2004-04-27
申请号：US10107380
申请日：2002-03-28
申请人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Noboru Takeuchi
发明人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Noboru Takeuchi
IPC分类号： H01L29788
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： A semiconductor memory comprises: a substrate; and one or more memory cells constituted of at least one island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate and has an insulating film allowing an electric charge to pass at least in a part of a region between the charge storage layer and the island-like semiconductor layer.
摘要翻译：半导体存储器包括：衬底; 以及由至少一个岛状半导体层，电荷存储层和控制栅极构成的一个或多个存储单元，电荷存储层和控制栅极被形成为完全或部分地环绕岛状半导体层的侧壁，其中所述一个或多个存储单元中的至少一个与所述半导体衬底电绝缘，并且具有允许电荷至少在所述电荷存储层和岛状半导体层之间的区域的一部分通过的绝缘膜。

6. 发明授权

US5602789A Electrically erasable and programmable non-volatile and multi-level memory systemn with write-verify controller 失效
标题翻译：具有写入验证控制器的电可擦除和可编程的非易失性和多级存储器系统
公开(公告)号：US5602789A
公开(公告)日：1997-02-11
申请号：US518024
申请日：1995-08-22
申请人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
发明人： Tetsuo Endoh , Riichiro Shirota , Kazunori Ohuchi , Ryouhei Kirisawa , Seiichi Aritome , Tomoharu Tanaka , Yoshiyuki Tanaka
IPC分类号： G11C11/56 , G11C16/34 , G11C29/50 , G01R31/28
CPC分类号： G11C16/3418 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/3404 , G11C16/3413 , G11C16/3431 , G11C16/3459 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/0403 , G11C2211/5621
摘要： An EEPROM for storing multi-level data includes a memory cell array in which electrically erasable and programmable memory cells are arranged in matrix and each of the memory cells has at least three storage states, a write circuit for writing data to the memory cells, first and second write verify means each constituted of a sense amplifier, a data latch circuit and a detection circuit, for verifying an insufficient-written state of a memory cell and an excess-written state of a memory cell, respectively, an additional write circuit for additionally writing data to the memory cell in the insufficient-written state, and an additional erase circuit for additionally erasing data from the memory cell in the excess-written state.
摘要翻译：用于存储多级数据的EEPROM包括存储单元阵列，其中电可擦除可编程存储器单元被排列成矩阵，并且每个存储单元具有至少三个存储状态，第一存储单元写入数据的写入电路以及分别由读出放大器，数据锁存电路和检测电路构成的第二写入验证装置，用于分别验证存储器单元的写入不足状态和存储单元的过量写入状态，附加写入电路在写入状态不足的情况下向存储器单元写入数据，以及附加擦除电路，用于在超量写入状态下从存储单元附加擦除数据。

7. 发明授权

US06188611B1 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06188611B1
公开(公告)日：2001-02-13
申请号：US09408441
申请日：1999-09-29
申请人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
发明人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/12 , G11C16/3445 , G11C16/3459 , G11C16/3468 , G11C16/3477 , G11C16/3486 , G11C2211/5621
摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

8. 发明授权

US5895949A Semiconductor device having inversion inducing gate 失效
标题翻译：具有反向感应门的半导体器件
公开(公告)号：US5895949A
公开(公告)日：1999-04-20
申请号：US879790
申请日：1997-06-20
申请人： Tetsuo Endoh
发明人： Tetsuo Endoh
IPC分类号： G11C16/04 , H01L27/115 , H01L29/423 , H01L29/76
CPC分类号： H01L27/115 , G11C16/0483 , H01L29/42324
摘要： A semiconductor device is characterized by comprising a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a plurality of cell transistors each having a control gate formed on the semiconductor substrate through the first insulating film, a second insulating film formed on upper and side surfaces of the control gate, and a conductive film formed on at least the side surface of the control gate through the second insulating film.
摘要翻译：半导体器件的特征在于包括半导体衬底，形成在半导体衬底上的第一绝缘膜，多个单元晶体管，每个单元晶体管具有通过第一绝缘膜形成在半导体衬底上的控制栅极，第二绝缘膜形成在上部和控制栅极的侧表面和通过第二绝缘膜形成在至少控制栅极的侧表面上的导电膜。

9. 发明授权

US5824583A Non-volatile semiconductor memory and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US5824583A
公开(公告)日：1998-10-20
申请号：US949819
申请日：1997-10-14
申请人： Masamichi Asano , Hiroshi Iwahashi , Ryouhei Kirisawa , Ryozo Nakayama , Satoshi Inoue , Riichiro Shirota , Tetsuo Endoh , Fujio Masuoka
发明人： Masamichi Asano , Hiroshi Iwahashi , Ryouhei Kirisawa , Ryozo Nakayama , Satoshi Inoue , Riichiro Shirota , Tetsuo Endoh , Fujio Masuoka
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11519 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.
摘要翻译：本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。浮动栅极部分地覆盖沟道区域。因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。多个存储单元串联连接以构成基本块。相邻的基本块由增强型MOS晶体管分开。在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。

10. 发明授权

US5523980A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5523980A
公开(公告)日：1996-06-04
申请号：US364990
申请日：1994-12-28
申请人： Koji Sakui , Hiroshi Nakamura , Tomoharu Tanaka , Masaki Momodomi , Fujio Masuoka , Kazunori Ohuchi , Tetsuo Endoh
发明人： Koji Sakui , Hiroshi Nakamura , Tomoharu Tanaka , Masaki Momodomi , Fujio Masuoka , Kazunori Ohuchi , Tetsuo Endoh
IPC分类号： G11C16/06 , G11C8/12 , G11C16/02 , G11C16/04 , G11C29/00 , G11C29/34 , H01L29/78 , G11C8/00
CPC分类号： G11C8/12 , G11C16/0483
摘要： A NAND-cell type EEPROM having a plurality of bit lines, a plurality of control gate lines intersecting with the bit lines, and a plurality of memory cells driven by applying a potential to the control gate lines for selectively storing data, supplying data to the bit lines and receiving data therefrom. The memory cells form a plurality of cell units. The memory cells constituting each cell unit are connected in series to one bit line by a common selecting gate transistor. A plurality of data latch circuits are provided on the bit lines, respectively, for storing data to be written into the memory cells selected by the control gate lines. Further, a plurality of selecting gate drivers are provided to correspond to the cell units, respectively, for driving the control gate lines. A row decoder decodes row addresses for driving the selecting gate drivers and the control gate lines. A plurality of block-address latch circuits are provided to correspond to the selecting gate drivers, respectively, for temporarily storing signals derived from a row address by the row decoder, thereby to select at least two of the selecting gate drivers at the same time in order to write data.
摘要翻译：具有多个位线的NAND单元型EEPROM，与位线相交的多个控制栅极线，以及通过向控制栅极线施加电位而驱动的多个存储单元，用于选择性地存储数据，向位线和从其接收数据。存储单元形成多个单元单元。构成每个单元单元的存储单元通过公共选择栅极晶体管串联连接到一个位线。分别在位线上提供多个数据锁存电路，用于存储要写入由控制栅极线选择的存储单元的数据。此外，分别提供多个选择栅极驱动器以对应于用于驱动控制栅极线的单元单元。行解码器解码用于驱动选择栅极驱动器和控制栅极线的行地址。提供多个块地址锁存电路以分别对应于选择栅极驱动器，用于临时存储由行解码器从行地址导出的信号，从而同时选择至少两个选择栅极驱动器命令写数据。

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