专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5946231A Non-volatile semiconductor memory device 失效
公开(公告)号：US5946231A
公开(公告)日：1999-08-31
申请号：US72664
申请日：1998-05-05
申请人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
发明人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
IPC分类号： G11C11/56 , G11C16/08 , G11C16/12 , G11C16/34 , G11C7/00
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/12 , G11C16/3445 , G11C16/3459 , G11C16/3468 , G11C16/3477 , G11C16/3486 , G11C2211/5621
摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.

2. 发明授权

US6014330A Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US6014330A
公开(公告)日：2000-01-11
申请号：US167969
申请日：1998-10-08
申请人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
发明人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
IPC分类号： G11C11/56 , G11C16/08 , G11C16/12 , G11C16/34 , G11C7/00
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/12 , G11C16/3445 , G11C16/3459 , G11C16/3468 , G11C16/3477 , G11C16/3486 , G11C2211/5621
摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

3. 发明授权

US5774397A Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined state 失效
标题翻译：非易失性半导体存储器件以及将非易失性存储器单元编程到预定状态的方法
公开(公告)号：US5774397A
公开(公告)日：1998-06-30
申请号：US711652
申请日：1996-09-10
申请人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
发明人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
IPC分类号： G11C11/56 , G11C16/08 , G11C16/12 , G11C16/34 , G11C7/00
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/12 , G11C16/3445 , G11C16/3459 , G11C16/3468 , G11C16/3477 , G11C16/3486 , G11C2211/5621
摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

4. 发明授权

US5555204A Non-volatile semiconductor memory device 失效
标题翻译： Eeprom用于使用隧道电流写入和擦除数据。
公开(公告)号：US5555204A
公开(公告)日：1996-09-10
申请号：US266633
申请日：1994-06-28
申请人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
发明人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
IPC分类号： G11C11/56 , G11C16/08 , G11C16/12 , G11C16/34 , G11C16/02
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/12 , G11C16/3445 , G11C16/3459 , G11C16/3468 , G11C16/3477 , G11C16/3486 , G11C2211/5621
摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

5. 发明授权

US06188611B1 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06188611B1
公开(公告)日：2001-02-13
申请号：US09408441
申请日：1999-09-29
申请人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
发明人： Tetsuo Endoh , Yoshiyuki Tanaka , Seiichi Aritome , Riichiro Shirota , Susumu Shuto , Tomoharu Tanaka , Gertjan Hemink , Toru Tanzawa
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/08 , G11C16/12 , G11C16/3445 , G11C16/3459 , G11C16/3468 , G11C16/3477 , G11C16/3486 , G11C2211/5621
摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.
摘要翻译：非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的表面区域中的源极和漏极区的存储单元，以及第一栅极绝缘膜，电荷存储层，第二栅极绝缘膜和所述存储单元能够通过在所述电荷存储层和所述半导体衬底之间交换电荷来电数据重写，以及用于向所述半导体衬底施加高电位的装置和用于所述控制的中间电位的装置栅极处于第一数据擦除操作中，并且在第二次和随后的数据擦除操作中向半导体衬底施加高电位并将低电位施加到控制栅极，由此从电荷存储层去除电子。

6. 再颁专利

USRE42120E1 Multi-state EEPROM having write-verify control circuit 有权
标题翻译：具有写入验证控制电路的多状态EEPROM
公开(公告)号：USRE42120E1
公开(公告)日：2011-02-08
申请号：US11451590
申请日：2006-06-13
申请人： Tomoharu Tanaka , Gertjan Hemink
发明人： Tomoharu Tanaka , Gertjan Hemink
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation. A write operation, a write verify operation, and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until the memory cells are set in predetermined written states.
摘要翻译：一种具有存储单元阵列的EEPROM，其中电可编程存储器单元以矩阵形式布置，并且每个存储单元具有三个存储状态，包括用于临时存储用于控制多个存储单元的写入操作状态的数据的多个数据电路，用于根据分别对应于存储单元的数据电路的内容执行写入操作的写入电路，用于确认在写入操作时设置的存储单元的状态的写入验证电路，以及用于更新基于数据电路的内容和在写入操作时设置的存储单元的状态，仅对仅写入数据的存储单元执行重写操作的数据电路的内容。重复执行基于数据电路的内容的写入操作，写入验证操作和数据电路内容更新操作，直到存储器单元被设置为预定的写入状态。

7. 再颁专利

USRE41485E1 Multi-state EEPROM having write-verify control circuit 有权
公开(公告)号：USRE41485E1
公开(公告)日：2010-08-10
申请号：US11451587
申请日：2006-06-13
申请人： Tomoharu Tanaka , Gertjan Hemink
发明人： Tomoharu Tanaka , Gertjan Hemink
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation. A write operation, a write verify operation, and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until the memory cells are set in predetermined written states.

8. 再颁专利

USRE41020E1 Multi-state EEPROM having write-verify control circuit 有权
标题翻译：具有写入验证控制电路的多状态EEPROM
公开(公告)号：USRE41020E1
公开(公告)日：2009-12-01
申请号：US11451586
申请日：2006-06-13
申请人： Tomoharu Tanaka , Gertjan Hemink
发明人： Tomoharu Tanaka , Gertjan Hemink
IPC分类号： G11C16/24 , G11C16/26
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation. A write operation, a write verify operation, and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until the memory cells are set in predetermined written states.
摘要翻译：一种具有存储单元阵列的EEPROM，其中电可编程存储器单元以矩阵形式布置，并且每个存储单元具有三个存储状态，包括用于临时存储用于控制多个存储单元的写入操作状态的数据的多个数据电路，用于根据分别对应于存储单元的数据电路的内容执行写入操作的写入电路，用于确认在写入操作时设置的存储单元的状态的写入验证电路，以及用于更新基于数据电路的内容和在写入操作时设置的存储单元的状态，仅对仅写入数据的存储单元执行重写操作的数据电路的内容。重复执行基于数据电路的内容的写入操作，写入验证操作和数据电路内容更新操作，直到存储器单元被设置为预定的写入状态。

9. 再颁专利

USRE41021E1 Multi-state EEPROM having write-verify control circuit 有权
公开(公告)号：USRE41021E1
公开(公告)日：2009-12-01
申请号：US11451588
申请日：2006-06-13
申请人： Tomoharu Tanaka , Gertjan Hemink
发明人： Tomoharu Tanaka , Gertjan Hemink
IPC分类号： G11C16/34
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation. A write operation, a write verify operation, and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until the memory cells are set in predetermined written states.

10. 再颁专利

USRE41019E1 Multi-state EEPROM having write-verify control circuit 有权
公开(公告)号：USRE41019E1
公开(公告)日：2009-12-01
申请号：US11451589
申请日：2006-06-13
申请人： Tomoharu Tanaka , Gertjan Hemink
发明人： Tomoharu Tanaka , Gertjan Hemink
IPC分类号： G11C16/26
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation. A write operation, a write verify operation, and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until the memory cells are set in predetermined written states.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式