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    • 4. 发明授权
    • Semiconductor device and process for manufacturing the same
    • 半导体装置及其制造方法
    • US4557036A
    • 1985-12-10
    • US479135
    • 1983-03-25
    • Hakaru KyuragiHideo Oikawa
    • Hakaru KyuragiHideo Oikawa
    • H01L21/285H01L21/768H01L23/485H01L21/28
    • H01L21/28512H01L21/76801H01L21/76825H01L21/76828H01L21/76834H01L23/485H01L2924/0002Y10S148/103Y10S148/105
    • A multilayer structure comprising a Si layer/ a refractory metal oxide layer/ a refractory metal layer/ is subjected to annealing in an atmosphere of hydrogen or an inert gas mixed with hydrogen, thereby converting the multilayer structure into a multilayer structure comprising a Si layer/an inner SiO.sub.2 layer formed by internal oxidation of Si/a refractory metal layer. The inner SiO.sub.2 layer is selectively formed only on the surface of the refractory metal layer, since Si is internally oxidized from the side of the refractory metal layer. In case of gate electrode of a MISFET, the gate electrode and a contact hole for source or drain electrode are positioned in self-alignment with each other via the inner SiO.sub.2 layer. The distance between the gate electrode and the source or drain electrode is determined by the thickness of the inner SiO.sub.2 layer. A semiconductor device with a high density and a high speed is realized.
    • 包含Si层/难熔金属氧化物层/难熔金属层的多层结构在氢气或与氢气混合的惰性气体气氛中进行退火,由此将多层结构转化为包括Si层/ 通过Si / a难熔金属层的内部氧化形成的内部SiO 2层。 内部SiO 2层仅选择性地形成在难熔金属层的表面上,因为Si从难熔金属层的一侧内部被氧化。 在MISFET的栅电极的情况下,栅电极和源电极或漏电极的接触孔经由内部SiO 2层彼此自对准。 栅极电极和源极或漏极之间的距离由内部SiO 2层的厚度决定。 实现了高密度和高速度的半导体器件。
    • 7. 发明授权
    • Thin film forming apparatus and method
    • 薄膜成膜装置及方法
    • US4732761A
    • 1988-03-22
    • US842244
    • 1986-03-21
    • Katsuyuki MachidaHideo Oikawa
    • Katsuyuki MachidaHideo Oikawa
    • H01L21/205C23C14/35C23C16/40C23C16/48C23C16/511H01L21/302H01L21/3065H01L21/31H01L21/3105H01L21/768B05D5/12
    • C23C16/48C23C14/357C23C16/402C23C16/511H01L21/31051H01L21/31055H01L21/76819
    • An apparatus for forming a thin film to planarize a surface of a semiconductor device having convex and concave regions, comprising a plasma generating chamber into which are an Ar gas and an O.sub.2 gas are supplied so that a plasma is produced; a specimen chamber in which a substrate electrode upon which a specimen substrate is placed and which is in partial communication with the plasma generating chamber and into which an SiH.sub.4 gas as a film material is introduced; and a bias power source for applying a bias voltage to the substrate electrode so that ions sufficiently impinge substantially vertically upon the electrode to perform ion etching. First, an SiO.sub.2 film is deposited on the specimen substrate by using the O.sub.2 and SiH.sub.4 gases. In the next step, Ar plasma and O.sub.2 plasma are produced in the plasma generating chamber and a bias voltage is applied to the substrate electrode. As a result, deposition and etching occur simultaneously, whereby the surface of the device having convex and concave regions is planarized with an SiO.sub.2 film. Submicron interconnections can be planarized with easily setting planarization conditions at a low rf power. The planarization time can be shortened.
    • 一种用于形成薄膜以平坦化具有凸和凹区域的半导体器件的表面的装置,包括其中供给有Ar气体和O 2气体的等离子体产生室,从而产生等离子体; 试样室,其中放置有试样基板并与等离子体发生室部分连通的基板电极,并且引入作为膜材料的SiH 4气体; 以及偏置电源,用于向衬底电极施加偏置电压,使得离子充分地基本垂直地撞击在电极上以进行离子蚀刻。 首先,使用O 2和SiH 4气体在样品基板上沉积SiO 2膜。 在下一步骤中,在等离子体发生室中产生Ar等离子体和O 2等离子体,并且将偏置电压施加到衬底电极。 结果,沉积和蚀刻同时发生,由此具有凸区域的器件的表面被SiO 2膜平坦化。 亚微米互连可以平坦化,容易设置低功率的平坦化条件。 可以缩短平坦化时间。