专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4985368A Method for making semiconductor device with no stress generated at the trench corner portion 失效
标题翻译：制造在沟槽角部处产生应力的半导体器件的方法
公开(公告)号：US4985368A
公开(公告)日：1991-01-15
申请号：US429528
申请日：1989-10-31
申请人： Tatsuya Ishii , Yoshinori Okumura , Masao Nagatomo
发明人： Tatsuya Ishii , Yoshinori Okumura , Masao Nagatomo
IPC分类号： H01L27/04 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10829 , H01L29/66181 , Y10S257/911
摘要： The semiconductor device in which no stress occurs at the corner portion of the trench comprises a p type semiconductor substrate having a trench and a main surface, a thick insulating film formed on the bottom portion of the trench, a thin insulating film formed on the sidewall portion of the trench and connected to the end portion of the thick insulating film, and an n type impurity region formed in the semiconductor substrate only on the side portion of the thin insulating film.

2. 发明授权

US4894695A Semiconductor device with no stress generated at the trench corner portion and the method for making the same 失效
标题翻译：在沟槽角部分没有产生应力的半导体器件及其制造方法
公开(公告)号：US4894695A
公开(公告)日：1990-01-16
申请号：US169062
申请日：1988-03-17
申请人： Tatsuya Ishii , Yoshinori Okumura , Masao Nagatomo
发明人： Tatsuya Ishii , Yoshinori Okumura , Masao Nagatomo
IPC分类号： H01L27/04 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10829 , H01L29/66181 , Y10S257/911
摘要： The semiconductor device in which no stress occurs at the corner portion of the trench comprises a p type semiconductor substrate having a trench and a main surface, a thick insulating film formed on the bottom portion of the trench, a thin insulating film formed on the sidewall portion of the trench and connected to the end portion of the thick insulating film, and an n type impurity region formed in the semiconductor substrate only on the side portion of the thin insulating film.
摘要翻译：在沟槽的角部没有发生应力的半导体器件包括具有沟槽和主表面的ap型半导体衬底，形成在沟槽底部的厚绝缘膜，形成在侧壁部分上的薄绝缘膜并且连接到厚绝缘膜的端部，并且仅在薄绝缘膜的侧部形成在半导体衬底中的n型杂质区。

3. 发明授权

US5164806A Element isolating structure of semiconductor device suitable for high density integration 失效
标题翻译：适用于高密度整合的半导体器件的元件隔离结构
公开(公告)号：US5164806A
公开(公告)日：1992-11-17
申请号：US698690
申请日：1991-05-13
申请人： Masao Nagatomo , Hiroki Shimano , Tomonori Okudaira , Yoshinori Okumura
发明人： Masao Nagatomo , Hiroki Shimano , Tomonori Okudaira , Yoshinori Okumura
IPC分类号： H01L21/265 , H01L21/336 , H01L21/762 , H01L21/765
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/76216 , H01L21/765 , H01L29/6656 , Y10S257/90
摘要： An element isolating structure employed for isolating the elements of a semiconductor substrate has an impurity region having a concentration lower than that of a source/drain and a channel stop region, between the source/drain of an MOS transistor formed in an active region, and the channel stop region formed under an LOCOS film.A field shield isolating structure has a low concentrated impurity region between the source/drain of an MOS transistor formed in the active region and the substrate surface region covered by a field shield electrode layer. The low concentrated impurity region improves its junction breakdown voltage in the boundary region with the element isolating region.An improved LOCOS film is formed into an amorphous region on the surface of the substrate by an oblique rotating ion implanting method, and the amorphous region is formed by thermal oxidation. The method suppresses the emergence of a bird's beak.
摘要翻译：用于隔离半导体衬底的元件的元件隔离结构具有在有源区中形成的MOS晶体管的源极/漏极之间具有低于源极/漏极和沟道截止区域的浓度的杂质区域和在LOCOS膜下形成的通道停止区域。场屏蔽隔离结构在有源区中形成的MOS晶体管的源极/漏极与由场屏蔽电极层覆盖的衬底表面区域之间具有低浓度杂质区域。低浓度杂质区域改善了与元件隔离区域的边界区域的结击穿电压。通过倾斜旋转离子注入方法将改进的LOCOS膜形成在衬底的表面上的非晶区域中，通过热氧化形成非晶区域。该方法抑制鸟喙的出现。

4. 发明授权

US5153689A Semiconductor memory device having bit lines formed of an interconnecting layer of lower reflectance material than the material of the word lines 失效
标题翻译：具有形成互连层的低位反射材料的位线的半导体存储器件与字线的材料
公开(公告)号：US5153689A
公开(公告)日：1992-10-06
申请号：US404528
申请日：1989-09-08
申请人： Yoshinori Okumura , Takayuki Matsukawa , Ikuo Ogoh , Masao Nagatomo , Hideki Genjo , Atsushi Hachisuka
发明人： Yoshinori Okumura , Takayuki Matsukawa , Ikuo Ogoh , Masao Nagatomo , Hideki Genjo , Atsushi Hachisuka
IPC分类号： H01L21/3205 , H01L21/8242 , H01L23/52 , H01L23/532 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10808 , H01L23/53257 , H01L2924/0002
摘要： A memory cell of a semiconductor memory device comprises one MOS transistor (3) and one stacked capacitor (4). One of the source/drain regions (8a, 8b) of the MOS transistor is connected to a bit line (2a, 2b). The bit line is formed from a contact portion to the source/drain regions of the MOS transistor to a portion above the stacked capacitor. The bit line is formed of a metal having high melting point, a silicide of a metal having high melting point or a polycide. Since this material has low reflectance against exposing light, the precision in patterning the interconnection is improved.
摘要翻译：半导体存储器件的存储单元包括一个MOS晶体管（3）和一个堆叠电容器（4）。 MOS晶体管的源极/漏极区域（8a，8b）之一连接到位线（2a，2b）。位线由MOS晶体管的源极/漏极区域到层叠电容器上方的部分的接触部分形成。位线由具有高熔点的金属，具有高熔点的金属的硅化物或多晶硅化物形成。由于该材料对于曝光具有低的反射率，因此提高了互连图形化的精度。

5. 发明授权

US4984055A Semiconductor device having a plurality of conductive layers and manufacturing method therefor 失效
标题翻译：具有多个导电层的半导体器件及其制造方法
公开(公告)号：US4984055A
公开(公告)日：1991-01-08
申请号：US267103
申请日：1988-11-07
申请人： Yoshinori Okumura , Atsuhiro Fujii , Masao Nagatomo , Hiroji Ozaki , Wataru Wakamiya , Takayuki Matsukawa
发明人： Yoshinori Okumura , Atsuhiro Fujii , Masao Nagatomo , Hiroji Ozaki , Wataru Wakamiya , Takayuki Matsukawa
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L23/522 , H01L27/10 , H01L27/108
CPC分类号： H01L23/485 , H01L23/522 , H01L2924/0002
摘要： A semiconductor device having a plurality of conductive layers is disclosed. The device has first level conductors (9) formed spaced apart on a semiconductor substrate (1). The semiconductor substrate (1) is provided with impurity diffusion regions (11) in its major surface between adjacent first level conductors (9). A triple layer insulation formed of a pair of oxide layers (12, 14) and an silicon oxide layer (13) sandwiched between the oxide layers (12, 14) covers the semiconductor substrate (1) and the first level conductors (9) thereon. At least one contact hole (15) is formed to extend through the triple layer insulation to either the impurity diffusion region (11) in the semiconductor substrate (1) or the first level conductor (9) on the semiconductor substrate (1). A second level conductor (16, 17) is provided on the triple layer insulation and on the inner surrounding wall of the contact hole (15). Each of the three insulating layers in the triple layer insulation has its hole-defining surface exposed at the contact hole (15) flush with or displaced laterally into the contact hole (15) away from a corresponding hole-defining exposed surface of the next overlying insulating layer.
摘要翻译：公开了具有多个导电层的半导体器件。该器件具有在半导体衬底（1）上间隔开形成的第一级导体（9）。半导体衬底（1）在相邻的第一层导体（9）之间的主表面上设置有杂质扩散区（11）。由一对氧化物层（12,14）和夹在氧化物层（12,14）之间的氧化硅层（13）形成的三层绝缘体覆盖在其上的半导体衬底（1）和第一层导体（9）。形成至少一个接触孔（15），以通过三层绝缘体延伸到半导体衬底（1）中的杂质扩散区域（11）或半导体衬底（1）上的第一级导体（9）中。在三层绝缘体和接触孔（15）的内周围壁上设置有二级导体（16,17）。三层绝缘体中的三个绝缘层中的每一个具有其露出在接触孔（15）处的孔限定表面，该接触孔（15）与接触孔（15）平齐地或相对地偏离接触孔（15），远离与下一个上覆的相应的孔限定的暴露表面绝缘层。

6. 发明授权

US4956692A Semiconductor device having an isolation oxide film 失效
标题翻译：具有隔离氧化膜的半导体器件
公开(公告)号：US4956692A
公开(公告)日：1990-09-11
申请号：US266704
申请日：1988-11-03
申请人： Hiroji Ozaki , Masahiro Yoneda , Ikuo Ogoh , Yoshinori Okumura , Wataru Wakamiya , Masao Nagatomo
发明人： Hiroji Ozaki , Masahiro Yoneda , Ikuo Ogoh , Yoshinori Okumura , Wataru Wakamiya , Masao Nagatomo
IPC分类号： H01L27/10 , H01L21/31 , H01L21/334 , H01L21/76 , H01L21/762 , H01L21/8242 , H01L27/108
CPC分类号： H01L29/66181 , H01L21/76205 , H01L27/10829
摘要： Two trenches are formed at a predetermined distance on a main surface of a semiconductor substrate. An oxide film and a nitride film are successively formed on the main surface of the semiconductor including the inner surfaces of the trenches. After a resist is formed over the whole surface including the inner surfaces of the trenches, the resist is patterned to expose a portion of the nitride film on a side surface of each trench. The exposed portions of the nitride film are removed by using the patterned resist as a mask and thermal oxidation is applied. Then, an isolation oxide film is formed on a region between the trenches and an end of a bird's beak is located on a side surface of each trench and is connected to the oxide film formed in each trench.
摘要翻译：在半导体衬底的主表面上以预定距离形成两个沟槽。在包括沟槽的内表面的半导体的主表面上依次形成氧化物膜和氮化物膜。在包括沟槽的内表面的整个表面上形成抗蚀剂之后，将抗蚀剂图案化以在每个沟槽的侧表面上暴露出氮化膜的一部分。通过使用图案化的抗蚀剂作为掩模去除氮化物膜的暴露部分并施加热氧化。然后，在沟槽之间的区域上形成隔离氧化膜，并且鸟嘴的端部位于每个沟槽的侧表面上并连接到形成在每个沟槽中的氧化膜。

7. 发明授权

US5300444A Method of manufacturing a semiconductor device having a stacked structure formed of polycrystalline silicon film and silicon oxide film 失效
标题翻译：制造具有由多晶硅膜和氧化硅膜形成的层叠结构的半导体器件的方法
公开(公告)号：US5300444A
公开(公告)日：1994-04-05
申请号：US693505
申请日：1991-04-30
申请人： Atsushi Hachisuka , Masao Nagatomo , Ikuo Ogoh , Hideki Genjou , Yoshinori Okumura , Takayuki Matsukawa
发明人： Atsushi Hachisuka , Masao Nagatomo , Ikuo Ogoh , Hideki Genjou , Yoshinori Okumura , Takayuki Matsukawa
IPC分类号： H01L21/316 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/265
CPC分类号： H01L27/10844 , H01L21/02164 , H01L21/02211 , H01L21/02271 , H01L21/31612 , H01L27/10808
摘要： A semiconductor memory device comprising memory cells having stacked capacitors has a stacked structure formed by the selective removal of a polycrystalline silicon film (15; 20) and a silicon oxide film (18a; 18), employing the same mask (14). A field effect transistor connected to a stacked capacitor has a gate electrode (20) formed of the above described polycrystalline silicon film. This polycrystalline silicon film (20) is formed on the major surface of a semiconductor substrate. The above described silicon oxide film (18) as an upper layer insulating film formed on the gate electrode (20) has a residual stress not more than 10.sup.9 dyn/cm.sup.2. No notches occur in the polycrystalline silicon film (20) in the process of selectively removing the polycrystalline silicon film (15) and the silicon oxide film (18a) deposited thereon, employing the same mask (14), thereby not decreasing the operation speed of the field effect transistor having the gate electrode (20) formed of the polycrystalline silicon film.
摘要翻译：包括具有堆叠电容器的存储单元的半导体存储器件具有通过选择性去除多晶硅膜（15; 20）和使用相同掩模（14）的氧化硅膜（18a; 18）而形成的堆叠结构。连接到堆叠电容器的场效应晶体管具有由上述多晶硅膜形成的栅电极（20）。该多晶硅膜（20）形成在半导体衬底的主表面上。作为形成在栅电极（20）上的上层绝缘膜的上述氧化硅膜（18）的残留应力为109dyn / cm 2以下。在使用相同的掩模（14）选择性地去除沉积在其上的多晶硅膜（15）和氧化硅膜（18a）的过程中，在多晶硅膜（20）中没有发生缺口，从而不会降低该场效应晶体管具有由多晶硅膜形成的栅电极（20）。

8. 发明授权

US5112771A Method of fibricating a semiconductor device having a trench 失效
标题翻译：具有TRENCH的半导体器件的制备方法
公开(公告)号：US5112771A
公开(公告)日：1992-05-12
申请号：US349737
申请日：1989-06-12
申请人： Tatsuya Ishii , Yoji Mashiko , Masao Nagatomo , Michihiro Yamada
发明人： Tatsuya Ishii , Yoji Mashiko , Masao Nagatomo , Michihiro Yamada
IPC分类号： H01L21/308 , H01L21/763 , H01L27/108 , H01L29/94 , H01L21/76
CPC分类号： H01L27/10829 , H01L21/3081 , H01L21/3086 , H01L21/763 , H01L29/945
摘要： A semiconductor device having a trench (30) comprises a semiconductor substrate (11), a plurality of elements (13) provided on the semiconductor substrate, a trench (30) provided between the elements and an insulating material (12) embedded in the trench for isolating the elements. The trench has its bottom portion region enlarged in both sides.The semiconductor device is manufactured by enlarging the bottom portion region of the trench by etching.
摘要翻译：具有沟槽（30）的半导体器件包括半导体衬底（11），设置在半导体衬底上的多个元件（13），设置在元件之间的沟槽（30）和嵌入沟槽中的绝缘材料（12）用于隔离元件。沟槽的底部区域在两侧均扩大。通过蚀刻扩大沟槽的底部区域来制造半导体器件。

9. 发明授权

US4763182A Semiconductor memory device with deep bit-line channel stopper 失效
标题翻译：具有深位线通道阻塞的半导体存储器件
公开(公告)号：US4763182A
公开(公告)日：1988-08-09
申请号：US941216
申请日：1986-12-12
申请人： Hiroji Ozaki , Shinichi Sato , Akira Tokui , Akira Kawai , Masayuki Nakajima , Masao Nagatomo
发明人： Hiroji Ozaki , Shinichi Sato , Akira Tokui , Akira Kawai , Masayuki Nakajima , Masao Nagatomo
IPC分类号： H01L27/10 , G11C11/34 , H01L21/74 , H01L21/8242 , H01L27/108 , H01L29/08 , H01L29/10 , H01L29/78
CPC分类号： H01L27/10844 , H01L21/74 , H01L27/10805 , H01L29/0847 , H01L29/1083
摘要： A semiconductor memory device comprises a first conductivity type semiconductor substrate (1) formed thereon with a charge storage region (5) and a second conductivity type region (6) serving as a bit line, and first conductivity type highly concentrated regions (8, 11) higher in concentration than the semiconductor substrate (1) at least by one digit are formed to enclose the charge storage region (5) and the bit line region (6) respectively. Thus, potential barriers against electrons can be defined in interfaces between the highly concentrated region (8) and the charge storage region (5) and between the highly concentrated region (11) and the bit line region (6), thereby to prevent malfunction caused by incidence of radioactive rays such as alpha rays.
摘要翻译：半导体存储器件包括形成有电荷存储区域（5）的第一导电型半导体衬底（1）和用作位线的第二导电类型区域（6），以及第一导电型高浓度区域（8,11 形成浓度高于半导体衬底（1）的至少一位数，以分别包围电荷存储区域（5）和位线区域（6）。因此，可以在高度集中区域（8）和电荷存储区域（5）之间以及高度集中区域（11）和位线区域（6）之间的界面中限定抵抗电子的势垒，从而防止故障通过放射线如α射线的发生。

10. 发明授权

US5323343A DRAM device comprising a stacked type capacitor and a method of manufacturing thereof 失效
标题翻译： DRAM器件包括堆叠型电容器及其制造方法
公开(公告)号：US5323343A
公开(公告)日：1994-06-21
申请号：US77971
申请日：1993-06-18
申请人： Ikuo Ogoh , Masao Nagatomo
发明人： Ikuo Ogoh , Masao Nagatomo
IPC分类号： H01L21/8242 , H01L27/105 , H01L27/108 , G11C11/24
CPC分类号： H01L27/10852 , H01L27/10808 , H01L27/105
摘要： A DRAM according to the present invention comprises a memory cell array having memory cells constituted by one transfer gate transistor (10) and a capacitor (11), and a peripheral circuit having a MOS transistor (45a) with the LDD structure. At least the source/drain region (19) connected to the capacitor of the transfer gate transistor is formed of a low concentration impurity region (19a). The low concentration impurity region has an impurity concentration substantially equal to that of the low concentration source/drain region (31) of the LDD MOS transistor of the peripheral circuit. The low concentration/drain region of the transfer gate transistor is formed by masking the surface thereof at the time of the high concentration ion implantation step for high concentration source/drain formation of the MOS transistor of the peripheral circuit. By omitting the high concentration ion implantation step, the substrate deficiency of the source/drain region of the transfer gate transistor is eliminated to suppress leakage of the charge from the capacitor.
摘要翻译：根据本发明的DRAM包括具有由一个传输栅极晶体管（10）和电容器（11）构成的存储单元的存储单元阵列和具有LDD结构的MOS晶体管（45a）的外围电路。至少连接到传输门晶体管的电容器的源极/漏极区域（19）由低浓度杂质区域（19a）形成。低浓度杂质区域的杂质浓度基本上等于外围电路的LDD MOS晶体管的低浓度源极/漏极区域（31）的杂质浓度。传输栅极晶体管的低浓度/漏极区域是通过在高浓度离子注入步骤时对其外围电路的MOS晶体管的高浓度源极/漏极形成的表面进行掩蔽来形成的。通过省略高浓度离子注入步骤，消除了传输栅晶体管的源极/漏极区的衬底缺陷，以抑制电荷从电容器的泄漏。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式