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1. 发明申请

US20150301892A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20150301892A1
公开(公告)日：2015-10-22
申请号：US14789090
申请日：2015-07-01
申请人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada
发明人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada
IPC分类号： G06F11/10 , G06F3/06
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/08 , G06F11/1012 , G06F11/1048 , G06F11/1666 , G11C29/42 , H03M13/19
摘要： A memory system comprises an encoding processing circuit 100 that performs redundant encoding process on target data Din to be written to thereby generate data RDin such that the number of bits having a predetermined value is half or less than the total number of bits, and a memory 120 to which the data RDin generated by the encoding processing circuit are written.
摘要翻译：存储器系统包括对要写入的目标数据Din进行冗余编码处理的编码处理电路100，从而生成数据RDin，使得具有预定值的位数是总位数的一半或更少，存储器写入由编码处理电路产生的数据RDin 120的数据。

2. 发明授权

US08429496B2 Semiconductor memory device and error correcting method 有权
标题翻译：半导体存储器件和纠错方法
公开(公告)号：US08429496B2
公开(公告)日：2013-04-23
申请号：US12360215
申请日：2009-01-27
申请人： Yutaka Yamada , Tatsunori Kanai
发明人： Yutaka Yamada , Tatsunori Kanai
IPC分类号： G11C29/00
CPC分类号： G06F11/1008 , G11C2029/0411
摘要： A decoding unit is arranged between a reading unit that reads data with an error correction code added from memory cells on a specific one of the first data lines and an output unit that selectively outputs certain data of the read out data. The decoding unit corrects any errors in the data read out by the reading unit in accordance with the error correction code. The data in which the errors are corrected by the decoding unit is written back in the memory cells on the specific first data line.
摘要翻译：解码单元设置在读取单元，其读取数据与从特定第一数据线上的存储单元相加的纠错码;以及输出单元，其选择性地输出读出数据的某些数据。解码单元根据纠错码纠正由读取单元读出的数据中的任何错误。由解码单元校正错误的数据被写回到特定第一数据线上的存储单元中。

3. 发明申请

US20120311405A1 CACHE MEMORY, COMPUTER SYSTEM AND MEMORY ACCESS METHOD 有权
标题翻译：高速缓存存储器，计算机系统和存储器访问方法
公开(公告)号：US20120311405A1
公开(公告)日：2012-12-06
申请号：US13584182
申请日：2012-08-13
申请人： Tatsunori Kanai , Yutaka Yamada
发明人： Tatsunori Kanai , Yutaka Yamada
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1064
摘要： A cache memory has a data holding unit, having multiple cache lines each of which includes an address area, a data area and a dirty bit, and a controller which is given read data and a correction execution signal indicating whether or not error correction has been performed for the read data, the read data has been read from a memory storing error-correction-coded data, which also stores address information corresponding to the read data into the address area of any one of the multiple cache lines, stores the read data into the data area, and sets a predetermine value as the dirty bit on the basis of the correction execution signal.
摘要翻译：高速缓冲存储器具有数据保持单元，具有多个高速缓存行，每条高速缓存行包括地址区，数据区和脏位，以及给予读取数据的控制器和指示是否已经进行错误校正的校正执行信号对于读取数据执行读取数据，从存储错误校正编码数据的存储器中读取读取数据，该存储器还将与读取数据相对应的地址信息存储到多个高速缓存行中的任一个的地址区域中，存储读取数据进入数据区域，并且基于校正执行信号将预定值设置为脏位。

4. 发明申请

US20110276858A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20110276858A1
公开(公告)日：2011-11-10
申请号：US13157396
申请日：2011-06-10
申请人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada
发明人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada
IPC分类号： H03M13/05 , G06F11/10 , G06F12/00
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/08 , G06F11/1012 , G06F11/1048 , G06F11/1666 , G11C29/42 , H03M13/19
摘要： A memory system comprises an encoding processing circuit 100 that performs redundant encoding process on target data Din to be written to thereby generate data RDin such that the number of bits having a predetermined value is half or less than the total number of bits, and a memory 120 to which the data RDin generated by the encoding processing circuit are written.
摘要翻译：存储器系统包括对要写入的目标数据Din进行冗余编码处理的编码处理电路100，从而生成数据RDin，使得具有预定值的位数是总位数的一半或者少于存储器写入由编码处理电路产生的数据RDin 120的数据。

5. 发明授权

US09105358B2 Memory system having an encoding processing circuit for redundant encoding process 有权
标题翻译：具有用于冗余编码处理的编码处理电路的存储器系统
公开(公告)号：US09105358B2
公开(公告)日：2015-08-11
申请号：US13157396
申请日：2011-06-10
申请人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada
发明人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada
IPC分类号： G06F11/16 , G06F11/10 , G11C29/04 , G11C29/42 , G06F11/08 , H03M13/19
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/08 , G06F11/1012 , G06F11/1048 , G06F11/1666 , G11C29/42 , H03M13/19
摘要： In one embodiment, a memory system for writing redundant data output by an encoding processing circuit, comprises a memory, a encoding processing circuit, and a decoding circuit. The memory is electrically rewritable by using memory cells. The memory cells are capable of having two different resistance values corresponding to logical values of 1 or 0 respectively. The redundant data is read from and a predetermined logical value is written to the memory by flowing current in a same direction. The encoding processing circuit performs redundant encoding processing on target data and outputs redundant data. A number of bits having the predetermined logical value exceeds a number of bits having the logical value other than the predetermined logical value, for writing the redundant data to the memory. A decoding circuit reads data from the memory, and performs a decoding process on the data.
摘要翻译：在一个实施例中，用于写入由编码处理电路输出的冗余数据的存储器系统包括存储器，编码处理电路和解码电路。存储器通过使用存储器单元进行电可重写。存储单元能够分别具有对应于逻辑值1或0的两个不同的电阻值。读取冗余数据，并且通过沿相同方向流动电流将预定的逻辑值写入存储器。编码处理电路对目标数据进行冗余编码处理，并输出冗余数据。具有预定逻辑值的位数超过具有除了预定逻辑值之外的逻辑值的比特数，用于将冗余数据写入存储器。解码电路从存储器读取数据，并对数据进行解码处理。

6. 发明授权

US09075742B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US09075742B2
公开(公告)日：2015-07-07
申请号：US13360989
申请日：2012-01-30
申请人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada , Hideki Yoshida
发明人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada , Hideki Yoshida
IPC分类号： G11C29/00 , G06F11/10 , G11C29/04
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.
摘要翻译：根据一个实施例，存储器件包括写数据位，用于纠错的校验位和开销位到存储器中的写入设备，每个比特组对应于每组比特组（ s）包括数据位和/或校验位的至少一位，开销位的每个位表示相应的位组是否已被反相，读取单元读取数据位，校验位，以及来自存储器的开销位，校正单元，其基于校验位校正从存储器读取的数据位和开销位中的错误，以及反相单元，其将包含在存储器中的数据位反相所述比特组对应于所述开销比特，并且当所述经纠错的开销比特指示已经执行了反转时，将所述反相的数据比特作为从所述存储器读取的数据输出。

7. 发明授权

US08381072B2 Cache memory, computer system and memory access method 有权
标题翻译：缓存，计算机系统和内存访问方式
公开(公告)号：US08381072B2
公开(公告)日：2013-02-19
申请号：US13584182
申请日：2012-08-13
申请人： Tatsunori Kanai , Yutaka Yamada
发明人： Tatsunori Kanai , Yutaka Yamada
IPC分类号： H03M13/00
CPC分类号： G06F11/1064
摘要： A cache memory has a data holding unit having multiple cache lines each of which includes an address area, a data area and a dirty bit, and a controller which is given read data and a correction execution signal indicating whether or not error correction has been performed for the read data, the read data has been read from a memory storing error-correction-coded data, which also stores address information corresponding to the read data into the address area of any one of the multiple cache lines, stores the read data into the data area, and sets a predetermine value as the dirty bit on the basis of the correction execution signal.
摘要翻译：高速缓冲存储器具有数据保持单元，该数据保持单元具有多个高速缓存线，每条高速缓存行包括地址区，数据区和脏位，以及给予读取数据的控制器和指示是否执行了纠错的校正执行信号对于读取数据，读取数据已从存储错误校正编码数据的存储器中读出，该数据还将与读取数据相对应的地址信息存储到多个高速缓存行中的任一个的地址区域中，将读取的数据存储到数据区域，并且基于校正执行信号将预定值设置为脏位。

8. 发明申请

US20120131418A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20120131418A1
公开(公告)日：2012-05-24
申请号：US13360989
申请日：2012-01-30
申请人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada , Hideki Yoshida
发明人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada , Hideki Yoshida
IPC分类号： G11C29/52 , G06F11/10
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.
摘要翻译：根据一个实施例，存储器件包括写数据位，用于纠错的校验位和开销位到存储器中的写入设备，每个比特组对应于每组比特组（ s）包括数据位和/或校验位的至少一位，开销位的每个位表示相应的位组是否已被反相，读取单元读取数据位，校验位，以及来自存储器的开销位，校正单元，其基于校验位校正从存储器读取的数据位和开销位中的错误，以及反相单元，其将包含在存储器中的数据位反相所述比特组对应于所述开销比特，并且当所述经纠错的开销比特指示已经执行了反转时，将所述反相的数据比特作为从所述存储器读取的数据输出。

9. 发明申请

US20120117407A1 COMPUTER SYSTEM AND COMPUTER SYSTEM CONTROL METHOD 有权
标题翻译：计算机系统和计算机系统控制方法
公开(公告)号：US20120117407A1
公开(公告)日：2012-05-10
申请号：US13310892
申请日：2011-12-05
申请人： Tatsunori Kanai , Yutaka Yamada , Hideki Yoshida , Masaya Tarui
发明人： Tatsunori Kanai , Yutaka Yamada , Hideki Yoshida , Masaya Tarui
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： According to one embodiment, a computer system comprises a first memory that stores a first program, a second memory that stores a second program or data, a processor, a first and a second power control circuits. The first power control circuit causes the first memory to operate at a first power consumption when detecting change of an input signal to the processor, and causes the first memory to operate at a second power consumption smaller than the first power consumption and transmits a temporary halt instruction to the processor when the execution of the first program or the second program by the processor is completed. The second power control circuit causes the second memory to operate at a third power consumption before the processor executes the second program, reads or writes the data.The second memory accepts read and write operations while operating at the third power consumption.
摘要翻译：根据一个实施例，计算机系统包括存储第一程序的第一存储器，存储第二程序或数据的第二存储器，处理器，第一和第二功率控制电路。当检测到对处理器的输入信号的变化时，第一功率控制电路使得第一存储器以第一功率消耗操作，并且使得第一存储器以比第一功耗小的第二功耗工作，并且发送暂时停止当处理器执行第一程序或第二程序完成时，指令到处理器。第二功率控制电路使得第二存储器在处理器执行第二程序之前以第三功耗操作，读取或写入数据。第二个存储器在以第三次功耗运行的同时接受读写操作。

10. 发明授权

US08775752B2 Virtual memory management apparatus and memory management apparatus 有权
标题翻译：虚拟内存管理装置和内存管理装置
公开(公告)号：US08775752B2
公开(公告)日：2014-07-08
申请号：US13371541
申请日：2012-02-13
申请人： Hideki Yoshida , Tatsunori Kanai , Masaya Tarui , Yutaka Yamada
发明人： Hideki Yoshida , Tatsunori Kanai , Masaya Tarui , Yutaka Yamada
IPC分类号： G06F12/12 , G06F12/08 , G06F12/10
CPC分类号： G06F3/061 , G06F3/0652 , G06F3/0656 , G06F3/0688 , G06F12/0246 , G06F12/0638 , G06F12/08 , G06F12/0808 , G06F12/0811 , G06F12/0868 , G06F12/1009 , G06F12/12 , G06F12/123 , G06F2212/283 , G06F2212/651 , G06F2212/7201 , G06F2212/7208 , G11C7/1072
摘要： A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.
摘要翻译：实施例的虚拟存储器管理装置嵌入在计算机80中，并具有应用程序21，操作系统22，易失性存储器11和非易失性存储器12.易失性存储器11设置有多个干净的页面。非易失性存储器12设置有多个脏页和页表存储单元51.操作系统22设置有包括页传送单元25的虚拟存储器管理单元23。

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