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1. 发明授权

US09075742B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US09075742B2
公开(公告)日：2015-07-07
申请号：US13360989
申请日：2012-01-30
申请人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada , Hideki Yoshida
发明人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada , Hideki Yoshida
IPC分类号： G11C29/00 , G06F11/10 , G11C29/04
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.
摘要翻译：根据一个实施例，存储器件包括写数据位，用于纠错的校验位和开销位到存储器中的写入设备，每个比特组对应于每组比特组（ s）包括数据位和/或校验位的至少一位，开销位的每个位表示相应的位组是否已被反相，读取单元读取数据位，校验位，以及来自存储器的开销位，校正单元，其基于校验位校正从存储器读取的数据位和开销位中的错误，以及反相单元，其将包含在存储器中的数据位反相所述比特组对应于所述开销比特，并且当所述经纠错的开销比特指示已经执行了反转时，将所述反相的数据比特作为从所述存储器读取的数据输出。

2. 发明申请

US20120131418A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20120131418A1
公开(公告)日：2012-05-24
申请号：US13360989
申请日：2012-01-30
申请人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada , Hideki Yoshida
发明人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada , Hideki Yoshida
IPC分类号： G11C29/52 , G06F11/10
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.
摘要翻译：根据一个实施例，存储器件包括写数据位，用于纠错的校验位和开销位到存储器中的写入设备，每个比特组对应于每组比特组（ s）包括数据位和/或校验位的至少一位，开销位的每个位表示相应的位组是否已被反相，读取单元读取数据位，校验位，以及来自存储器的开销位，校正单元，其基于校验位校正从存储器读取的数据位和开销位中的错误，以及反相单元，其将包含在存储器中的数据位反相所述比特组对应于所述开销比特，并且当所述经纠错的开销比特指示已经执行了反转时，将所述反相的数据比特作为从所述存储器读取的数据输出。

3. 发明申请

US20120117407A1 COMPUTER SYSTEM AND COMPUTER SYSTEM CONTROL METHOD 有权
标题翻译：计算机系统和计算机系统控制方法
公开(公告)号：US20120117407A1
公开(公告)日：2012-05-10
申请号：US13310892
申请日：2011-12-05
申请人： Tatsunori Kanai , Yutaka Yamada , Hideki Yoshida , Masaya Tarui
发明人： Tatsunori Kanai , Yutaka Yamada , Hideki Yoshida , Masaya Tarui
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： According to one embodiment, a computer system comprises a first memory that stores a first program, a second memory that stores a second program or data, a processor, a first and a second power control circuits. The first power control circuit causes the first memory to operate at a first power consumption when detecting change of an input signal to the processor, and causes the first memory to operate at a second power consumption smaller than the first power consumption and transmits a temporary halt instruction to the processor when the execution of the first program or the second program by the processor is completed. The second power control circuit causes the second memory to operate at a third power consumption before the processor executes the second program, reads or writes the data.The second memory accepts read and write operations while operating at the third power consumption.
摘要翻译：根据一个实施例，计算机系统包括存储第一程序的第一存储器，存储第二程序或数据的第二存储器，处理器，第一和第二功率控制电路。当检测到对处理器的输入信号的变化时，第一功率控制电路使得第一存储器以第一功率消耗操作，并且使得第一存储器以比第一功耗小的第二功耗工作，并且发送暂时停止当处理器执行第一程序或第二程序完成时，指令到处理器。第二功率控制电路使得第二存储器在处理器执行第二程序之前以第三功耗操作，读取或写入数据。第二个存储器在以第三次功耗运行的同时接受读写操作。

4. 发明授权

US08775752B2 Virtual memory management apparatus and memory management apparatus 有权
标题翻译：虚拟内存管理装置和内存管理装置
公开(公告)号：US08775752B2
公开(公告)日：2014-07-08
申请号：US13371541
申请日：2012-02-13
申请人： Hideki Yoshida , Tatsunori Kanai , Masaya Tarui , Yutaka Yamada
发明人： Hideki Yoshida , Tatsunori Kanai , Masaya Tarui , Yutaka Yamada
IPC分类号： G06F12/12 , G06F12/08 , G06F12/10
CPC分类号： G06F3/061 , G06F3/0652 , G06F3/0656 , G06F3/0688 , G06F12/0246 , G06F12/0638 , G06F12/08 , G06F12/0808 , G06F12/0811 , G06F12/0868 , G06F12/1009 , G06F12/12 , G06F12/123 , G06F2212/283 , G06F2212/651 , G06F2212/7201 , G06F2212/7208 , G11C7/1072
摘要： A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.
摘要翻译：实施例的虚拟存储器管理装置嵌入在计算机80中，并具有应用程序21，操作系统22，易失性存储器11和非易失性存储器12.易失性存储器11设置有多个干净的页面。非易失性存储器12设置有多个脏页和页表存储单元51.操作系统22设置有包括页传送单元25的虚拟存储器管理单元23。

5. 发明授权

US08683249B2 Switching a processor and memory to a power saving mode when waiting to access a second slower non-volatile memory on-demand 有权
标题翻译：当等待按需访问第二个较慢的非易失性存储器时，将处理器和存储器切换到省电模式
公开(公告)号：US08683249B2
公开(公告)日：2014-03-25
申请号：US13310892
申请日：2011-12-05
申请人： Tatsunori Kanai , Yutaka Yamada , Hideki Yoshida , Masaya Tarui
发明人： Tatsunori Kanai , Yutaka Yamada , Hideki Yoshida , Masaya Tarui
IPC分类号： G06F1/26
CPC分类号： G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： According to one embodiment, a computer system comprises a first memory that stores a first program, a second memory that stores a second program or data, a processor, a first and a second power control circuits. The first power control circuit causes the first memory to operate at a first power consumption when detecting change of an input signal to the processor, and causes the first memory to operate at a second power consumption smaller than the first power consumption and transmits a temporary halt instruction to the processor when the execution of the first program or the second program by the processor is completed. The second power control circuit causes the second memory to operate at a third power consumption before the processor executes the second program, reads or writes the data. The second memory accepts read and write operations while operating at the third power consumption.
摘要翻译：根据一个实施例，计算机系统包括存储第一程序的第一存储器，存储第二程序或数据的第二存储器，处理器，第一和第二功率控制电路。当检测到对处理器的输入信号的变化时，第一功率控制电路使得第一存储器以第一功率消耗操作，并且使得第一存储器以比第一功耗小的第二功耗工作，并且发送暂时停止当处理器执行第一程序或第二程序完成时，指令到处理器。第二功率控制电路使得第二存储器在处理器执行第二程序之前以第三功耗操作，读取或写入数据。第二个存储器在以第三次功耗运行的同时接受读写操作。

6. 发明申请

US20120151119A1 VIRTUAL MEMORY MANAGEMENT APPARATUS 有权
标题翻译：虚拟内存管理装置
公开(公告)号：US20120151119A1
公开(公告)日：2012-06-14
申请号：US13371541
申请日：2012-02-13
申请人： Hideki Yoshida , Tatsunori Kanai , Masaya Tarui , Yutaka Yamada
发明人： Hideki Yoshida , Tatsunori Kanai , Masaya Tarui , Yutaka Yamada
IPC分类号： G06F12/00
CPC分类号： G06F3/061 , G06F3/0652 , G06F3/0656 , G06F3/0688 , G06F12/0246 , G06F12/0638 , G06F12/08 , G06F12/0808 , G06F12/0811 , G06F12/0868 , G06F12/1009 , G06F12/12 , G06F12/123 , G06F2212/283 , G06F2212/651 , G06F2212/7201 , G06F2212/7208 , G11C7/1072
摘要： A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.
摘要翻译：实施例的虚拟存储器管理装置嵌入在计算机80中，并具有应用程序21，操作系统22，易失性存储器11和非易失性存储器12.易失性存储器11设置有多个干净的页面。非易失性存储器12设置有多个脏页和页表存储单元51.操作系统22设置有包括页传送单元25的虚拟存储器管理单元23。

7. 发明授权

US07441248B2 Data transfer scheme using caching technique for reducing network load 失效
标题翻译：数据传输方案采用缓存技术减少网络负载
公开(公告)号：US07441248B2
公开(公告)日：2008-10-21
申请号：US10253517
申请日：2002-09-25
申请人： Hideaki Sato , Tatsunori Kanai , Hideki Yoshida , Toshibumi Seki , Kenichiro Yoshii , Takayuki Miyazawa , Yasuhiro Kimura , Haruhiko Toyama
发明人： Hideaki Sato , Tatsunori Kanai , Hideki Yoshida , Toshibumi Seki , Kenichiro Yoshii , Takayuki Miyazawa , Yasuhiro Kimura , Haruhiko Toyama
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00 , G06F15/16
CPC分类号： H04L67/2819 , H04L67/2842 , H04L67/288 , H04L69/22 , H04L69/329
摘要： In a data transfer device, presence/absence of a prescribed header in the received request message is analyzed, and information indicating the presence/absence of the prescribed header, or information indicating either presence or absence of the prescribed header when the prescribed header is either present or absent as a result of analysis is stored. Then, when a reply message corresponding to the request message is received, the presence/absence of the prescribed header is checked by referring to the stored information, and the reply message is transferred according to a result of checking.
摘要翻译：在数据传送装置中，分析所接收到的请求消息中规定的报头的存在/不存在，以及指示规定标题的存在/不存在的信息，或者当规定报头是作为分析结果存在或不存在。然后，当接收到与请求消息对应的回复消息时，通过参考所存储的信息来检查规定报头的存在/不存在，并且根据检查结果传送回复消息。

8. 发明授权

US07383348B2 Data transfer scheme using caching technique for reducing network load 失效
标题翻译：数据传输方案采用缓存技术减少网络负载
公开(公告)号：US07383348B2
公开(公告)日：2008-06-03
申请号：US10167413
申请日：2002-06-13
申请人： Toshibumi Seki , Tatsunori Kanai , Kenichiro Yoshii , Hideki Yoshida , Haruhiko Toyama , Hideaki Sato , Yasuhiro Kimura , Takayuki Miyazawa
发明人： Toshibumi Seki , Tatsunori Kanai , Kenichiro Yoshii , Hideki Yoshida , Haruhiko Toyama , Hideaki Sato , Yasuhiro Kimura , Takayuki Miyazawa
IPC分类号： G06F15/16
CPC分类号： H04L67/2819 , H04L29/06 , H04L67/2828 , H04L67/288 , H04L69/329
摘要： In a data transfer scheme using a caching technique and/or a compression technique which is capable of reducing the network load of a network connecting between data transfer devices, correspondences between data and their names are registered at the data transfer devices and the corresponding names are transferred, instead of transferring the data, for those data for which the correspondences are registered, so that it is possible to reduce the amount of transfer data among the data transfer devices. Server side data transfer devices and client side data transfer devices can be provided in multiple-to-one, one-to-multiple, or multiple-to-multiple manners.
摘要翻译：在使用缓存技术和/或压缩技术的数据传输方案中，能够减少在数据传输设备之间连接的网络的网络负载，数据和它们的名称之间的对应关系被登记在数据传输设备上，并且相应的名称是而是传送数据，而不是传送数据，对于其对应被登记的那些数据，使得可以减少数据传送装置之间的传送数据量。服务器端数据传输设备和客户端数据传输设备可以以多对一，一对多或多对多的方式提供。

9. 发明授权

US07743208B2 Storage apparatus and area allocation method 失效
标题翻译：存储设备和区域分配方法
公开(公告)号：US07743208B2
公开(公告)日：2010-06-22
申请号：US11797286
申请日：2007-05-02
申请人： Hideki Yoshida , Tatsunori Kanai , Nobuo Sakiyama
发明人： Hideki Yoshida , Tatsunori Kanai , Nobuo Sakiyama
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F3/0641 , G06F3/0613 , G06F3/0617 , G06F3/067 , G06F11/2094 , G06F17/3015 , H04L69/329
摘要： A file memory stores data corresponding to identifiers of an allocated area in an identifier space. A first memory stores a basis position of the allocated area in the identifier space. A second memory stores a weight of the storage apparatus as a performance degree. A first decision unit decides a space width to divisionally allocate the identifier space with another storage apparatus by using the weight and a weight of another storage apparatus. Another storage apparatus allocates a neighboring area of the allocated area in the identifier space. A second decision unit decides the allocated area of an area between the basis position and a basis position of the neighboring area in the identifier space by using the space width.
摘要翻译：文件存储器将对应于分配区域的标识符的数据存储在标识符空间中。第一存储器将分配的区域的基准位置存储在标识符空间中。第二存储器将存储装置的重量作为性能程度存储。第一决定单元通过使用另一存储装置的权重和权重来决定空间宽度以与另一存储装置分开分配标识符空间。另一个存储装置在所述标识符空间中分配所分配区域的相邻区域。第二判定单元通过使用空格宽度来确定标识符空间中的基准位置与相邻区域的基准位置之间的区域的分配面积。

10. 发明授权

US07054912B2 Data transfer scheme using caching technique for reducing network load 失效
公开(公告)号：US07054912B2
公开(公告)日：2006-05-30
申请号：US10092540
申请日：2002-03-08
申请人： Tatsunori Kanai , Toshibumi Seki , Kenichiro Yoshii , Hideaki Sato , Takayuki Miyazawa , Haruhiko Toyama , Yasuhiro Kimura , Hideki Yoshida
发明人： Tatsunori Kanai , Toshibumi Seki , Kenichiro Yoshii , Hideaki Sato , Takayuki Miyazawa , Haruhiko Toyama , Yasuhiro Kimura , Hideki Yoshida
IPC分类号： G06F15/167
CPC分类号： H04L67/2828 , H04L29/06 , H04L67/2876 , H04L69/04 , H04L69/329
摘要： In a data transfer scheme using a caching technique and/or a compression technique which is capable of reducing the network load of a network connecting between data transfer devices, correspondences between data and their names are registered at the data transfer devices and the corresponding names are transferred, instead of transferring the data, for those data for which the correspondences are registered, so that it is possible to reduce the amount of transfer data among the data transfer devices.

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