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1. 发明授权

US09207743B2 Device for calculating a time required for system processing after the system resumes from sleep and setting an operation mode accordingly 有权
标题翻译：用于计算系统从休眠状态恢复并相应地设置操作模式后系统处理所需的时间的装置
公开(公告)号：US09207743B2
公开(公告)日：2015-12-08
申请号：US13724106
申请日：2012-12-21
申请人： Hiroyoshi Haruki , Koichi Fujisaki , Junichi Segawa , Satoshi Shirai , Yusuke Shirota , Akihiro Shibata , Masaya Tarui , Tetsuro Kimura , Tatsunori Kanai , Haruhiko Toyama
发明人： Hiroyoshi Haruki , Koichi Fujisaki , Junichi Segawa , Satoshi Shirai , Yusuke Shirota , Akihiro Shibata , Masaya Tarui , Tetsuro Kimura , Tatsunori Kanai , Haruhiko Toyama
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3234 , G06F1/263 , G06F1/3212 , G06F1/3228 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171 , Y02D10/174 , Y02D50/20
摘要： According to an embodiment, a control device includes a calculator and a setting unit. The calculator is configured to calculate a system processing time indicating a time required for processing executed after a system, the system including a plurality of elements, power to each element being individually controlled, resumes from a sleep state in which the number of elements supplied with power is limited to a predetermined number and an operation of the system is stopped. The setting unit is configured to set a mode indicating an operation state of the system according to the system processing time calculated by the calculator when a resume factor indicating a factor for resuming the system from the sleep state occurs.
摘要翻译：根据实施例，控制装置包括计算器和设定单元。计算器被配置为计算系统处理时间，其指示系统之后执行的处理所需的时间，该系统包括多个元件，每个元件被单独控制的功率从休眠状态恢复，其中提供的元件的数量功率被限制为预定数量，并且停止系统的操作。设置单元被配置为当发生指示用于恢复系统从休眠状态的因素的恢复因子时，根据由计算器计算的系统处理时间来设置指示系统的操作状态的模式。

2. 发明授权

US09105358B2 Memory system having an encoding processing circuit for redundant encoding process 有权
标题翻译：具有用于冗余编码处理的编码处理电路的存储器系统
公开(公告)号：US09105358B2
公开(公告)日：2015-08-11
申请号：US13157396
申请日：2011-06-10
申请人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada
发明人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada
IPC分类号： G06F11/16 , G06F11/10 , G11C29/04 , G11C29/42 , G06F11/08 , H03M13/19
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/08 , G06F11/1012 , G06F11/1048 , G06F11/1666 , G11C29/42 , H03M13/19
摘要： In one embodiment, a memory system for writing redundant data output by an encoding processing circuit, comprises a memory, a encoding processing circuit, and a decoding circuit. The memory is electrically rewritable by using memory cells. The memory cells are capable of having two different resistance values corresponding to logical values of 1 or 0 respectively. The redundant data is read from and a predetermined logical value is written to the memory by flowing current in a same direction. The encoding processing circuit performs redundant encoding processing on target data and outputs redundant data. A number of bits having the predetermined logical value exceeds a number of bits having the logical value other than the predetermined logical value, for writing the redundant data to the memory. A decoding circuit reads data from the memory, and performs a decoding process on the data.
摘要翻译：在一个实施例中，用于写入由编码处理电路输出的冗余数据的存储器系统包括存储器，编码处理电路和解码电路。存储器通过使用存储器单元进行电可重写。存储单元能够分别具有对应于逻辑值1或0的两个不同的电阻值。读取冗余数据，并且通过沿相同方向流动电流将预定的逻辑值写入存储器。编码处理电路对目标数据进行冗余编码处理，并输出冗余数据。具有预定逻辑值的位数超过具有除了预定逻辑值之外的逻辑值的比特数，用于将冗余数据写入存储器。解码电路从存储器读取数据，并对数据进行解码处理。

3. 发明授权

US09075742B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US09075742B2
公开(公告)日：2015-07-07
申请号：US13360989
申请日：2012-01-30
申请人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada , Hideki Yoshida
发明人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada , Hideki Yoshida
IPC分类号： G11C29/00 , G06F11/10 , G11C29/04
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.
摘要翻译：根据一个实施例，存储器件包括写数据位，用于纠错的校验位和开销位到存储器中的写入设备，每个比特组对应于每组比特组（ s）包括数据位和/或校验位的至少一位，开销位的每个位表示相应的位组是否已被反相，读取单元读取数据位，校验位，以及来自存储器的开销位，校正单元，其基于校验位校正从存储器读取的数据位和开销位中的错误，以及反相单元，其将包含在存储器中的数据位反相所述比特组对应于所述开销比特，并且当所述经纠错的开销比特指示已经执行了反转时，将所述反相的数据比特作为从所述存储器读取的数据输出。

4. 发明授权

US08892810B2 Semiconductor device and memory protection method 有权
标题翻译：半导体器件和存储器保护方法
公开(公告)号：US08892810B2
公开(公告)日：2014-11-18
申请号：US13399185
申请日：2012-02-17
申请人： Hiroto Nakai , Tatsunori Kanai , Kenichi Maeda
发明人： Hiroto Nakai , Tatsunori Kanai , Kenichi Maeda
IPC分类号： G06F12/02 , G06F9/54
CPC分类号： G06F9/524 , G06F9/544 , G06F12/0246
摘要： According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets.
摘要翻译：根据一个实施例，半导体器件包括处理器和存储器件。存储器件具有非易失性半导体存储器件，并且被配置为用作处理器的主存储器。当处理器执行多个程序时，处理器管理作为各个程序的工作流程执行程序所需的信息，并创建表，其保持各工作组所需的信息和各条信息的地址之间的关系在存储器件中，用于各个工作台。处理器参考相应工作台的相应表访问存储器件。

5. 发明授权

US08868952B2 Controller and program product 有权
标题翻译：控制器和程序产品
公开(公告)号：US08868952B2
公开(公告)日：2014-10-21
申请号：US13345824
申请日：2012-01-09
申请人： Hiroyoshi Haruki , Koichi Fujisaki , Satoshi Shirai , Masaya Tarui , Akihiro Shibata , Tetsuro Kimura , Tatsunori Kanai , Haruhiko Toyama
发明人： Hiroyoshi Haruki , Koichi Fujisaki , Satoshi Shirai , Masaya Tarui , Akihiro Shibata , Tetsuro Kimura , Tatsunori Kanai , Haruhiko Toyama
IPC分类号： G06F1/32 , G06F9/48
CPC分类号： G06F9/4893 , G06F1/3228 , G06F1/324 , G06F1/3243 , G06F1/3287 , Y02D10/126 , Y02D10/152 , Y02D10/171 , Y02D10/24 , Y02D50/20
摘要： According to one embodiment, a controller includes a state detecting unit, a calculating unit, and a determining unit. The state detecting unit detects an idle state in which indicates there are no process that can execute on a processing device capable of performing one or more processes. The calculating unit calculates a resuming time, which indicates a time length until the next process starts, when the state detecting unit detects the idle state. The determining unit determines an operation mode of the processing device on the basis of the resuming time calculated by the calculating unit.
摘要翻译：根据一个实施例，控制器包括状态检测单元，计算单元和确定单元。状态检测单元检测空闲状态，其中表示不能在能够执行一个或多个处理的处理设备上执行的处理。当状态检测单元检测到空闲状态时，计算单元计算恢复时间，其指示直到下一个处理开始的时间长度。确定单元基于由计算单元计算的恢复时间来确定处理装置的操作模式。

6. 发明申请

US20130191670A1 CONTROL DEVICE, SYSTEM, AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：控制设备，系统和计算机程序产品
公开(公告)号：US20130191670A1
公开(公告)日：2013-07-25
申请号：US13724106
申请日：2012-12-21
申请人： Hiroyoshi Haruki , Koichi Fujisaki , Junichi Segawa , Satoshi Shirai , Yusuke Shirota , Akihiro Shibata , Masaya Tarui , Tetsuro Kimura , Tatsunori Kanai , Haruhiko Toyama
发明人： Hiroyoshi Haruki , Koichi Fujisaki , Junichi Segawa , Satoshi Shirai , Yusuke Shirota , Akihiro Shibata , Masaya Tarui , Tetsuro Kimura , Tatsunori Kanai , Haruhiko Toyama
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/263 , G06F1/3212 , G06F1/3228 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171 , Y02D10/174 , Y02D50/20
摘要： According to an embodiment, a control device includes a calculator and a setting unit. The calculator is configured to calculate a system processing time indicating a time required for processing executed after a system, the system including a plurality of elements, power to each element being individually controlled, resumes from a sleep state in which the number of elements supplied with power is limited to a predetermined number and an operation of the system is stopped. The setting unit is configured to set a mode indicating an operation state of the system according to the system processing time calculated by the calculator when a resume factor indicating a factor for resuming the system from the sleep state occurs.
摘要翻译：根据实施例，控制装置包括计算器和设定单元。计算器被配置为计算系统处理时间，其指示系统之后执行的处理所需的时间，该系统包括多个元件，每个元件被单独控制的功率从休眠状态恢复，其中提供的元件的数量功率被限制为预定数量，并且停止系统的操作。设置单元被配置为当发生指示用于恢复系统从休眠状态的因素的恢复因子时，根据由计算器计算的系统处理时间来设置指示系统的操作状态的模式。

7. 发明申请

US20130080813A1 CONTROL SYSTEM, CONTROL METHOD, AND COMPUTER PROGRAM PRODUCT 有权
公开(公告)号：US20130080813A1
公开(公告)日：2013-03-28
申请号：US13556354
申请日：2012-07-24
申请人： Masaya Tarui , Koichi Fujisaki , Hiroyoshi Haruki , Tatsunori Kanai , Haruhiko Toyama , Tetsuro Kimura , Junichi Segawa , Yusuke Shirota , Satoshi Shirai , Akihiro Shibata
发明人： Masaya Tarui , Koichi Fujisaki , Hiroyoshi Haruki , Tatsunori Kanai , Haruhiko Toyama , Tetsuro Kimura , Junichi Segawa , Yusuke Shirota , Satoshi Shirai , Akihiro Shibata
IPC分类号： G06F1/32
CPC分类号： G06F12/0893 , G06F1/3275 , G06F1/3287 , G06F12/0804 , G06F12/0864 , G06F2212/1028 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： According to an embodiment, a control system includes a detector, an estimating unit, a determining unit, and a controller. The detector detects an idle state. The estimating unit estimates an idle period. When the idle state is detected, the determining unit determines whether a first power consumption when writeback of data which needs to be written back to a main storage device is performed and supply of power to a cache memory is stopped, is larger than a second power consumption when writeback of the data is not performed and supply of power is continued for the idle period. The controller stops the supply of power to the cache memory when the first power consumption is determined to be smaller than the second power consumption and continues the supply of power when the first power consumption is determined to be larger than the second power consumption.

8. 发明授权

US08381072B2 Cache memory, computer system and memory access method 有权
标题翻译：缓存，计算机系统和内存访问方式
公开(公告)号：US08381072B2
公开(公告)日：2013-02-19
申请号：US13584182
申请日：2012-08-13
申请人： Tatsunori Kanai , Yutaka Yamada
发明人： Tatsunori Kanai , Yutaka Yamada
IPC分类号： H03M13/00
CPC分类号： G06F11/1064
摘要： A cache memory has a data holding unit having multiple cache lines each of which includes an address area, a data area and a dirty bit, and a controller which is given read data and a correction execution signal indicating whether or not error correction has been performed for the read data, the read data has been read from a memory storing error-correction-coded data, which also stores address information corresponding to the read data into the address area of any one of the multiple cache lines, stores the read data into the data area, and sets a predetermine value as the dirty bit on the basis of the correction execution signal.
摘要翻译：高速缓冲存储器具有数据保持单元，该数据保持单元具有多个高速缓存线，每条高速缓存行包括地址区，数据区和脏位，以及给予读取数据的控制器和指示是否执行了纠错的校正执行信号对于读取数据，读取数据已从存储错误校正编码数据的存储器中读出，该数据还将与读取数据相对应的地址信息存储到多个高速缓存行中的任一个的地址区域中，将读取的数据存储到数据区域，并且基于校正执行信号将预定值设置为脏位。

9. 发明申请

US20120246397A1 STORAGE DEVICE MANAGEMENT DEVICE AND METHOD FOR MANAGING STORAGE DEVICE 有权
标题翻译：存储设备管理设备和用于管理存储设备的方法
公开(公告)号：US20120246397A1
公开(公告)日：2012-09-27
申请号：US13491824
申请日：2012-06-08
申请人： Hiroto NAKAI , Tatsunori Kanai
发明人： Hiroto NAKAI , Tatsunori Kanai
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0638
摘要： According to one embodiment, a storage device management device is connected to a random access memory and a first storage device. When the random access memory includes a free region sufficient to store write data, the write data is stored onto the random access memory. Data on the random access memory selected in the descending order of elapsed time from the last access is sequentially copied onto the first storage device, and a region in the random access memory which has stored the copied data is released. When stored on the random access memory, the read data is read from the random access memory to the processor. When stored on the first storage device, the read data is copied onto the random access memory and read from the random access memory to the processor.
摘要翻译：根据一个实施例，存储设备管理设备连接到随机存取存储器和第一存储设备。当随机存取存储器包括足以存储写入数据的空闲区域时，写入数据被存储到随机存取存储器中。按照从最后访问经过的时间的降序选择的随机存取存储器上的数据被顺序复制到第一存储设备上，并且释放存储了复制数据的随机存取存储器中的区域。当存储在随机存取存储器中时，将读取的数据从随机存取存储器读取到处理器。当存储在第一存储设备上时，将读取的数据复制到随机存取存储器中并从随机存取存储器读取到处理器。

10. 发明申请

US20120131418A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20120131418A1
公开(公告)日：2012-05-24
申请号：US13360989
申请日：2012-01-30
申请人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada , Hideki Yoshida
发明人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada , Hideki Yoshida
IPC分类号： G11C29/52 , G06F11/10
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.
摘要翻译：根据一个实施例，存储器件包括写数据位，用于纠错的校验位和开销位到存储器中的写入设备，每个比特组对应于每组比特组（ s）包括数据位和/或校验位的至少一位，开销位的每个位表示相应的位组是否已被反相，读取单元读取数据位，校验位，以及来自存储器的开销位，校正单元，其基于校验位校正从存储器读取的数据位和开销位中的错误，以及反相单元，其将包含在存储器中的数据位反相所述比特组对应于所述开销比特，并且当所述经纠错的开销比特指示已经执行了反转时，将所述反相的数据比特作为从所述存储器读取的数据输出。

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