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1. 发明授权

US07243170B2 Method and circuit for reading and writing an instruction buffer 有权
标题翻译：用于读写指令缓冲器的方法和电路
公开(公告)号：US07243170B2
公开(公告)日：2007-07-10
申请号：US10707149
申请日：2003-11-24
申请人： Taqi N. Buti , Brian W. Curran , Maureen A. Delaney , Saiful Islam , Zakaria M. Khwaja , Jafar Nahidi , Dung Q. Nguyen
发明人： Taqi N. Buti , Brian W. Curran , Maureen A. Delaney , Saiful Islam , Zakaria M. Khwaja , Jafar Nahidi , Dung Q. Nguyen
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F9/3802 , G06F9/3814
摘要： An instruction buffer and a method of buffering instructions. The instruction buffer including: a memory array partitioned into multiple identical memory sub-arrays arranged in sequential order from a first memory sub-array to a last memory sub-array, each memory sub-array having multiple instruction entry positions and adapted to store a different instruction of a set of concurrent instructions in a single instruction entry position of any one of the memory sub-arrays, the set of concurrent instructions arranged in sequential order from a first instruction to a last instruction
摘要翻译：指令缓冲器和缓冲指令的方法。所述指令缓冲器包括：分割成从第一存储器子阵列到最后存储器子阵列的顺序排列的多个相同的存储器子阵列的存储器阵列，每个存储器子阵列具有多个指令条目位置，并且适于存储任何一个存储器子阵列的单个指令输入位置中的一组并行指令的不同指令，以从第一指令到最后指令的顺序排列的并发指令集

2. 发明申请

US20090070719A1 Logic Block Timing Estimation Using Conesize 有权
标题翻译：使用锥形的逻辑块时序估计
公开(公告)号：US20090070719A1
公开(公告)日：2009-03-12
申请号：US11853235
申请日：2007-09-11
申请人： Reinaldo A. Bergamaschi , Sean M. Carey , Brian W. Curran , Prabhakar N. Kudva , Matthew E. Mariani , Mark D. Mayo , Ruchir Puri
发明人： Reinaldo A. Bergamaschi , Sean M. Carey , Brian W. Curran , Prabhakar N. Kudva , Matthew E. Mariani , Mark D. Mayo , Ruchir Puri
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time.
摘要翻译：用于逻辑块定时分析的系统可以包括控制器和与控制器通信的存储器。存储器可以提供逻辑块的延迟对锥形值。该系统可以进一步包括一个拟合模块，用于根据逻辑块的延迟 - 锥度值来提供延迟锥。系统还可以包括锥形解析器，其使用延迟锥来通过逻辑块提供延迟值。锥形解析器可用于通过将延迟锥与期望的周期时间进行比较来验证逻辑块的设计。

3. 发明授权

US5572736A Method and apparatus for reducing bus noise and power consumption 失效
标题翻译：降低总线噪声和功耗的方法和装置
公开(公告)号：US5572736A
公开(公告)日：1996-11-05
申请号：US414554
申请日：1995-03-31
申请人： Brian W. Curran
发明人： Brian W. Curran
IPC分类号： G06F13/40 , G06F1/32
CPC分类号： G06F13/4072 , Y02B60/1228 , Y02B60/1235
摘要： In a computer system comprising a plurality of subsystems, interconnected by a bus comprising bit drivers and bit receivers, data words are transmitted on the bus in the form of code words. The code words are formulated such that the number of bits of the bus which changes with the transmission of successive code words is minimized. A switching code, comprising one or more bits, defines a plurality of mapping codes and a data word to be transmitted is mapped by use of the mapping codes to a plurality of code words. One of the plurality of code words differing from a previously transmitted code word in the least number of bit positions is selected. The selected code words is transmitted, together with a switching code, identifying the mapping from which the transmitted code word was generated. At the receiving end of the bus, the switching code is decoded to identify the mapping used in creating the code word. Using the identified mapping, the original data word is recovered.
摘要翻译：在包括由包括位驱动器和位接收器的总线互连的多个子系统的计算机系统中，数据字以代码字的形式在总线上传送。编码字被配置为使得随着连续代码字的传输而变化的总线的位数最小化。包括一个或多个位的切换代码定义多个映射代码，并且将要发送的数据字通过使用映射代码映射到多个代码字。选择与最少数量的位位置中的先前发送的代码字不同的多个代码字中的一个。所选择的代码字与切换代码一起发送，识别生成发送的代码字的映射。在总线的接收端，对切换代码进行解码以识别用于创建代码字的映射。使用识别的映射，恢复原始数据字。

4. 发明授权

US5479640A Memory access system including a memory controller with memory redrive circuitry 失效
标题翻译：存储器存取系统包括具有存储器重新驱动电路的存储器控制器
公开(公告)号：US5479640A
公开(公告)日：1995-12-26
申请号：US85215
申请日：1993-06-30
申请人： Frank P. Cartman , Brian W. Curran , Matthew A. Krygowski , Tin-Chee Lo , Sandy N. Luu , Sanjay B. Patel , William W. Shen
发明人： Frank P. Cartman , Brian W. Curran , Matthew A. Krygowski , Tin-Chee Lo , Sandy N. Luu , Sanjay B. Patel , William W. Shen
IPC分类号： G06F12/02 , G11C8/00 , G11C11/408
CPC分类号： G06F12/0215 , G11C11/408 , G11C8/00
摘要： A memory access system for improving memory access when addressing dynamic random access modules (DRAMs). The memory access system includes a main memory and a memory controller. To improve memory access, both the memory controller and the main memory hardware remember the row address of the last access. Macro operation commands for fetch and store contain the last row address. The main memory hardware redrives that row address to the DRAMs after completion of an access, so that the memory controller need not provide a row address to the memory for each command of a command sequence.
摘要翻译：一种用于在寻址动态随机存取模块（DRAM）时改善存储器访问的存储器访问系统。存储器存取系统包括主存储器和存储器控制器。为了改善内存访问，内存控制器和主内存硬件都记住上次访问的行地址。用于获取和存储的宏操作命令包含最后一行地址。完成访问后，主存储器硬件将该行地址重新发送到DRAM，使得存储器控制器不需要为命令序列的每个命令向存储器提供行地址。

5. 发明授权

US5428762A Expandable memory having plural memory cards for distributively storing system data 失效
标题翻译：可扩展存储器，具有用于分布式存储系统数据的多个存储卡
公开(公告)号：US5428762A
公开(公告)日：1995-06-27
申请号：US850194
申请日：1992-03-11
申请人： Brian W. Curran , Joseph L. Temple, III
发明人： Brian W. Curran , Joseph L. Temple, III
IPC分类号： G11C5/00 , G06F13/16 , G06F13/40 , G06F13/38 , G06F13/42
CPC分类号： G06F13/1694
摘要： An improved memory system and memory controller which permits simplified memory upgrades in the field. The system includes a memory board with multiple card sockets. As additional cards are added the data cables are distributed among the cards and the memory controller is programmed to coordinate the sequencing of the memory in the cards. Data is transferred between the cards and memory controller via distributively coupled cables. Control and address signals are provided to cards via wires embedded in the memory board from the memory controller. A repowering circuit on each card makes copies of the control and address signals which are sent to other cards through the embedded wires in the board. Data received by a card is stored in memory through steering logic and buffers.
摘要翻译：改进的存储器系统和存储器控制器，其允许在现场简化存储器升级。该系统包括一个具有多个卡插槽的存储器板。随着附加卡被添加，数据电缆分布在卡之间，并且存储器控制器被编程以协调卡中的存储器的排序。数据通过分布式耦合电缆在卡和存储控制器之间传输。控制和地址信号通过从存储器控制器嵌入存储器板中的线路提供给卡。每个卡上的重新加电电路将通过板中的嵌入式电线发送到其他卡的控制和地址信号的副本。由卡接收的数据通过转向逻辑和缓冲器存储在存储器中。

6. 发明授权

US5032985A Multiprocessor system with memory fetch buffer invoked during cross-interrogation 失效
标题翻译：在交叉询问期间调用具有内存提取缓冲区的多处理器系统
公开(公告)号：US5032985A
公开(公告)日：1991-07-16
申请号：US222678
申请日：1988-07-21
申请人： Brian W. Curran , Joseph M. D'Onofrio , Richard N. Fuqua , Robert D. Herzl , Louis J. Milich , Paul M. Moore , Joseph L. Temple, III
发明人： Brian W. Curran , Joseph M. D'Onofrio , Richard N. Fuqua , Robert D. Herzl , Louis J. Milich , Paul M. Moore , Joseph L. Temple, III
IPC分类号： G06F12/08 , G06F15/16
CPC分类号： G06F12/0817
摘要： An improved multiprocessor system of the type including a plurality of processors and an array of memories interconnected by an interrogation logic where the processors have a store-in cache is presented. In such processors the most recent copy of the data does not always reside in the memories but can reside in a processor's cache necessitating cross-interrogation producing system delays. These delays are reduced by a fetch buffer selectively coupled to each memory for holding data before cross-interrogation and other checks are complete.

7. 发明申请

US20090070720A1 System to Identify Timing Differences from Logic Block Changes and Associated Methods 审中-公开
标题翻译：识别与逻辑块更改和相关方法的时间差异的系统
公开(公告)号：US20090070720A1
公开(公告)日：2009-03-12
申请号：US11853276
申请日：2007-09-11
申请人： Reinaldo A. Bergamaschi , Sean M. Carey , Brian W. Curran , Prabhakar N. Kudva , Lawrence Lange , Matthew E. Mariani , Mark D. Mayo , Ruchir Puri , Gebhard Weber
发明人： Reinaldo A. Bergamaschi , Sean M. Carey , Brian W. Curran , Prabhakar N. Kudva , Lawrence Lange , Matthew E. Mariani , Mark D. Mayo , Ruchir Puri , Gebhard Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system to identify timing differences due to logic block changes, the system may include a controller, and storage in communication with the controller. The controller may provide delay values of a previous logic block and a current logic block. The system may also include a timing-modeler to compare the delay values of the previous logic block with the current logic block for timing analysis. The system may further include an interface that provides a report based upon the previous logic block and the current logic block comparison.
摘要翻译：用于识别由于逻辑块变化引起的时序差异的系统，系统可以包括控制器和与控制器通信的存储器。控制器可以提供先前逻辑块和当前逻辑块的延迟值。该系统还可以包括一个定时建模器，用于将先前逻辑块的延迟值与用于定时分析的当前逻辑块进行比较。系统还可以包括基于先前逻辑块和当前逻辑块比较来提供报告的接口。

8. 发明授权

US06966046B2 CMOS tapered gate and synthesis method 失效
标题翻译： CMOS锥形栅极及其合成方法
公开(公告)号：US06966046B2
公开(公告)日：2005-11-15
申请号：US09841505
申请日：2001-04-24
申请人： Brian W. Curran , Lisa Bryant Lacey , Gregory A. Northrop , Ruchir Puri , Leon Stok
发明人： Brian W. Curran , Lisa Bryant Lacey , Gregory A. Northrop , Ruchir Puri , Leon Stok
IPC分类号： G06F17/50 , H01L21/82 , H03K19/096 , H03K19/20
CPC分类号： G06F17/505
摘要： A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce the delay through some of the input pins. For example in a tapered NAND gate the bottom devices in the NFET stack are have longer widths than the top device to achieve smaller top input to output pin delay at the expense of larger bottom input to output pin delay. The method of using synthesis algorithms modifies the input net to gate pin connections and swaps traditional non-tapered gates with tapered gates to improve the delay of the timing critical paths. The latest arriving gate input net is swapped with the net connected to the top pin. The gate is then converted to a tapered gate provided the paths through the bottom gate input(s) that are not timing critical.
摘要翻译：高性能门库增加了锥形门。改变堆叠器件的宽度以减少通过一些输入引脚的延迟。例如在锥形NAND门中，NFET堆叠中的底部器件具有比顶部器件更宽的宽度，以牺牲较大的底部输入到输出引脚延迟为代价来实现较小的顶部输入以输出引脚延迟。使用合成算法的方法将输入网络修改为栅极引脚连接，并与锥形栅极交换传统的非锥形栅极，以改善时序关键路径的延迟。最新到达的门输入网络被互换，网络连接到顶针。然后将栅极转换成锥形栅极，提供通过底栅输入（不是时序关键）的路径。

9. 发明授权

US5939915A Noise-immune pass gate latch 失效
标题翻译：无噪声通过门锁
公开(公告)号：US5939915A
公开(公告)日：1999-08-17
申请号：US907346
申请日：1997-08-06
申请人： Brian W. Curran
发明人： Brian W. Curran
IPC分类号： H03K3/013 , H03K3/037 , H03K3/356 , H03K3/289
CPC分类号： H03K3/037 , H03K3/013 , H03K3/356156
摘要： A non-buffered, noise-immune transmission gate latch for high performance applications is disclosed. The latch data input circuit contains an additional PFET for pulling up the gate of a transmission PFET and an additional NFET to pull down the gate of the transmission NFET to prevent the transmission gate from inadvertently opening when noise is coupled into the data input node. When data input voltage rises to Vdd+Vtp, the additional PFET begins to turn ON, and an inverted clock node is pulled above Vdd. The higher inverted clock node voltage is coupled to the gate of the transmission PFET and thereby prevents the transmission PFET from inadvertently turning ON. When data input voltage drops to -Vtn, the additional NFET begins to turn ON, and a clock node Is pulled below ground. The lower clock node voltage is coupled to the gate of the transmission NFET and thereby prevents the transmission NFET from inadvertently turning ON. Thus two additional transistors provide the necessary noise immunity.
摘要翻译：公开了一种用于高性能应用的非缓冲，无噪声的传输门锁。锁存数据输入电路包含用于提升传输PFET的栅极和附加NFET的附加PFET，以将传输NFET的栅极拉下来，以防止当噪声耦合到数据输入节点时传输门不经意地打开。当数据输入电压上升到Vdd + Vtp时，附加PFET开始导通，反相时钟节点被拉到Vdd以上。较高的反相时钟节点电压耦合到传输PFET的栅极，从而防止传输PFET无意中导通。当数据输入电压下降到-Vtn时，额外的NFET开始导通，时钟节点被拉到地下。较低时钟节点电压耦合到传输NFET的栅极，从而防止透射NFET无意中导通。因此两个额外的晶体管提供必要的抗干扰能力。

10. 发明授权

US5568075A Timing signal generator 失效
公开(公告)号：US5568075A
公开(公告)日：1996-10-22
申请号：US453587
申请日：1995-05-30
申请人： Brian W. Curran , Rafael Blanco
发明人： Brian W. Curran , Rafael Blanco
IPC分类号： G11C7/10 , G11C7/22 , H03K5/13
CPC分类号： G11C7/22 , G11C7/1072 , H03K5/131 , H03K5/133
摘要： A programmable, timing signal generator propagates a digital wave along a delay chain comprised of series connected inverters that has sufficient stages that the edge of the wave will not propagate to the end during one system clock cycle time. The delay chain is sampled once each clock cycle, and the point to which the wave has progressed is encoded. Programmable, fine leading and fine trailing edge registers store, as a fraction of the clock cycle time, the desired locations of the timing signal leading and trailing edge relative to the clock edges.

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