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1. 发明授权

US07676779B2 Logic block timing estimation using conesize 有权
标题翻译：使用锥形的逻辑块定时估计
公开(公告)号：US07676779B2
公开(公告)日：2010-03-09
申请号：US11853235
申请日：2007-09-11
申请人： Reinaldo A. Bergamaschi , Sean M. Carey , Brian W. Curran , Prabhakar N. Kudva , Matthew E. Mariani , Mark D. Mayo , Ruchir Puri
发明人： Reinaldo A. Bergamaschi , Sean M. Carey , Brian W. Curran , Prabhakar N. Kudva , Matthew E. Mariani , Mark D. Mayo , Ruchir Puri
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5031
摘要： A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time.
摘要翻译：用于逻辑块定时分析的系统可以包括控制器和与控制器通信的存储器。存储器可以提供逻辑块的延迟对锥形值。该系统可以进一步包括一个拟合模块，用于根据逻辑块的延迟 - 锥度值来提供延迟锥。系统还可以包括锥形解析器，其使用延迟锥来通过逻辑块提供延迟值。锥形解析器可用于通过将延迟锥与期望的周期时间进行比较来验证逻辑块的设计。

2. 发明授权

US4967151A Method and apparatus for detecting faults in differential current switching logic circuits 失效
标题翻译：用于检测差动电流开关逻辑电路故障的方法和装置
公开(公告)号：US4967151A
公开(公告)日：1990-10-30
申请号：US420690
申请日：1989-10-11
申请人： Arnold E. Barish , David A. Kiesling , Mark D. Mayo , Walter A. Svarczkopf
发明人： Arnold E. Barish , David A. Kiesling , Mark D. Mayo , Walter A. Svarczkopf
IPC分类号： G01R31/30 , G06F11/00
CPC分类号： G06F11/0754 , G01R31/3004
摘要： A circuit for testing a differential current switching logic circuit of the type including: a bias potential, two resistors connected to the bias potential, and apparatus responsive to an input signal for sinking a first current through a selected one of the resistors so as to generate first and second differential output signals at the resistors. The circuit includes first, second, and third transistors, each having first and second terminals for conducting a current responsive to a signal applied to a control terminal. Apparatus are provided for supplying a current. The first transistor has its first terminal connected to the current supplying means, and its second terminal connected to a circuit node. The second transistor has its first terminal connected to the circuit node, its second terminal connected to the bias potential, and its control terminal connected to sense the potential at a selected one of the resistors. The third transistor has its first terminal connected to the circuit node, its second terminal connected to the selected resistor, and its control terminal connected to sense the potential at the other of the resistors. The circuit functions to sense the potential difference between the first and second differential output signals. When the potential difference is less than a predetermined level, a second current is sunk through the one resistor so as to lower the potential of the output signal associated with the one resistor relative to the potential of the output signal associated with the other resistor.
摘要翻译：一种用于测试类型的差分电流开关逻辑电路的电路，包括：偏置电位，连接到偏置电位的两个电阻器，以及响应于输入信号的装置，用于将第一电流吸收通过所选择的一个电阻器，以便产生电阻器上的第一和第二差分输出信号。电路包括第一，第二和第三晶体管，每个具有第一和第二端子，用于响应于施加到控制端子的信号传导电流。提供用于提供电流的装置。第一晶体管的第一端子连接到电流供应装置，其第二端子连接到电路节点。第二晶体管的第一端子连接到电路节点，其第二端子连接到偏置电位，并且其控制端子被连接以感测所选择的一个电阻器中的电位。第三晶体管的第一端子连接到电路节点，其第二端子连接到所选择的电阻器，并且其控制端子连接以感测另一个电阻器上的电位。电路用于检测第一和第二差分输出信号之间的电位差。当电位差小于预定电平时，第二电流通过一个电阻器沉没，以便降低与一个电阻器相关联的输出信号相对于与另一个电阻器相关联的输出信号的电位的电位。

3. 发明申请

US20090070720A1 System to Identify Timing Differences from Logic Block Changes and Associated Methods 审中-公开
标题翻译：识别与逻辑块更改和相关方法的时间差异的系统
公开(公告)号：US20090070720A1
公开(公告)日：2009-03-12
申请号：US11853276
申请日：2007-09-11
申请人： Reinaldo A. Bergamaschi , Sean M. Carey , Brian W. Curran , Prabhakar N. Kudva , Lawrence Lange , Matthew E. Mariani , Mark D. Mayo , Ruchir Puri , Gebhard Weber
发明人： Reinaldo A. Bergamaschi , Sean M. Carey , Brian W. Curran , Prabhakar N. Kudva , Lawrence Lange , Matthew E. Mariani , Mark D. Mayo , Ruchir Puri , Gebhard Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system to identify timing differences due to logic block changes, the system may include a controller, and storage in communication with the controller. The controller may provide delay values of a previous logic block and a current logic block. The system may also include a timing-modeler to compare the delay values of the previous logic block with the current logic block for timing analysis. The system may further include an interface that provides a report based upon the previous logic block and the current logic block comparison.
摘要翻译：用于识别由于逻辑块变化引起的时序差异的系统，系统可以包括控制器和与控制器通信的存储器。控制器可以提供先前逻辑块和当前逻辑块的延迟值。该系统还可以包括一个定时建模器，用于将先前逻辑块的延迟值与用于定时分析的当前逻辑块进行比较。系统还可以包括基于先前逻辑块和当前逻辑块比较来提供报告的接口。

4. 发明申请

US20090070719A1 Logic Block Timing Estimation Using Conesize 有权
标题翻译：使用锥形的逻辑块时序估计
公开(公告)号：US20090070719A1
公开(公告)日：2009-03-12
申请号：US11853235
申请日：2007-09-11
申请人： Reinaldo A. Bergamaschi , Sean M. Carey , Brian W. Curran , Prabhakar N. Kudva , Matthew E. Mariani , Mark D. Mayo , Ruchir Puri
发明人： Reinaldo A. Bergamaschi , Sean M. Carey , Brian W. Curran , Prabhakar N. Kudva , Matthew E. Mariani , Mark D. Mayo , Ruchir Puri
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time.
摘要翻译：用于逻辑块定时分析的系统可以包括控制器和与控制器通信的存储器。存储器可以提供逻辑块的延迟对锥形值。该系统可以进一步包括一个拟合模块，用于根据逻辑块的延迟 - 锥度值来提供延迟锥。系统还可以包括锥形解析器，其使用延迟锥来通过逻辑块提供延迟值。锥形解析器可用于通过将延迟锥与期望的周期时间进行比较来验证逻辑块的设计。

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