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1. 发明授权

US07989923B2 Bi-directional transient voltage suppression device and forming method thereof 有权
标题翻译：双向瞬态电压抑制装置及其形成方法
公开(公告)号：US07989923B2
公开(公告)日：2011-08-02
申请号：US12342118
申请日：2008-12-23
申请人： Tang-Kuei Tseng , Kun-Hsien Lin , Hsin-Chin Jiang
发明人： Tang-Kuei Tseng , Kun-Hsien Lin , Hsin-Chin Jiang
IPC分类号： H01L29/167
CPC分类号： H01L29/87
摘要： A bidirectional transient voltage suppression device is disclosed. The bi-directional transient voltage suppression device comprises a semiconductor die. The semiconductor die has a multi-layer structure comprising a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type, an epitaxial layer, and five diffused regions. The buried layer and the semiconductor substrate form a first semiconductor junction. The first diffused region of the second conductivity type and the semiconductor substrate form a second semiconductor junction. The fourth diffused region of the first conductivity type and the third diffused region of the second conductivity type form a third semiconductor junction. The fifth diffused region of the first conductivity type and the second diffused region of the second conductivity type form a fourth semiconductor junction.
摘要翻译：公开了一种双向瞬态电压抑制装置。双向瞬态电压抑制装置包括半导体管芯。半导体管芯具有包括第一导电类型的半导体衬底，第二导电类型的掩埋层，外延层和五个扩散区域的多层结构。掩埋层和半导体衬底形成第一半导体结。第二导电类型的第一扩散区域和半导体衬底形成第二半导体结。第一导电类型的第四扩散区域和第二导电类型的第三扩散区域形成第三半导体结。第一导电类型的第五扩散区域和第二导电类型的第二扩散区域形成第四半导体结。

2. 发明授权

US08232601B1 Transient voltage suppressors 有权
标题翻译：瞬态电压抑制器
公开(公告)号：US08232601B1
公开(公告)日：2012-07-31
申请号：US13475599
申请日：2012-05-18
申请人： Kun-Hsien Lin , Che-Hao Chuang , Ryan Hsin-Chin Jiang
发明人： Kun-Hsien Lin , Che-Hao Chuang , Ryan Hsin-Chin Jiang
IPC分类号： H01L23/62
CPC分类号： H01L29/8613 , H01L27/0255 , H01L27/0259 , H01L29/866
摘要： The present invention relates a transient voltage suppressor (TVS) for directional ESD protection. The TVS includes: a conductivity type substrate; a first type lightly doped region, having a first type heavily doped region arranged therein; a second type lightly doped region, having a second type heavily doped region and a third type heavily doped region arranged therein; a third type lightly doped region, having a fourth type heavily doped region arranged therein; a plurality of closed isolation trenches, arranged on the conductivity type substrate, wherein at least one of the plurality of closed isolation trenches is neighbored one of the type lightly doped regions; and a first pin. Accordingly, the TVS of present invention may adaptively provide effective ESD protection under positive and negative ESD stresses, improve the efficiency of ESD protection within the limited layout area.
摘要翻译：本发明涉及用于定向ESD保护的瞬态电压抑制器（TVS）。 TVS包括：导电型基板; 第一类型轻掺杂区域，其中布置有第一类型重掺杂区域; 具有第二类型重掺杂区域和布置在其中的第三类型重掺杂区域的第二类型轻掺杂区域; 第三类型轻掺杂区域，其中布置有第四类型重掺杂区域; 多个封闭的隔离沟槽，布置在所述导电型衬底上，其中所述多个闭合隔离沟槽中的至少一个与所述轻掺杂区域中的一个相邻; 和第一个引脚。因此，本发明的TVS可以在正和负ESD应力下自适应地提供有效的ESD保护，从而在有限的布局区域内提高ESD保护的效率。

3. 发明授权

US08217421B2 ESD protection device with vertical transistor structure 有权
标题翻译：具有垂直晶体管结构的ESD保护器件
公开(公告)号：US08217421B2
公开(公告)日：2012-07-10
申请号：US12840749
申请日：2010-07-21
申请人： Zi-Ping Chen , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
发明人： Zi-Ping Chen , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
IPC分类号： H01L29/66
CPC分类号： H01L27/0259
摘要： A new ESD protection device with an integrated-circuit vertical transistor structure is disclosed, which includes a heavily doped p-type substrate (P+ substrate), a n-type well (N well) in the P+ substrate, a heavily doped p-type diffusion (P+ diffusion) in the N well, a heavily doped n-type diffusion (N+ diffusion) in the N well, and a p-type well (P well) surrounding the N well in the P+ substrate. A bond pad is connected to both the P+ and N+ diffusions, and a ground is coupled to the P+ substrate. Another P+ diffusion is implanted in the N well or another N+ diffusion is implanted in the P well to form a Zener diode, which behaves as a trigger for the PNP transistor when a positive ESD zaps. A parasitic diode is formed at the junction between the P+ substrate and the N well, to bypass a negative ESD stress on the bond pad.
摘要翻译：公开了一种具有集成电路垂直晶体管结构的新型ESD保护器件，其包括重掺杂p型衬底（P +衬底），P +衬底中的n型阱（N阱），重掺杂p型衬底 N阱中的扩散（P +扩散），N阱中的重掺杂n型扩散（N +扩散）以及P +衬底中N阱周围的p型阱（P阱）。接合焊盘连接到P +和N +扩散两者，并且接地耦合到P +衬底。将另一个P +扩散注入到N阱中，或者将另一个N +扩散注入到P阱中以形成齐纳二极管，当正ESD成像时，其作为PNP晶体管的触发器。在P +衬底和N阱之间的接合处形成寄生二极管，以绕过接合焊盘上的负ESD应力。

4. 发明授权

US08785971B2 Transient voltage suppressor without leakage current 有权
标题翻译：瞬态电压抑制器无泄漏电流
公开(公告)号：US08785971B2
公开(公告)日：2014-07-22
申请号：US13303946
申请日：2011-11-23
申请人： Che-Hao Chuang , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
发明人： Che-Hao Chuang , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
IPC分类号： H01L23/58 , H01L27/02 , H01L29/866 , H01L29/861
CPC分类号： H01L27/0296 , H01L29/8613 , H01L29/866
摘要： A transient voltage suppressor without leakage current is disclosed, which comprises a P-substrate. There is an N-type epitaxial layer formed on the P-substrate, and a first N-heavily doped area, a first P-heavily doped area, an electrostatic discharge (ESD) device and at least one deep isolation trench are formed in the N-epitaxial layer. A first N-buried area is formed in the bottom of the N-epitaxial layer to neighbor the P-substrate and located below the first N-heavily doped area and the first P-heavily doped area. The ESD device is coupled to the first N-heavily doped area. The deep isolation trench is not only adjacent to the first N-heavily doped area, but has a depth greater than a depth of the first N-buried area, thereby separating the first N-buried area and the ESD device.
摘要翻译：公开了一种无泄漏电流的瞬态电压抑制器，其包括P型衬底。在P基板上形成有N型外延层，在第一N重掺杂区，第一P重掺杂区，静电放电（ESD）器件和至少一个深隔离沟槽中形成第一N重掺杂区， N外延层。在N外延层的底部形成第一N区，以邻近P衬底并且位于第一N重掺杂区和第一P重掺杂区的下方。 ESD器件耦合到第一N重掺杂区域。深隔离沟槽不仅与第一N重掺杂区相邻，而且具有大于第一N埋入区深度的深度，从而分离第一N埋区和ESD器。

5. 发明授权

US08169000B2 Lateral transient voltage suppressor with ultra low capacitance 有权
标题翻译：具有超低电容的横向瞬态电压抑制器
公开(公告)号：US08169000B2
公开(公告)日：2012-05-01
申请号：US12836785
申请日：2010-07-15
申请人： Che-Hao Chuang , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
发明人： Che-Hao Chuang , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
IPC分类号： H01L23/62
CPC分类号： H01L27/0255
摘要： A lateral transient voltage suppressor with ultra low capacitance is disclosed. The suppressor comprises a first conductivity type substrate and at least one diode cascade structure arranged in the first conductivity type substrate. The cascade structure further comprises at least one second conductivity type lightly doped well and at least one first conductivity type lightly doped well, wherein there are two heavily doped areas arranged in the second conductivity type lightly doped well and the first conductivity type lightly doped well. The cascade structure neighbors a second conductivity type well, wherein there are three heavily doped areas arranged in the second conductivity type well. The suppressor further comprises a plurality of deep isolation trenches arranged in the first conductivity type substrate and having a depth greater than depths of the second conductivity type lightly doped well, the second conductivity type well and the first conductivity type lightly doped well. Each doped well is isolated by trenches.
摘要翻译：公开了具有超低电容的横向瞬态电压抑制器。抑制器包括第一导电型衬底和布置在第一导电类型衬底中的至少一个二极管级联结构。级联结构还包括至少一个第二导电类型轻掺杂阱和至少一个第一导电类型轻掺杂阱，其中存在布置在第二导电类型轻掺杂阱和第一导电类型轻掺杂阱中的两个重掺杂区。级联结构邻近第二导电类型阱，其中存在布置在第二导电类型阱中的三个重掺杂区域。抑制器还包括布置在第一导电类型衬底中并且具有大于第二导电类型轻掺杂阱的深度的深度的多个深隔离沟槽，第二导电类型阱和第一导电类型轻掺杂阱。每个掺杂的阱由沟槽隔离。

6. 发明申请

US20120068299A1 TRANSIENT VOLTAGE SUPPRESSORS 有权
标题翻译：瞬态电压抑制器
公开(公告)号：US20120068299A1
公开(公告)日：2012-03-22
申请号：US12888151
申请日：2010-09-22
申请人： Kun-Hsien Lin , Che-Hao Chuang , Ryan Hsin-Chin Jiang
发明人： Kun-Hsien Lin , Che-Hao Chuang , Ryan Hsin-Chin Jiang
IPC分类号： H01L23/60
CPC分类号： H01L29/8613 , H01L27/0255 , H01L27/0259 , H01L29/866
摘要： The present invention relates a transient voltage suppressor (TVS) for directional ESD protection. The TVS includes: a conductivity type substrate; a first type lightly doped region, having a first type heavily doped region arranged therein; a second type lightly doped region, having a second type heavily doped region and a third type heavily doped region arranged therein; a third type lightly doped region, having a fourth type heavily doped region arranged therein; a plurality of closed isolation trenches, arranged on the conductivity type substrate, wherein at least one of the plurality of closed isolation trenches is neighbored one of the type lightly doped regions; and a first pin. Accordingly, the TVS of present invention may adaptively provide effective ESD protection under positive and negative ESD stresses, improve the efficiency of ESD protection within the limited layout area.
摘要翻译：本发明涉及用于定向ESD保护的瞬态电压抑制器（TVS）。 TVS包括：导电型基板; 第一类型轻掺杂区域，其中布置有第一类型重掺杂区域; 具有第二类型重掺杂区域和布置在其中的第三类型重掺杂区域的第二类型轻掺杂区域; 第三类型轻掺杂区域，其中布置有第四类型重掺杂区域; 多个封闭的隔离沟槽，布置在所述导电型衬底上，其中所述多个闭合隔离沟槽中的至少一个与所述轻掺杂区域中的一个相邻; 和第一个引脚。因此，本发明的TVS可以在正和负ESD应力下自适应地提供有效的ESD保护，从而在有限的布局区域内提高ESD保护的效率。

7. 发明申请

US20120012974A1 LATERAL TRANSIENT VOLTAGE SUPPRESSOR FOR LOW-VOLTAGE APPLICATIONS 有权
标题翻译：用于低电压应用的侧向瞬态电压抑制器
公开(公告)号：US20120012974A1
公开(公告)日：2012-01-19
申请号：US12837128
申请日：2010-07-15
申请人： Che-Hao CHUANG , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
发明人： Che-Hao CHUANG , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
IPC分类号： H01L29/06
CPC分类号： H01L27/0255
摘要： A lateral transient voltage suppressor for low-voltage applications is disclosed. The suppressor comprises an N-type heavily doped substrate and at least two clamp diode structures horizontally arranged in the N-type heavily doped substrate. Each clamp diode structure further comprises a clamp well arranged in the N-type heavily doped substrate and having a first heavily doped area and a second heavily doped area. The first and second heavily doped areas respectively belong to opposite types. There is a plurality of deep isolation trenches arranged in the N-type heavily doped substrate and having a depth greater than depth of the clamp well. The deep isolation trenches can separate each clamp well. The present invention avoids the huge leakage current to be suitable for low-voltage application.
摘要翻译：公开了一种用于低电压应用的横向瞬态电压抑制器。抑制器包括N型重掺杂衬底和水平地布置在N型重掺杂衬底中的至少两个钳位二极管结构。每个钳位二极管结构还包括在N型重掺杂衬底中布置的具有第一重掺杂区域和第二重掺杂区域的钳位阱。第一和第二重掺杂区域分别属于相反的类型。在N型重掺杂衬底中布置有多个深的隔离沟槽，其深度大于夹具阱的深度。深的隔离沟槽可以很好地分离每个夹具。本发明避免了巨大的漏电流适合于低电压应用。

8. 发明申请

US20120012973A1 LATERAL TRANSIENT VOLTAGE SUPPRESSOR WITH ULTRA LOW CAPACITANCE 有权
标题翻译：具有超低电容的侧向瞬态电压抑制器
公开(公告)号：US20120012973A1
公开(公告)日：2012-01-19
申请号：US12836785
申请日：2010-07-15
申请人： Che-Hao Chuang , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
发明人： Che-Hao Chuang , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
IPC分类号： H01L29/06
CPC分类号： H01L27/0255
摘要： A lateral transient voltage suppressor with ultra low capacitance is disclosed. The suppressor comprises a first type substrate and at least one diode cascade structure arranged in the first type substrate. The cascade structure further comprises at least one second type lightly doped well and at least one first type lightly doped well, wherein there are two heavily doped areas arranged in the second type lightly doped well and the first type lightly doped well. The cascade structure neighbors a second type well, wherein there are three heavily doped areas arranged in the second type well. The suppressor further comprises a plurality of deep isolation trenches arranged in the first type substrate and having a depth greater than depths of the second type lightly doped well, the second type well and the first type lightly doped well. Each doped well is isolated by trenches.
摘要翻译：公开了具有超低电容的横向瞬态电压抑制器。抑制器包括第一类型衬底和布置在第一类型衬底中的至少一个二极管级联结构。级联结构还包括至少一个第二类型轻掺杂阱和至少一个第一类型轻掺杂阱，其中在第二类型轻掺杂阱和第一类型轻掺杂阱中布置有两个重掺杂区。级联结构邻近第二类型井，其中在第二类井中布置有三个重掺杂区域。抑制器还包括布置在第一类型衬底中并且具有大于第二类型轻掺杂阱，第二类型阱和第一类型轻掺杂阱的深度的深度的多个深隔离沟槽。每个掺杂的阱由沟槽隔离。

9. 发明授权

US08552530B2 Vertical transient voltage suppressors 有权
标题翻译：垂直瞬态电压抑制器
公开(公告)号：US08552530B2
公开(公告)日：2013-10-08
申请号：US12848531
申请日：2010-08-02
申请人： Kun-Hsien Lin , Zi-Ping Chen , Che-Hao Chuang , Ryan Hsin-Chin Jiang
发明人： Kun-Hsien Lin , Zi-Ping Chen , Che-Hao Chuang , Ryan Hsin-Chin Jiang
IPC分类号： H01L29/06
CPC分类号： H01L27/0259
摘要： A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region.
摘要翻译：公开了一种用于保护电子设备的垂直瞬态电压抑制器。垂直瞬变电压包括具有高掺杂浓度的导电型衬底; 导电型衬底上布置有第一类型轻掺杂区域，其中导电类型衬底和第一类型轻掺杂区域分别属于相反类型; 第一类型重掺杂区和第二类重掺杂区布置在第一类型轻掺杂区域中，其中第一和第二类型重掺杂区和导电类型衬底属于相同类型; 并且深度第一类型重掺杂区域布置在导电类型衬底上并且与第一类型轻掺杂区域相邻，其中深第一类型重掺杂区域和第一类型轻掺杂区域分别属于相反类型，并且其中深第一类型重掺杂区域型重掺杂区域耦合到第一类型重掺杂区域。

10. 发明授权

US08304838B1 Electrostatic discharge protection device structure 有权
标题翻译：静电放电保护装置结构
公开(公告)号：US08304838B1
公开(公告)日：2012-11-06
申请号：US13216016
申请日：2011-08-23
申请人： Zi-Ping Chen , Tung-Yang Chen , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
发明人： Zi-Ping Chen , Tung-Yang Chen , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
IPC分类号： H01L21/00
CPC分类号： H01L27/0255
摘要： An electrostatic discharge protection device structure is disclosed, which comprises a semiconductor substrate and an N-type epitaxial layer arranged on the semiconductor substrate. At least one snapback cascade structure is arranged in the N-type epitaxial layer, wherein the snapback cascade structure further comprises first and second P-type wells arranged in the N-type epitaxial layer. First and second heavily doped areas arranged in the first P-type well respectively belong to opposite types. And, third and fourth heavily doped areas arranged in the second P-type well respectively belong to opposite types, wherein the second and third heavily doped areas respectively belong to opposite types and are electrically connected with each other. When the first heavily doped area receives an ESD signal, an ESD current flows from the first heavily doped area to the fourth heavily doped area through the first P-type well, the N-type epitaxial layer, and the second P-type well.
摘要翻译：公开了一种静电放电保护器件结构，其包括半导体衬底和布置在半导体衬底上的N型外延层。在N型外延层中布置有至少一个快速反应级联结构，其中快速回退级联结构还包括布置在N型外延层中的第一和第二P型阱。排列在第一P型井中的第一和第二重掺杂区域分别属于相反的类型。并且，排列在第二P型阱中的第三和第四重掺杂区域分别属于相反的类型，其中第二和第三重掺杂区域分别属于相反的类型并且彼此电连接。当第一重掺杂区域接收到ESD信号时，ESD电流通过第一P型阱，N型外延层和第二P型阱从第一重掺杂区流动到第四重掺杂区。

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