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1. 发明授权

US08232601B1 Transient voltage suppressors 有权
标题翻译：瞬态电压抑制器
公开(公告)号：US08232601B1
公开(公告)日：2012-07-31
申请号：US13475599
申请日：2012-05-18
申请人： Kun-Hsien Lin , Che-Hao Chuang , Ryan Hsin-Chin Jiang
发明人： Kun-Hsien Lin , Che-Hao Chuang , Ryan Hsin-Chin Jiang
IPC分类号： H01L23/62
CPC分类号： H01L29/8613 , H01L27/0255 , H01L27/0259 , H01L29/866
摘要： The present invention relates a transient voltage suppressor (TVS) for directional ESD protection. The TVS includes: a conductivity type substrate; a first type lightly doped region, having a first type heavily doped region arranged therein; a second type lightly doped region, having a second type heavily doped region and a third type heavily doped region arranged therein; a third type lightly doped region, having a fourth type heavily doped region arranged therein; a plurality of closed isolation trenches, arranged on the conductivity type substrate, wherein at least one of the plurality of closed isolation trenches is neighbored one of the type lightly doped regions; and a first pin. Accordingly, the TVS of present invention may adaptively provide effective ESD protection under positive and negative ESD stresses, improve the efficiency of ESD protection within the limited layout area.
摘要翻译：本发明涉及用于定向ESD保护的瞬态电压抑制器（TVS）。 TVS包括：导电型基板; 第一类型轻掺杂区域，其中布置有第一类型重掺杂区域; 具有第二类型重掺杂区域和布置在其中的第三类型重掺杂区域的第二类型轻掺杂区域; 第三类型轻掺杂区域，其中布置有第四类型重掺杂区域; 多个封闭的隔离沟槽，布置在所述导电型衬底上，其中所述多个闭合隔离沟槽中的至少一个与所述轻掺杂区域中的一个相邻; 和第一个引脚。因此，本发明的TVS可以在正和负ESD应力下自适应地提供有效的ESD保护，从而在有限的布局区域内提高ESD保护的效率。

2. 发明授权

US08785971B2 Transient voltage suppressor without leakage current 有权
标题翻译：瞬态电压抑制器无泄漏电流
公开(公告)号：US08785971B2
公开(公告)日：2014-07-22
申请号：US13303946
申请日：2011-11-23
申请人： Che-Hao Chuang , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
发明人： Che-Hao Chuang , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
IPC分类号： H01L23/58 , H01L27/02 , H01L29/866 , H01L29/861
CPC分类号： H01L27/0296 , H01L29/8613 , H01L29/866
摘要： A transient voltage suppressor without leakage current is disclosed, which comprises a P-substrate. There is an N-type epitaxial layer formed on the P-substrate, and a first N-heavily doped area, a first P-heavily doped area, an electrostatic discharge (ESD) device and at least one deep isolation trench are formed in the N-epitaxial layer. A first N-buried area is formed in the bottom of the N-epitaxial layer to neighbor the P-substrate and located below the first N-heavily doped area and the first P-heavily doped area. The ESD device is coupled to the first N-heavily doped area. The deep isolation trench is not only adjacent to the first N-heavily doped area, but has a depth greater than a depth of the first N-buried area, thereby separating the first N-buried area and the ESD device.
摘要翻译：公开了一种无泄漏电流的瞬态电压抑制器，其包括P型衬底。在P基板上形成有N型外延层，在第一N重掺杂区，第一P重掺杂区，静电放电（ESD）器件和至少一个深隔离沟槽中形成第一N重掺杂区， N外延层。在N外延层的底部形成第一N区，以邻近P衬底并且位于第一N重掺杂区和第一P重掺杂区的下方。 ESD器件耦合到第一N重掺杂区域。深隔离沟槽不仅与第一N重掺杂区相邻，而且具有大于第一N埋入区深度的深度，从而分离第一N埋区和ESD器。

3. 发明授权

US08169000B2 Lateral transient voltage suppressor with ultra low capacitance 有权
标题翻译：具有超低电容的横向瞬态电压抑制器
公开(公告)号：US08169000B2
公开(公告)日：2012-05-01
申请号：US12836785
申请日：2010-07-15
申请人： Che-Hao Chuang , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
发明人： Che-Hao Chuang , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
IPC分类号： H01L23/62
CPC分类号： H01L27/0255
摘要： A lateral transient voltage suppressor with ultra low capacitance is disclosed. The suppressor comprises a first conductivity type substrate and at least one diode cascade structure arranged in the first conductivity type substrate. The cascade structure further comprises at least one second conductivity type lightly doped well and at least one first conductivity type lightly doped well, wherein there are two heavily doped areas arranged in the second conductivity type lightly doped well and the first conductivity type lightly doped well. The cascade structure neighbors a second conductivity type well, wherein there are three heavily doped areas arranged in the second conductivity type well. The suppressor further comprises a plurality of deep isolation trenches arranged in the first conductivity type substrate and having a depth greater than depths of the second conductivity type lightly doped well, the second conductivity type well and the first conductivity type lightly doped well. Each doped well is isolated by trenches.
摘要翻译：公开了具有超低电容的横向瞬态电压抑制器。抑制器包括第一导电型衬底和布置在第一导电类型衬底中的至少一个二极管级联结构。级联结构还包括至少一个第二导电类型轻掺杂阱和至少一个第一导电类型轻掺杂阱，其中存在布置在第二导电类型轻掺杂阱和第一导电类型轻掺杂阱中的两个重掺杂区。级联结构邻近第二导电类型阱，其中存在布置在第二导电类型阱中的三个重掺杂区域。抑制器还包括布置在第一导电类型衬底中并且具有大于第二导电类型轻掺杂阱的深度的深度的多个深隔离沟槽，第二导电类型阱和第一导电类型轻掺杂阱。每个掺杂的阱由沟槽隔离。

4. 发明申请

US20120068299A1 TRANSIENT VOLTAGE SUPPRESSORS 有权
标题翻译：瞬态电压抑制器
公开(公告)号：US20120068299A1
公开(公告)日：2012-03-22
申请号：US12888151
申请日：2010-09-22
申请人： Kun-Hsien Lin , Che-Hao Chuang , Ryan Hsin-Chin Jiang
发明人： Kun-Hsien Lin , Che-Hao Chuang , Ryan Hsin-Chin Jiang
IPC分类号： H01L23/60
CPC分类号： H01L29/8613 , H01L27/0255 , H01L27/0259 , H01L29/866
摘要： The present invention relates a transient voltage suppressor (TVS) for directional ESD protection. The TVS includes: a conductivity type substrate; a first type lightly doped region, having a first type heavily doped region arranged therein; a second type lightly doped region, having a second type heavily doped region and a third type heavily doped region arranged therein; a third type lightly doped region, having a fourth type heavily doped region arranged therein; a plurality of closed isolation trenches, arranged on the conductivity type substrate, wherein at least one of the plurality of closed isolation trenches is neighbored one of the type lightly doped regions; and a first pin. Accordingly, the TVS of present invention may adaptively provide effective ESD protection under positive and negative ESD stresses, improve the efficiency of ESD protection within the limited layout area.
摘要翻译：本发明涉及用于定向ESD保护的瞬态电压抑制器（TVS）。 TVS包括：导电型基板; 第一类型轻掺杂区域，其中布置有第一类型重掺杂区域; 具有第二类型重掺杂区域和布置在其中的第三类型重掺杂区域的第二类型轻掺杂区域; 第三类型轻掺杂区域，其中布置有第四类型重掺杂区域; 多个封闭的隔离沟槽，布置在所述导电型衬底上，其中所述多个闭合隔离沟槽中的至少一个与所述轻掺杂区域中的一个相邻; 和第一个引脚。因此，本发明的TVS可以在正和负ESD应力下自适应地提供有效的ESD保护，从而在有限的布局区域内提高ESD保护的效率。

5. 发明申请

US20120012974A1 LATERAL TRANSIENT VOLTAGE SUPPRESSOR FOR LOW-VOLTAGE APPLICATIONS 有权
标题翻译：用于低电压应用的侧向瞬态电压抑制器
公开(公告)号：US20120012974A1
公开(公告)日：2012-01-19
申请号：US12837128
申请日：2010-07-15
申请人： Che-Hao CHUANG , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
发明人： Che-Hao CHUANG , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
IPC分类号： H01L29/06
CPC分类号： H01L27/0255
摘要： A lateral transient voltage suppressor for low-voltage applications is disclosed. The suppressor comprises an N-type heavily doped substrate and at least two clamp diode structures horizontally arranged in the N-type heavily doped substrate. Each clamp diode structure further comprises a clamp well arranged in the N-type heavily doped substrate and having a first heavily doped area and a second heavily doped area. The first and second heavily doped areas respectively belong to opposite types. There is a plurality of deep isolation trenches arranged in the N-type heavily doped substrate and having a depth greater than depth of the clamp well. The deep isolation trenches can separate each clamp well. The present invention avoids the huge leakage current to be suitable for low-voltage application.
摘要翻译：公开了一种用于低电压应用的横向瞬态电压抑制器。抑制器包括N型重掺杂衬底和水平地布置在N型重掺杂衬底中的至少两个钳位二极管结构。每个钳位二极管结构还包括在N型重掺杂衬底中布置的具有第一重掺杂区域和第二重掺杂区域的钳位阱。第一和第二重掺杂区域分别属于相反的类型。在N型重掺杂衬底中布置有多个深的隔离沟槽，其深度大于夹具阱的深度。深的隔离沟槽可以很好地分离每个夹具。本发明避免了巨大的漏电流适合于低电压应用。

6. 发明申请

US20120012973A1 LATERAL TRANSIENT VOLTAGE SUPPRESSOR WITH ULTRA LOW CAPACITANCE 有权
标题翻译：具有超低电容的侧向瞬态电压抑制器
公开(公告)号：US20120012973A1
公开(公告)日：2012-01-19
申请号：US12836785
申请日：2010-07-15
申请人： Che-Hao Chuang , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
发明人： Che-Hao Chuang , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
IPC分类号： H01L29/06
CPC分类号： H01L27/0255
摘要： A lateral transient voltage suppressor with ultra low capacitance is disclosed. The suppressor comprises a first type substrate and at least one diode cascade structure arranged in the first type substrate. The cascade structure further comprises at least one second type lightly doped well and at least one first type lightly doped well, wherein there are two heavily doped areas arranged in the second type lightly doped well and the first type lightly doped well. The cascade structure neighbors a second type well, wherein there are three heavily doped areas arranged in the second type well. The suppressor further comprises a plurality of deep isolation trenches arranged in the first type substrate and having a depth greater than depths of the second type lightly doped well, the second type well and the first type lightly doped well. Each doped well is isolated by trenches.
摘要翻译：公开了具有超低电容的横向瞬态电压抑制器。抑制器包括第一类型衬底和布置在第一类型衬底中的至少一个二极管级联结构。级联结构还包括至少一个第二类型轻掺杂阱和至少一个第一类型轻掺杂阱，其中在第二类型轻掺杂阱和第一类型轻掺杂阱中布置有两个重掺杂区。级联结构邻近第二类型井，其中在第二类井中布置有三个重掺杂区域。抑制器还包括布置在第一类型衬底中并且具有大于第二类型轻掺杂阱，第二类型阱和第一类型轻掺杂阱的深度的深度的多个深隔离沟槽。每个掺杂的阱由沟槽隔离。

7. 发明授权

US08552530B2 Vertical transient voltage suppressors 有权
标题翻译：垂直瞬态电压抑制器
公开(公告)号：US08552530B2
公开(公告)日：2013-10-08
申请号：US12848531
申请日：2010-08-02
申请人： Kun-Hsien Lin , Zi-Ping Chen , Che-Hao Chuang , Ryan Hsin-Chin Jiang
发明人： Kun-Hsien Lin , Zi-Ping Chen , Che-Hao Chuang , Ryan Hsin-Chin Jiang
IPC分类号： H01L29/06
CPC分类号： H01L27/0259
摘要： A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region.
摘要翻译：公开了一种用于保护电子设备的垂直瞬态电压抑制器。垂直瞬变电压包括具有高掺杂浓度的导电型衬底; 导电型衬底上布置有第一类型轻掺杂区域，其中导电类型衬底和第一类型轻掺杂区域分别属于相反类型; 第一类型重掺杂区和第二类重掺杂区布置在第一类型轻掺杂区域中，其中第一和第二类型重掺杂区和导电类型衬底属于相同类型; 并且深度第一类型重掺杂区域布置在导电类型衬底上并且与第一类型轻掺杂区域相邻，其中深第一类型重掺杂区域和第一类型轻掺杂区域分别属于相反类型，并且其中深第一类型重掺杂区域型重掺杂区域耦合到第一类型重掺杂区域。

8. 发明申请

US20130153957A1 SILICON-CONTROLLED-RECTIFIER WITH ADJUSTABLE HOLDING VOLTAGE 审中-公开
标题翻译：具有可调节保持电压的硅控制整流器
公开(公告)号：US20130153957A1
公开(公告)日：2013-06-20
申请号：US13331241
申请日：2011-12-20
申请人： Kun-Hsien Lin , Che-Hao Chuang , Ryan Hsin-Chin Jiang
发明人： Kun-Hsien Lin , Che-Hao Chuang , Ryan Hsin-Chin Jiang
IPC分类号： H01L29/73
CPC分类号： H01L27/0262 , H01L29/861
摘要： A silicon-controlled-rectifier (SCR) with adjustable holding voltage is disclosed, which comprises a heavily doped semiconductor layer and an epitaxial layer formed on the heavily doped semiconductor layer. A first N-well having a first P-heavily doped area is formed in the epitaxial layer. A second N-well or a first P-well is formed in the epitaxial layer. When the second N-well is formed in the epitaxial layer, a P-doped area is located between the first N-well and the second N-well. Besides, a first N-heavily doped area is formed in the second N-well or the first P-well. At least one deep isolation trench is formed in the epitaxial layer and located between the first P-heavily doped area and the first N-heavily doped area. A distance between the deep isolation trench and the heavily doped semiconductor layer is larger than zero.
摘要翻译：公开了具有可调保持电压的硅控整流器（SCR），其包括在重掺杂半导体层上形成的重掺杂半导体层和外延层。在外延层中形成具有第一P重掺杂区的第一N阱。在外延层中形成第二N阱或第一P阱。当第二N阱形成在外延层中时，P掺杂区域位于第一N阱和第二N阱之间。此外，在第二N阱或第一P阱中形成第一N重掺杂区。在外延层中形成至少一个深的隔离沟槽，并且位于第一P重掺杂区域和第一N重掺杂区域之间。深隔离沟槽和重掺杂半导体层之间的距离大于零。

9. 发明申请

US20130127007A1 TRANSIENT VOLTAGE SUPPRESSOR WITHOUT LEAKAGE CURRENT 有权
标题翻译：瞬态电压抑制器，无泄漏电流
公开(公告)号：US20130127007A1
公开(公告)日：2013-05-23
申请号：US13303946
申请日：2011-11-23
申请人： Che-Hao Chuang , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
发明人： Che-Hao Chuang , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
IPC分类号： H01L29/06
CPC分类号： H01L27/0296 , H01L29/8613 , H01L29/866
摘要： A transient voltage suppressor without leakage current is disclosed, which comprises a P-substrate. There is an N-type epitaxial layer formed on the P-substrate, and a first N-heavily doped area, a first P-heavily doped area, an electrostatic discharge (ESD) device and at least one deep isolation trench are formed in the N-epitaxial layer. A first N-buried area is formed in the bottom of the N-epitaxial layer to neighbor the P-substrate and located below the first N-heavily doped area and the first P-heavily doped area. The ESD device is coupled to the first N-heavily doped area. The deep isolation trench is not only adjacent to the first N-heavily doped area, but has a depth greater than a depth of the first N-buried area, thereby separating the first N-buried area and the ESD device.
摘要翻译：公开了一种无泄漏电流的瞬态电压抑制器，其包括P型衬底。在P基板上形成有N型外延层，在第一N重掺杂区，第一P重掺杂区，静电放电（ESD）器件和至少一个深隔离沟槽中形成第一N重掺杂区， N外延层。在N外延层的底部形成第一N区，以邻近P衬底并且位于第一N重掺杂区和第一P重掺杂区的下方。 ESD器件耦合到第一N重掺杂区域。深隔离沟槽不仅与第一N重掺杂区相邻，而且具有大于第一N埋入区深度的深度，从而分离第一N埋区和ESD器。

10. 发明申请

US20120241903A1 LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR 有权
标题翻译：低电容瞬态电压抑制器
公开(公告)号：US20120241903A1
公开(公告)日：2012-09-27
申请号：US13072138
申请日：2011-03-25
申请人： Yu-Shu SHEN , Kun-Hsien Lin , Che-Hao Chuang , Ryan Hsin-Chin Jiang
发明人： Yu-Shu SHEN , Kun-Hsien Lin , Che-Hao Chuang , Ryan Hsin-Chin Jiang
IPC分类号： H01L29/66
CPC分类号： H01L27/0255 , H01L29/861
摘要： A low capacitance transient voltage suppressor is disclosed. The suppressor comprises an N-type heavily doped substrate and an epitaxial layer formed on the substrate. At least one steering diode structure formed in the epitaxial layer comprises a diode lightly doped well and a first P-type lightly doped well, wherein a P-type heavily doped area is formed in the diode lightly doped well and a first N-type heavily doped area and a second P-type heavily doped area are formed in the first P-type lightly doped well. A second P-type lightly doped well having two N-type heavily doped areas is formed in the epitaxial layer. In addition, an N-type heavily doped well and at least one deep isolation trench are formed in the epitaxial layer, wherein the trench has a depth greater than or equal to depths of all the doped wells, so as to separate at least one doped well.
摘要翻译：公开了一种低电容瞬态电压抑制器。抑制器包括N型重掺杂衬底和形成在衬底上的外延层。形成在外延层中的至少一个转向二极管结构包括二极管轻掺杂阱和第一P型轻掺杂阱，其中在二极管轻掺杂阱中形成P型重掺杂区，并且第一N型重掺杂阱在第一P型轻掺杂阱中形成掺杂区域和第二P型重掺杂区域。在外延层中形成具有两个N型重掺杂区的第二P型轻掺杂阱。此外，在外延层中形成N型重掺杂阱和至少一个深隔离沟槽，其中沟槽的深度大于或等于所有掺杂阱的深度，以便分离至少一个掺杂的好。

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