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1. 发明授权

US07989923B2 Bi-directional transient voltage suppression device and forming method thereof 有权
标题翻译：双向瞬态电压抑制装置及其形成方法
公开(公告)号：US07989923B2
公开(公告)日：2011-08-02
申请号：US12342118
申请日：2008-12-23
申请人： Tang-Kuei Tseng , Kun-Hsien Lin , Hsin-Chin Jiang
发明人： Tang-Kuei Tseng , Kun-Hsien Lin , Hsin-Chin Jiang
IPC分类号： H01L29/167
CPC分类号： H01L29/87
摘要： A bidirectional transient voltage suppression device is disclosed. The bi-directional transient voltage suppression device comprises a semiconductor die. The semiconductor die has a multi-layer structure comprising a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type, an epitaxial layer, and five diffused regions. The buried layer and the semiconductor substrate form a first semiconductor junction. The first diffused region of the second conductivity type and the semiconductor substrate form a second semiconductor junction. The fourth diffused region of the first conductivity type and the third diffused region of the second conductivity type form a third semiconductor junction. The fifth diffused region of the first conductivity type and the second diffused region of the second conductivity type form a fourth semiconductor junction.
摘要翻译：公开了一种双向瞬态电压抑制装置。双向瞬态电压抑制装置包括半导体管芯。半导体管芯具有包括第一导电类型的半导体衬底，第二导电类型的掩埋层，外延层和五个扩散区域的多层结构。掩埋层和半导体衬底形成第一半导体结。第二导电类型的第一扩散区域和半导体衬底形成第二半导体结。第一导电类型的第四扩散区域和第二导电类型的第三扩散区域形成第三半导体结。第一导电类型的第五扩散区域和第二导电类型的第二扩散区域形成第四半导体结。

2. 发明授权

US08116049B2 Transient voltage detection circuit 有权
标题翻译：瞬态电压检测电路
公开(公告)号：US08116049B2
公开(公告)日：2012-02-14
申请号：US12625449
申请日：2009-11-24
申请人： Ming-Dou Ker , Hsin-Chin Jiang , Wen-Yi Chen
发明人： Ming-Dou Ker , Hsin-Chin Jiang , Wen-Yi Chen
IPC分类号： H02H3/22
CPC分类号： H02H9/046 , H02H1/0007
摘要： The invention discloses a transient voltage detection circuit suitable for an electronic system. The electronic system includes a high voltage line and a low voltage line. The transient voltage detection circuit includes at least one detection circuit and a judge module. Each detection circuit includes a P-typed transistor and/or an N-typed transistor, a capacitor and a detection node. The transistor is coupled with the capacitor, and the detection node is located between the transistor and the capacitor. The judge module is coupled to each of the detection nodes. The judge module generates a judgment according to voltage levels of the detection nodes. Accordingly, the transient voltage detection circuit is formed. The electronic system may selectively execute a protective action according to the judgment.
摘要翻译：本发明公开了一种适用于电子系统的瞬态电压检测电路。电子系统包括高压线路和低压线路。瞬态电压检测电路包括至少一个检测电路和判断模块。每个检测电路包括P型晶体管和/或N型晶体管，电容器和检测节点。晶体管与电容器耦合，检测节点位于晶体管和电容器之间。判断模块耦合到每个检测节点。判断模块根据检测节点的电压电平生成判断。因此，形成了瞬态电压检测电路。电子系统可以根据判断选择性地执行保护动作。

3. 发明授权

US07394630B2 Electrostatic discharge protection device for mixed voltage interface 有权
标题翻译：用于混合电压接口的静电放电保护装置
公开(公告)号：US07394630B2
公开(公告)日：2008-07-01
申请号：US10268756
申请日：2002-10-11
申请人： Ming-Dou Ker , Kuo-Chun Hsu , Hsin-Chin Jiang
发明人： Ming-Dou Ker , Kuo-Chun Hsu , Hsin-Chin Jiang
IPC分类号： H02H3/22
CPC分类号： H01L27/0266
摘要： An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.
摘要翻译：一种静电放电保护电路，其包括以堆叠结构连接的至少两个晶体管，由两个相邻晶体管共享的第一掺杂剂类型的第一扩散区域和形成在第一扩散区域中的第二掺杂剂类型的第二扩散区域。衬底触发位置被引入堆叠晶体管的器件结构，以提高ESD稳健性和开启速度。提出了实现堆叠晶体管的区域效率布局。堆叠晶体管可以在具有混合电压I / O接口的ESD保护电路中或在具有多个电源的集成电路中实现。在不使用厚栅掩模的情况下制造堆叠晶体管。

4. 发明授权

US06747861B2 Electrostatic discharge protection for a mixed-voltage device using a stacked-transistor-triggered silicon controlled rectifier 有权
标题翻译：使用堆叠晶体管触发的可控硅整流器的混合电压装置的静电放电保护
公开(公告)号：US06747861B2
公开(公告)日：2004-06-08
申请号：US09987616
申请日：2001-11-15
申请人： Ming-Dou Ker , Chien-Hui Chung , Hsin-Chin Jiang
发明人： Ming-Dou Ker , Chien-Hui Chung , Hsin-Chin Jiang
IPC分类号： H02H904
CPC分类号： H01L27/0262
摘要： An electrostatic discharge protection circuit that includes a rectifier, having an anode and a cathode, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first n-type portion, and a second n-type portion contiguous with the second p-type portion, wherein the first p-type portion is coupled to the anode and the second n-type portion is coupled to the cathode, a first transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the first n-type portion of the rectifier, a second transistor having a first terminal, a second terminal and a gate terminal, wherein the first terminal is coupled to the second terminal of the first transistor, and the second terminal is coupled to the second n-type portion of the rectifier, and a voltage coupling circuit having a first terminal, a second terminal, a third terminal, and a fourth terminal, wherein the first terminal is coupled to the anode of the rectifier, the second and the third terminals are respectively coupled to the gate terminals of the first and second transistors, and the fourth terminal is coupled to the cathode.
摘要翻译：一种静电放电保护电路，包括具有阳极和阴极的整流器，包括第一p型部分，与第一p型部分相邻的第一n型部分，与第一p型部分邻接的第二p型部分 n型部分和与第二p型部分邻接的第二n型部分，其中第一p型部分耦合到阳极，第二n型部分耦合到阴极，第一晶体管具有第一端子，第二端子和栅极端子，其中第一端子耦合到整流器的第一n型部分，具有第一端子，第二端子和栅极端子的第二晶体管，其中第一端子是耦合到第一晶体管的第二端子，并且第二端子耦合到整流器的第二n型部分，以及具有第一端子，第二端子，第三端子和第四端子的电压耦合电路，其中第一端子耦合到整流器的阳极，第二和第三端子分别耦合到第一和第二晶体管的栅极端子，并且第四端子耦合到阴极。

5. 发明授权

US07675724B2 Electrostatic discharge protection device for mixed voltage interface 有权
标题翻译：用于混合电压接口的静电放电保护装置
公开(公告)号：US07675724B2
公开(公告)日：2010-03-09
申请号：US12114485
申请日：2008-05-02
申请人： Ming-Dou Ker , Kuo-Chun Hsu , Hsin-Chin Jiang
发明人： Ming-Dou Ker , Kuo-Chun Hsu , Hsin-Chin Jiang
IPC分类号： H02H3/22
CPC分类号： H01L27/0266
摘要： An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.
摘要翻译：一种静电放电保护电路，其包括以堆叠结构连接的至少两个晶体管，由两个相邻晶体管共享的第一掺杂剂类型的第一扩散区域和形成在第一扩散区域中的第二掺杂剂类型的第二扩散区域。衬底触发位置被引入堆叠晶体管的器件结构，以提高ESD稳健性和开启速度。提出了实现堆叠晶体管的区域效率布局。堆叠晶体管可以在具有混合电压I / O接口的ESD保护电路中或在具有多个电源的集成电路中实现。在不使用厚栅掩模的情况下制造堆叠晶体管。

6. 发明申请

US20090040668A1 ESD PROTECTION CIRCUITS FOR MIXED-VOLTAGE BUFFERS 审中-公开
标题翻译：混合电压缓冲器的ESD保护电路
公开(公告)号：US20090040668A1
公开(公告)日：2009-02-12
申请号：US11837306
申请日：2007-08-10
申请人： Zi-Ping Chen , Ming-Dao Ker , Hsin-Chin Jiang
发明人： Zi-Ping Chen , Ming-Dao Ker , Hsin-Chin Jiang
IPC分类号： H02H9/04
CPC分类号： H01L27/0285
摘要： An ESD protection circuit that protects a mixed-voltage input/output (I/O) buffer circuit in an integrated circuit is provided. The ESD protection circuit includes an ESD discharging circuit coupled to the I/O pad and ESD detection circuit coupled to the discharging circuit providing a means for detecting an ESD and triggering the discharging circuit to conduct the ESD to ground. The ESD discharging circuit comprises stacked NMOS transistors or a field oxide device (FOD). The protection circuit can also be used in an ESD protection circuit for a high-voltage-tolerant input pad or to protect multiple input pads and/or multiple I/O pads in an integrated circuit.
摘要翻译：提供了一种保护集成电路中混合电压输入/输出（I / O）缓冲电路的ESD保护电路。 ESD保护电路包括耦合到I / O焊盘的ESD放电电路和耦合到放电电路的ESD检测电路，其提供用于检测ESD并触发放电电路以将ESD导电到地的装置。 ESD放电电路包括堆叠的NMOS晶体管或场氧化物器件（FOD）。保护电路也可以用于高耐压输入焊盘的ESD保护电路中，或者用于保护集成电路中的多个输入焊盘和/或多个I / O焊盘。

7. 发明申请

US20070188952A1 ON-CHIP LATCH-UP PROTECTION CIRCUIT 有权
标题翻译：片上保护电路
公开(公告)号：US20070188952A1
公开(公告)日：2007-08-16
申请号：US11618674
申请日：2006-12-29
申请人： Ming-Dou Ker , Jang-Jie Peng , Hsin-Chin Jiang
发明人： Ming-Dou Ker , Jang-Jie Peng , Hsin-Chin Jiang
IPC分类号： G01S13/08 , H02H9/00
CPC分类号： H01L27/0248 , H03K17/0822
摘要： An on-chip latch-up protection circuit. The lath-up protection circuit includes a core circuit, a power switch, and a current extractor. The power switch controls major current flowing through the core circuit. The current extractor detects amplitude of the major current. The power switch, the core circuit and the current extractor are coupled in series between a relatively-high power line and a relatively-low power line. When the major current surpasses a predetermined amplitude, the power switch is turned off, causing latch-up stops.
摘要翻译：一个片内闭锁保护电路。上拉保护电路包括核心电路，电源开关和电流提取器。电源开关控制流经核心电路的大电流。当前提取器检测主电流的幅度。电源开关，核心电路和电流提取器串联在相对较高的电力线和相对低的电力线之间。当主电流超过预定幅度时，电源开关被关闭，导致闭锁停止。

8. 发明授权

US07663853B2 On-chip latch-up protection circuit 有权
标题翻译：片内闭锁保护电路
公开(公告)号：US07663853B2
公开(公告)日：2010-02-16
申请号：US11618674
申请日：2006-12-29
申请人： Ming-Dou Ker , Jang-Jie Peng , Hsin-Chin Jiang
发明人： Ming-Dou Ker , Jang-Jie Peng , Hsin-Chin Jiang
IPC分类号： H02H7/00
CPC分类号： H01L27/0248 , H03K17/0822
摘要： An on-chip latch-up protection circuit. The lath-up protection circuit includes a core circuit, a power switch, and a current extractor. The power switch controls major current flowing through the core circuit. The current extractor detects amplitude of the major current. The power switch, the core circuit and the current extractor are coupled in series between a relatively-high power line and a relatively-low power line. When the major current surpasses a predetermined amplitude, the power switch is turned off, causing latch-up stops.
摘要翻译：一个片内闭锁保护电路。上拉保护电路包括核心电路，电源开关和电流提取器。电源开关控制流经核心电路的大电流。当前提取器检测主电流的幅度。电源开关，核心电路和电流提取器串联在相对较高的电力线和相对低的电力线之间。当主电流超过预定幅度时，电源开关被关闭，导致闭锁停止。

9. 发明授权

US07253999B2 On-chip latch-up protection circuit 有权
标题翻译：片内闭锁保护电路
公开(公告)号：US07253999B2
公开(公告)日：2007-08-07
申请号：US10446049
申请日：2003-05-28
申请人： Ming-Dou Ker , Jeng-Jie Peng , Hsin-Chin Jiang
发明人： Ming-Dou Ker , Jeng-Jie Peng , Hsin-Chin Jiang
IPC分类号： H02H9/00
CPC分类号： H01L27/0248 , H03K17/0822
摘要： An on-chip latch-up protection circuit. The lath-up protection circuit includes a core circuit, a power switch, and a current extractor. The power switch controls major current flowing through the core circuit. The current extractor detects amplitude of the major current. The power switch, the core circuit and the current extractor are coupled in series between a relatively-high power line and a relatively-low power line. When the major current surpasses a predetermined amplitude, the power switch is turned off, causing latch-up stops.
摘要翻译：一个片内闭锁保护电路。上拉保护电路包括核心电路，电源开关和电流提取器。电源开关控制流经核心电路的大电流。当前提取器检测主电流的幅度。电源开关，核心电路和电流提取器串联在相对较高的电力线和相对低的电力线之间。当主电流超过预定幅度时，电源开关被关闭，导致闭锁停止。

10. 发明授权

US06838908B2 Mixed-voltage I/O design with novel floating N-well and gate-tracking circuits 有权
标题翻译：具有新型浮动N阱和栅极跟踪电路的混合电压I / O设计
公开(公告)号：US06838908B2
公开(公告)日：2005-01-04
申请号：US10400873
申请日：2003-03-28
申请人： Ming-Dou Ker , Che-Hao Chuang , Kuo-Chung Lee , Hsin-Chin Jiang
发明人： Ming-Dou Ker , Che-Hao Chuang , Kuo-Chung Lee , Hsin-Chin Jiang
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/094
CPC分类号： H03K19/00361
摘要： A mixed-voltage I/O buffer circuit that prevents leakages through a driver stage PMOS transistor is provided. The buffer circuit has a first part that prevents leakage through a parasitic diode of the transistor and a second part that prevents leakage through the transistor when the transistor is turned on by a signal on a bonding pad having a voltage level higher than a power supply voltage of the buffer circuit. The buffer circuit provides biases approximately equal to the high voltage signal to a gate and a substrate terminal of the PMOS transistor when the bonding pad has the high voltage signal thereon, and provides a bias approximately equal to the power supply voltage of the buffer circuit to the gate and substrate of the PMOS transistor when the bonding pad has a low voltage signal thereon.
摘要翻译：提供了一种混合电压I / O缓冲电路，其防止通过驱动级PMOS晶体管的泄漏。缓冲电路具有第一部分，其防止通过晶体管的寄生二极管的泄漏;以及第二部分，当第二部分通过具有高于电源电压的电压电平的焊盘上的信号导通晶体管时，防止漏电流通过晶体管的缓冲电路。当焊盘在其上具有高电压信号时，缓冲电路向PMOS晶体管的栅极和衬底端子提供大致等于高电压信号的偏压，并且提供大致等于缓冲电路的电源电压的偏置，当焊盘在其上具有低电压信号时，PMOS晶体管的栅极和衬底。

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