专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07851279B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07851279B2
公开(公告)日：2010-12-14
申请号：US12213727
申请日：2008-06-24
申请人： Tamae Takano , Tetsuya Kakehata , Shunpei Yamazaki
发明人： Tamae Takano , Tetsuya Kakehata , Shunpei Yamazaki
IPC分类号： H01L21/00
CPC分类号： H01L27/1157 , H01L27/105 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L27/1214 , H01L27/1251 , H01L27/13 , H01L29/4234 , H01L29/792 , H01L29/7923
摘要： The invention provides a semiconductor device and its manufacturing method in which a memory transistor and a plurality of thin film transistors that have gate insulating films with different thicknesses are fabricated over a substrate. The invention is characterized by the structural difference between the memory transistor and the plurality of thin film transistors. Specifically, the memory transistor and some of the plurality of thin film transistors are provided to have a bottom gate structure while the other thin film transistors are provided to have a top gate structure, which enables the reduction of characteristic defects of the transistor and simplification of its manufacturing process.
摘要翻译：本发明提供一种半导体器件及其制造方法，其中在衬底上制造具有不同厚度的栅极绝缘膜的存储晶体管和多个薄膜晶体管。本发明的特征在于存储晶体管与多个薄膜晶体管之间的结构差异。具体地，存储晶体管和多个薄膜晶体管中的一些被设置为具有底栅结构，而另一个薄膜晶体管被设置为具有顶栅结构，这使得能够减小晶体管的特性缺陷并简化其制造工艺。

2. 发明授权

US08022469B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08022469B2
公开(公告)日：2011-09-20
申请号：US12963847
申请日：2010-12-09
申请人： Tamae Takano , Tetsuya Kakehata , Shunpei Yamazaki
发明人： Tamae Takano , Tetsuya Kakehata , Shunpei Yamazaki
IPC分类号： H01L29/792
CPC分类号： H01L27/1157 , H01L27/105 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L27/1214 , H01L27/1251 , H01L27/13 , H01L29/4234 , H01L29/792 , H01L29/7923
摘要： The invention provides a semiconductor device and its manufacturing method in which a memory transistor and a plurality of thin film transistors that have gate insulating films with different thicknesses are fabricated over a substrate. The invention is characterized by the structural difference between the memory transistor and the plurality of thin film transistors. Specifically, the memory transistor and some of the plurality of thin film transistors are provided to have a bottom gate structure while the other thin film transistors are provided to have a top gate structure, which enables the reduction of characteristic defects of the transistor and simplification of its manufacturing process.
摘要翻译：本发明提供一种半导体器件及其制造方法，其中在衬底上制造具有不同厚度的栅极绝缘膜的存储晶体管和多个薄膜晶体管。本发明的特征在于存储晶体管与多个薄膜晶体管之间的结构差异。具体地，存储晶体管和多个薄膜晶体管中的一些被设置为具有底栅结构，而另一个薄膜晶体管被设置为具有顶栅结构，这使得能够减小晶体管的特性缺陷并简化其制造工艺。

3. 发明授权

US08581332B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US08581332B2
公开(公告)日：2013-11-12
申请号：US13207450
申请日：2011-08-11
申请人： Tamae Takano , Tetsuya Kakehata , Shunpei Yamazaki
发明人： Tamae Takano , Tetsuya Kakehata , Shunpei Yamazaki
IPC分类号： H01L29/792
CPC分类号： H01L27/1157 , H01L27/105 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L27/1214 , H01L27/1251 , H01L27/13 , H01L29/4234 , H01L29/792 , H01L29/7923
摘要： The invention provides a semiconductor device and its manufacturing method in which a memory transistor and a plurality of thin film transistors that have gate insulating films with different thicknesses are fabricated over a substrate. The invention is characterized by the structural difference between the memory transistor and the plurality of thin film transistors. Specifically, the memory transistor and some of the plurality of thin film transistors are provided to have a bottom gate structure while the other thin film transistors are provided to have a top gate structure, which enables the reduction of characteristic defects of the transistor and simplification of its manufacturing process.

4. 发明申请

US20110291173A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110291173A1
公开(公告)日：2011-12-01
申请号：US13207450
申请日：2011-08-11
申请人： Tamae Takano , Tetsuya Kakehata , Shunpei Yamazaki
发明人： Tamae Takano , Tetsuya Kakehata , Shunpei Yamazaki
IPC分类号： H01L29/788
CPC分类号： H01L27/1157 , H01L27/105 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L27/1214 , H01L27/1251 , H01L27/13 , H01L29/4234 , H01L29/792 , H01L29/7923
摘要： The invention provides a semiconductor device and its manufacturing method in which a memory transistor and a plurality of thin film transistors that have gate insulating films with different thicknesses are fabricated over a substrate. The invention is characterized by the structural difference between the memory transistor and the plurality of thin film transistors. Specifically, the memory transistor and some of the plurality of thin film transistors are provided to have a bottom gate structure while the other thin film transistors are provided to have a top gate structure, which enables the reduction of characteristic defects of the transistor and simplification of its manufacturing process.
摘要翻译：本发明提供一种半导体器件及其制造方法，其中在衬底上制造具有不同厚度的栅极绝缘膜的存储晶体管和多个薄膜晶体管。本发明的特征在于存储晶体管与多个薄膜晶体管之间的结构差异。具体地，存储晶体管和多个薄膜晶体管中的一些被设置为具有底栅结构，而另一个薄膜晶体管被设置为具有顶栅结构，这使得能够减小晶体管的特性缺陷并简化其制造工艺。

5. 发明申请

US20090001452A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090001452A1
公开(公告)日：2009-01-01
申请号：US12213727
申请日：2008-06-24
申请人： Tamae Takano , Tetsuya Kakehata , Shunpei Yamazaki
发明人： Tamae Takano , Tetsuya Kakehata , Shunpei Yamazaki
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L27/1157 , H01L27/105 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L27/1214 , H01L27/1251 , H01L27/13 , H01L29/4234 , H01L29/792 , H01L29/7923
摘要： The invention provides a semiconductor device and its manufacturing method in which a memory transistor and a plurality of thin film transistors that have gate insulating films with different thicknesses are fabricated over a substrate. The invention is characterized by the structural difference between the memory transistor and the plurality of thin film transistors. Specifically, the memory transistor and some of the plurality of thin film transistors are provided to have a bottom gate structure while the other thin film transistors are provided to have a top gate structure, which enables the reduction of characteristic defects of the transistor and simplification of its manufacturing process.
摘要翻译：本发明提供一种半导体器件及其制造方法，其中在衬底上制造具有不同厚度的栅极绝缘膜的存储晶体管和多个薄膜晶体管。本发明的特征在于存储晶体管与多个薄膜晶体管之间的结构差异。具体地，存储晶体管和多个薄膜晶体管中的一些被设置为具有底栅结构，而另一个薄膜晶体管被设置为具有顶栅结构，这使得能够减小晶体管的特性缺陷并简化其制造工艺。

6. 发明申请

US20090050941A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090050941A1
公开(公告)日：2009-02-26
申请号：US12222917
申请日：2008-08-19
申请人： Shunpei Yamazaki , Hideto Ohnuma , Tetsuya Kakehata
发明人： Shunpei Yamazaki , Hideto Ohnuma , Tetsuya Kakehata
IPC分类号： H01L29/04 , H01L21/762
CPC分类号： H01L29/66772 , H01L21/31662 , H01L21/76254 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/1203 , H01L27/1214 , H01L27/1229 , H01L27/1266 , H01L2224/16225 , H01L2224/16227 , H01L2224/32245 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2224/13099 , H01L2224/29099 , H01L2224/80001
摘要： A semiconductor device including a plurality of field-effect transistors which are stacked with a planarization layer interposed therebetween over a substrate having an insulating surface, in which semiconductor layers in the plurality of field-effect transistors are separated from semiconductor substrates, and the semiconductor layers are bonded to an insulating layer formed over the substrate having an insulating surface or an insulating layer formed over the planarization layer.
摘要翻译：一种半导体器件，包括多个场效应晶体管，所述多个场效应晶体管在其间具有绝缘表面的衬底上层叠有平坦化层，所述多个场效应晶体管中的半导体层与半导体衬底分离，并且所述半导体层被结合到形成在具有形成在平坦化层上的绝缘表面或绝缘层的衬底上的绝缘层。

7. 发明授权

US08236668B2 Method for manufacturing SOI substrate 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US08236668B2
公开(公告)日：2012-08-07
申请号：US12244414
申请日：2008-10-02
申请人： Hideto Ohnuma , Takashi Shingu , Tetsuya Kakehata , Kazutaka Kuriki , Shunpei Yamazaki
发明人： Hideto Ohnuma , Takashi Shingu , Tetsuya Kakehata , Kazutaka Kuriki , Shunpei Yamazaki
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L27/1266 , H01L21/2007 , H01L21/76254 , H01L27/1214 , H01L29/66772
摘要： An object of the present invention is to provide a method for manufacturing an SOI substrate provided with a semiconductor layer which can be used practically even where a substrate having a low upper temperature limit such as a glass substrate is used. The manufacturing method compromises the steps of preparing a semiconductor substrate provided with a bonding layer formed on a surface thereof and a separation layer formed at a predetermined depth from the surface thereof, bonding the bonding layer to the base substrate having a distortion point of 700° C. or lower so that the semiconductor substrate and the base substrate face each other, and separating a part of the semiconductor substrate at the separation layer by heat treatment in order to form a single-crystal semiconductor layer over the base substrate. In the manufacturing method, a substrate which shrinks isotropically at least by the heat treatment is used as the base substrate.
摘要翻译：本发明的目的是提供一种制造具有半导体层的SOI衬底的方法，即使在使用诸如玻璃衬底的上限温度低的衬底的情况下也可以使用。制造方法损害了制备其表面上形成有接合层的半导体衬底和从其表面形成在预定深度的分离层的步骤，将接合层粘合到具有700°的变形点的基底 C.或更低，使得半导体衬底和基底基板彼此面对，并且通过热处理在分离层处分离半导体衬底的一部分，以在基底衬底上形成单晶半导体层。在制造方法中，使用至少通过热处理各向同性收缩的基板作为基底。

8. 发明授权

US07851332B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07851332B2
公开(公告)日：2010-12-14
申请号：US12237606
申请日：2008-09-25
申请人： Shunpei Yamazaki , Junichi Koezuka , Tetsuya Kakehata
发明人： Shunpei Yamazaki , Junichi Koezuka , Tetsuya Kakehata
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L21/76254 , H01L29/42384 , H01L29/66772 , H01L29/78621
摘要： A semiconductor device including a semiconductor substrate is provided. The semiconductor substrate includes a substrate having an insulating surface, and a plurality of stacks over the substrate having an insulating surface. Each of the plurality of stacks includes a bonding layer over the substrate having an insulating surface, an insulating layer over the bonding layer, and a single crystal semiconductor layer over the insulating layer. The substrate having an insulating surface has a depression, and the depression is provided between one of the plurality of stacks and another adjacent one of the plurality of stacks.
摘要翻译：提供了包括半导体衬底的半导体器件。半导体衬底包括具有绝缘表面的衬底和在衬底上的多个堆叠，其具有绝缘表面。多个堆叠中的每一个在基板上包括具有绝缘表面的接合层，接合层上的绝缘层以及绝缘层上的单晶半导体层。具有绝缘表面的基板具有凹陷，并且凹陷设置在多个叠层中的一个和多个叠层中的另一个相邻的堆叠之间。

9. 发明授权

US08470648B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08470648B2
公开(公告)日：2013-06-25
申请号：US12899993
申请日：2010-10-07
申请人： Shunpei Yamazaki , Hideto Ohnuma , Tetsuya Kakehata
发明人： Shunpei Yamazaki , Hideto Ohnuma , Tetsuya Kakehata
IPC分类号： H01L21/762
CPC分类号： H01L27/1266 , H01L21/31662 , H01L21/76254 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/1203 , H01L27/1214 , H01L27/1229 , H01L29/66772 , H01L2224/16225 , H01L2224/16227 , H01L2224/32245 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2224/13099 , H01L2224/29099 , H01L2224/80001
摘要： A semiconductor device including a plurality of field-effect transistors which are stacked with a planarization layer interposed therebetween over a substrate having an insulating surface, in which semiconductor layers in the plurality of field-effect transistors are separated from semiconductor substrates, and the semiconductor layers are bonded to an insulating layer formed over the substrate having an insulating surface or an insulating layer formed over the planarization layer.
摘要翻译：一种半导体器件，包括多个场效应晶体管，所述多个场效应晶体管在其间具有绝缘表面的衬底上层叠有平坦化层，所述多个场效应晶体管中的半导体层与半导体衬底分离，并且所述半导体层被结合到形成在具有形成在平坦化层上的绝缘表面或绝缘层的衬底上的绝缘层。

10. 发明授权

US07608490B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07608490B2
公开(公告)日：2009-10-27
申请号：US11440175
申请日：2006-05-25
申请人： Shunpei Yamazaki , Tetsuya Kakehata , Hideto Ohnuma , Masaharu Nagai , Mitsuaki Osame , Masayuki Sakakura , Shigeki Komori
发明人： Shunpei Yamazaki , Tetsuya Kakehata , Hideto Ohnuma , Masaharu Nagai , Mitsuaki Osame , Masayuki Sakakura , Shigeki Komori
IPC分类号： H01L21/00
CPC分类号： H01L21/02683 , H01L21/02238 , H01L21/02247 , H01L21/02252 , H01L21/02332 , H01L21/0234 , H01L21/02686 , H01L21/2026 , H01L27/1214 , H01L27/124 , H01L27/127 , H01L27/1285 , H01L27/1288
摘要： To provide a semiconductor device having a circuit with high operating performance and high reliability, and improve the reliability of the semiconductor device, thereby improving the reliability of an electronic device having the same. The aforementioned object is achieved by combining a step of crystallizing a semiconductor layer by irradiation with continuous wave laser beams or pulsed laser beams with a repetition rate of 10 MHz or more, while scanning in one direction; a step of photolithography with the use of a photomask or a leticle including an auxiliary pattern which is formed of a diffraction grating pattern or a semi-transmissive film having a function of reducing the light intensity; and a step of performing oxidation, nitridation, or surface-modification to the surface of the semiconductor film, an insulating film, or a conductive film, with high-density plasma with a low electron temperature.
摘要翻译：为了提供具有高操作性能和高可靠性的电路的半导体器件，并且提高了半导体器件的可靠性，从而提高了具有该半导体器件的电子器件的可靠性。上述目的是通过在沿一个方向扫描的同时，通过照射连续波激光束或重复频率为10MHz或更高的脉冲激光束来结合半导体层结晶步骤来实现的; 使用光掩模或包含由衍射光栅图案形成的辅助图案或具有降低光强度功能的半透射膜的吸收体的光刻步骤; 以及对具有低电子温度的高密度等离子体对半导体膜，绝缘膜或导电膜的表面进行氧化，氮化或表面改性的步骤。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式