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    • 2. 发明授权
    • Analog to digital converter circuit of successive approximation type operating at low voltage
    • 在低电压下工作的逐次逼近型模数转换器电路
    • US07015841B2
    • 2006-03-21
    • US11029492
    • 2005-01-06
    • Takeshi YoshidaAtsushi IwataMamoru SasakiMiho AkagiKunihiko Goto
    • Takeshi YoshidaAtsushi IwataMamoru SasakiMiho AkagiKunihiko Goto
    • H03M1/10
    • H03M1/1245H03M1/466H03M1/804
    • In a sampling and holding, a control logic circuit connects another end of each capacitor of a DA converter to a ground potential, and outputs a sampled input analog signal from a switched amplifier to one end of a hold capacitor to hold. In a successive approximation, it controls a switched amplifier to set an output terminal thereof to a high-impedance state and the hold capacitor to connect the one end thereof to the ground potential. Then, it switches over connection of another end of each capacitor from the ground potential to a power supply voltage based on a digital value held by a successive approximation register to output an output voltage from another end of the hold capacitor to a comparator, and compares the output voltage from another end thereof with an intermediate reference voltage to obtain a digital value from the successive approximation register.
    • 在采样和保持中,控制逻辑电路将DA转换器的每个电容器的另一端连接到地电位,并且将来自开关放大器的采样输入模拟信号输出到保持电容器的一端以保持。 在逐次逼近中,它控制开关放大器将其输出端子设置为高阻抗状态,并且保持电容器将其一端连接到地电位。 然后,基于由逐次逼近寄存器保持的数字值将每个电容器的另一端从地电位切换到电源电压,以将输出电压从保持电容器的另一端输出到比较器,并将其进行比较 来自其另一端的输出电压具有中间参考电压,以从逐次逼近寄存器获得数字值。
    • 6. 发明授权
    • Coupling with a valve for dispensing liquids
    • 与用于分配液体的阀连接
    • US5379918A
    • 1995-01-10
    • US77453
    • 1993-06-17
    • Kunihiko Goto
    • Kunihiko Goto
    • F16L37/44B67D3/04B67D99/00F16L37/22F16L37/28B67D5/00
    • B67B7/26
    • A coupling including a plug attached to a sealed container and having an opening, and a socket having a cutter section for breaking a thin film for sealing the opening when the plug is connected to the socket. The plug has an engagement groove formed in an outer periphery of a plug cylinder, and the socket includes a socket outer cylinder having a lock engageable with the engaging groove, and a socket inner cylinder which is engaged with a smaller-diameter portion of the outer cylinder and is axially movable within the socket outer cylinder. Stoppers are provided within an annular space defined between the socket inner cylinder and the socket outer cylinder. The stopper restricts forward movement of the socket inner cylinder in the state in which the socket is separated from the plug, and the stopper fixes the lock in the state in which the socket is connected to the plug.
    • 一种联接器,包括附接到密封容器并具有开口的插头,以及具有用于当插头连接到插座时用于断开薄膜以密封开口的切割器部分的插座。 插塞具有形成在插塞筒的外周中的接合槽,并且插座包括具有可与接合槽接合的锁的插座外筒和与外部的小直径部分接合的插座内筒 并且在插座外筒内可轴向移动。 止动件设置在限定在插座内筒和插座外筒之间的环形空间内。 止动器在插座与插头分离的状态下限制插座内筒的向前运动,并且止动器将锁定件固定在插座连接到插头的状态。
    • 7. 发明授权
    • Sample and hold circuit
    • 采样保持电路
    • US4393318A
    • 1983-07-12
    • US154949
    • 1980-05-30
    • Masayuki TakahashiKunihiko GotoHisami TanakaMichinobu Ohhata
    • Masayuki TakahashiKunihiko GotoHisami TanakaMichinobu Ohhata
    • G11C27/02H03K17/687
    • G11C27/02
    • A sample and hold circuit for holding a sampled voltage, having a first MOS transistor for sampling the input voltage and a holding capacitor for holding the sampled voltage, and further comprising a second MOS transistor. The source and the drain of the second transistor are both connected to the output terminal of the circuit. The gate-source capacitance of the first MOS transistor is the sum of the gate-source and gate-drain capacitances of the second MOS transistor. When a voltage for turning on or off the first MOS transistor is applied to the gate of the first MOS transistor, the second MOS transistor is turned off or on respectively. The effect of this invention is that the sampled voltage can be held constant while turning off the first MOS transistor.
    • 一种用于保持采样电压的采样和保持电路,具有用于对输入电压进行采样的第一MOS晶体管和用于保持采样电压的保持电容器,还包括第二MOS晶体管。 第二晶体管的源极和漏极都连接到电路的输出端子。 第一MOS晶体管的栅极 - 源极电容是第二MOS晶体管的栅极 - 源极和栅极 - 漏极电容的总和。 当将第一MOS晶体管的导通或截止电压施加到第一MOS晶体管的栅极时,第二MOS晶体管分别关断或接通。 本发明的效果是,在关闭第一MOS晶体管的同时,采样电压可以保持恒定。