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1. 发明申请

US20110024820A1 METHOD OF MANUFACTURING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, AND A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：制造非易失性半导体存储器件的方法和非易失性半导体存储器件
公开(公告)号：US20110024820A1
公开(公告)日：2011-02-03
申请号：US12904923
申请日：2010-10-14
申请人： Takeshi SAKAI , Yasushi ISHII , Tsutomu OKAZAKI , Masaru NAKAMICHI , Toshikazu MATSUI , Kyoya NITTA , Satoru MACHIDA , Munekatsu NAKAGAWA , Yuichi TSUKADA
发明人： Takeshi SAKAI , Yasushi ISHII , Tsutomu OKAZAKI , Masaru NAKAMICHI , Toshikazu MATSUI , Kyoya NITTA , Satoru MACHIDA , Munekatsu NAKAGAWA , Yuichi TSUKADA
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L21/823842 , H01L21/82385 , H01L21/823857 , H01L21/823864 , H01L27/105 , H01L27/1052 , H01L27/11573
摘要： For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.
摘要翻译：为了增强具有MONOS型晶体管的非易失性半导体存储器件的高性能，非易失性半导体存储器件被提供有具有改进性能的MONOS型晶体管，其中MONOS非易失性存储器的存储单元包括控制晶体管和存储晶体管。控制晶体管的控制栅极包括n型多晶硅膜，并且形成在包括氧化硅膜的栅极绝缘膜上。存储晶体管的存储栅极包括n型多晶硅膜，并设置在控制栅极的一个侧壁上。存储器栅极包括具有低于控制栅极的薄层电阻的掺杂多晶硅膜，其包括通过将杂质离子注入未掺杂的硅膜形成的多晶硅膜。

2. 发明申请

US20090122609A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090122609A1
公开(公告)日：2009-05-14
申请号：US12354867
申请日：2009-01-16
申请人： Tsutomu OKAZAKI , Daisuke OKADA , Kyoya NITTA , Toshihiro TANAKA , Akira KATA , Toshikazu MATSUI , Yasushi ISHII , Digh HISAMOTO , Kan YASUI
发明人： Tsutomu OKAZAKI , Daisuke OKADA , Kyoya NITTA , Toshihiro TANAKA , Akira KATA , Toshikazu MATSUI , Yasushi ISHII , Digh HISAMOTO , Kan YASUI
IPC分类号： G11C16/04 , H01L27/115
CPC分类号： H01L27/1157 , G11C16/0425 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/0649 , H01L29/4234 , H01L29/42344 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
摘要翻译：半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极。第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分第一个方向第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

3. 发明申请

US20110248344A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20110248344A1
公开(公告)日：2011-10-13
申请号：US13048926
申请日：2011-03-16
申请人： Kyoya NITTA , Yutaka HOSHINO
发明人： Kyoya NITTA , Yutaka HOSHINO
IPC分类号： H01L27/12
CPC分类号： H01L29/42384 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/4908 , H01L29/78612 , H01L29/78654 , H01L2924/0002 , H01L2924/00
摘要： An object of the invention is to provide a semiconductor device having improved performance, high reliability, and a reduced chip size, in particular, to provide a semiconductor device having an MOSFET over an SOI substrate capable of maintaining its reliability while controlling the potential of a well below a gate electrode and preventing generation of parasitic capacitance. Generation of parasitic capacitance is prevented by controlling the potential of a well below a gate electrode by using a well contact plug passing through a hole portion formed in a gate electrode wiring. Generation of defects in a gate insulating film is prevented by making use of a gettering effect produced by causing an element isolation region to extend along the gate electrode.
摘要翻译：本发明的目的是提供一种具有改进的性能，高可靠性和减小的芯片尺寸的半导体器件，特别是提供一种在SOI衬底上具有MOSFET的半导体器件，其能够保持其可靠性，同时控制一个远低于栅电极并防止寄生电容的产生。通过使用穿过形成在栅电极布线中的孔部的阱接触塞来控制阱下方的阱的电位来防止寄生电容的产生。通过利用通过使元件隔离区域沿着栅电极延伸而产生的吸杂效应来防止栅绝缘膜中的缺陷的产生。

4. 发明申请

US20120302061A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120302061A1
公开(公告)日：2012-11-29
申请号：US13563876
申请日：2012-08-01
申请人： Hiroyuki ARIE , Nobuaki UMEMURA , Nobuyoshi HATTORI , Nobuto NAKANISHI , Kimio HARA , Kyoya NITTA , Makoto ISHIKAWA
发明人： Hiroyuki ARIE , Nobuaki UMEMURA , Nobuyoshi HATTORI , Nobuto NAKANISHI , Kimio HARA , Kyoya NITTA , Makoto ISHIKAWA
IPC分类号： H01L21/768
CPC分类号： H01L29/7835 , H01L21/02057 , H01L21/743 , H01L29/4175 , H01L29/66659 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.
摘要翻译：在具有LDMOSFET的半导体器件中，源电极位于其后表面。因此，为了降低顶表面的源极接触区域与后表面的源电极之间的电阻，提供了通过P型外延从上表面延伸到P +型衬底的多晶硅埋入式插塞并用硼重掺杂。在多晶硅埋塞塞周围的单晶硅区域发生位错，引起泄漏故障。半导体器件具有延伸穿过具有不同杂质浓度的第一和第二半导体层之间的边界表面的硅基插塞。至少插头的内部是多晶区域。在多晶区域的表面中，位于与其相邻的上述边界面的两侧的部分各自被固相外延区域覆盖。

5. 发明申请

US20100327349A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100327349A1
公开(公告)日：2010-12-30
申请号：US12795863
申请日：2010-06-08
申请人： Hiroyuki ARIE , Nobuaki UMEMURA , Nobuyoshi HATTORI , Nobuto NAKANISHI , Kimio HARA , Kyoya NITTA , Makoto ISHIKAWA
发明人： Hiroyuki ARIE , Nobuaki UMEMURA , Nobuyoshi HATTORI , Nobuto NAKANISHI , Kimio HARA , Kyoya NITTA , Makoto ISHIKAWA
IPC分类号： H01L29/78 , H01L21/768
CPC分类号： H01L29/7835 , H01L21/02057 , H01L21/743 , H01L29/4175 , H01L29/66659 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.
摘要翻译：在具有LDMOSFET的半导体器件中，源电极位于其后表面。因此，为了降低顶表面的源极接触区域与后表面的源电极之间的电阻，提供了通过P型外延从上表面延伸到P +型衬底的多晶硅埋入式插塞并用硼重掺杂。在多晶硅埋塞塞周围的单晶硅区域发生位错，引起泄漏故障。半导体器件具有延伸穿过具有不同杂质浓度的第一和第二半导体层之间的边界表面的硅基插塞。至少插头的内部是多晶区域。在多晶区域的表面中，位于与其相邻的上述边界面的两侧的部分各自被固相外延区域覆盖。

6. 发明申请

US20120199905A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120199905A1
公开(公告)日：2012-08-09
申请号：US13365211
申请日：2012-02-02
申请人： Kyoya NITTA
发明人： Kyoya NITTA
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L21/28518 , H01L21/32051 , H01L21/76838 , H01L23/4824 , H01L23/485 , H01L23/5222 , H01L23/5283 , H01L29/0847 , H01L29/086 , H01L29/0865 , H01L29/0878 , H01L29/0882 , H01L29/1083 , H01L29/4175 , H01L29/41758 , H01L29/41775 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/66659 , H01L29/7816 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with improved characteristics is provided. The semiconductor device includes a LDMOS, a source plug electrically coupled to a source region of the LDMOS, a source wiring disposed over the source plug, a drain plug electrically coupled to a drain region of the LDMOS, and a drain wiring disposed over the drain plug. The structure of the source plug of the semiconductor device is devised. The semiconductor device is structured such that the drain plug is linearly disposed to extend in a direction Y, and the source plug includes a plurality of separated source plugs arranged at predetermined intervals in the direction Y. In this way, the separation of the source plug decreases an opposed area between the source plug and the drain plug, and can thus decrease the parasitic capacitance therebetween.
摘要翻译：提供了具有改进特性的半导体器件。半导体器件包括LDMOS，电耦合到LDMOS的源极区域的源极端子，设置在源极端子上的源极布线，电耦合到LDMOS的漏极区域的漏极引线以及设置在漏极上的漏极布线插头。设计了半导体器件的源极插头的结构。半导体器件被构造为使得排水塞线性地设置成沿Y方向延伸，并且源极插塞包括沿Y方向以预定间隔布置的多个分离的源极插塞。以这种方式，源插头减小了源极插塞和排水塞之间的相对面积，从而可以减小它们之间的寄生电容。

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