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1. 发明申请

US20080188043A1 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080188043A1
公开(公告)日：2008-08-07
申请号：US12005444
申请日：2007-12-26
申请人： Norio Ishitsuka , Nobuyoshi Hattori , Tomio Iwasaki
发明人： Norio Ishitsuka , Nobuyoshi Hattori , Tomio Iwasaki
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/26513 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： After a gate electrode is formed on a main surface of a semiconductor substrate, low concentration layers are formed on the main surface of the semiconductor substrate by implanting impurities therein, with using the gate electrode as a mask. Thereafter, first sidewalls and second sidewalls are formed on the both side surfaces of the gate electrode. Subsequently, nitrogen or the like is ion-implanted into the semiconductor substrate, with using the first sidewalls, the second sidewalls and the gate electrode as a mask, thereby forming a crystallization-control region (CCR) on the main surface of the semiconductor substrate. Then, after the second sidewalls are removed, high concentration layers for a source and a drain are formed on the main surface of the semiconductor substrate.
摘要翻译：在半导体衬底的主表面上形成栅电极之后，通过使用栅电极作为掩模，在半导体衬底的主表面上注入杂质，形成低浓度层。此后，在栅电极的两个侧表面上形成第一侧壁和第二侧壁。随后，使用第一侧壁，第二侧壁和栅电极作为掩模，将氮等离子注入到半导体衬底中，从而在半导体衬底的主表面上形成结晶化控制区域（CCR）。然后，在去除第二侧壁之后，在半导体衬底的主表面上形成用于源极和漏极的高浓度层。

2. 发明申请

US20050212056A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050212056A1
公开(公告)日：2005-09-29
申请号：US11135522
申请日：2005-05-24
申请人： Toshiaki Iwamatsu , Takashi Ipposhi , Hideki Naruoka , Nobuyoshi Hattori , Shigeto Maegawa , Yasuo Yamaguchi , Takuji Matsumoto
发明人： Toshiaki Iwamatsu , Takashi Ipposhi , Hideki Naruoka , Nobuyoshi Hattori , Shigeto Maegawa , Yasuo Yamaguchi , Takuji Matsumoto
IPC分类号： H01L21/76 , H01L21/762 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/12 , H01L29/45 , H01L29/786
CPC分类号： H01L21/76286 , H01L21/76264 , H01L21/76281 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/458
摘要： To provide a semiconductor device capable of preventing drawbacks from being caused by metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film (ST21), a polysilicon film (PS21) is selectively provided on the trench isolation oxide film (ST21), a silicon layer (S22) is provided on the polysilicon film (PS21), and a side wall spacer (SW2) is provided on a side surface of the polysilicon film (PS21). The polysilicon film (PS21) is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region (WR11) and an N-type well region (WR12) in an SOI layer 3 across the two well regions.
摘要翻译：提供能够防止金属污染引起的缺陷的半导体器件以及半导体器件的制造方法。区域（NR）和区域（PR）由沟槽隔离氧化膜（ST21）限定，在沟槽隔离氧化膜（ST21）上选择性地设置多晶硅膜（PS21），硅层（S 22）设置在多晶硅膜（PS21）上，在多晶硅膜（PS21）的侧面设置有侧壁隔板（SW2）。多晶硅膜（PS21）被设置在对应于SOI层3中的P型阱区域（WR 11）和N型阱区域（WR 12）的PN结部分JP的顶部的位置两个井区。

3. 发明授权

US06844242B2 Method of manufacturing SOI wafer 失效
标题翻译：制造SOI晶圆的方法
公开(公告)号：US06844242B2
公开(公告)日：2005-01-18
申请号：US10113291
申请日：2002-04-02
申请人： Hideki Naruoka , Nobuyoshi Hattori , Hidekazu Yamamoto
发明人： Hideki Naruoka , Nobuyoshi Hattori , Hidekazu Yamamoto
IPC分类号： H01L21/683 , H01L21/00 , H01L21/02 , H01L21/762 , H01L27/12 , H01L21/30 , H01L21/46
CPC分类号： H01L21/67092 , H01L21/76251 , Y10S414/138
摘要： A boat (4) has a recess (5) for supporting a laminated wafer (50). The recess (5) has a first side surface (5a), a first bottom surface (5b), a second side surface (5c), a second bottom surface (5d) and a third side surface (5e). Viewing from an upper surface of the boat (4), the second bottom surface (5d) is located in a position lower than the first bottom surface (5b). The laminated wafer (50) is mounted on the boat (4) in the state that a side surface of a first silicon wafer (1) is not in contact with the second bottom surface (5d) of the recess (5) and a side surface of a second silicon wafer (2) is in contact with the first bottom surface (5b) of the recess (5). A second main surface (2a) of the second silicon wafer (2) is in contact with the first side surface (5a) of the recess (5) and a second main surface (1a) of the first silicon wafer (1) is in contact with the third side surface (5e) of the recess (5).
摘要翻译：船（4）具有用于支撑层叠晶片（50）的凹部（5）。凹部（5）具有第一侧面（5a），第一底面（5b），第二侧面（5c），第二底面（5d）和第三侧面（5e）。从船（4）的上表面看，第二底面（5d）位于比第一底面（5b）低的位置。在第一硅晶片（1）的侧面与凹部（5）的第二底面（5d）不接触的状态下，将层叠晶片（50）安装在舟皿（4）上，第二硅晶片（2）的表面与凹部（5）的第一底表面（5b）接触。第二硅晶片（2）的第二主表面（2a）与凹部（5）的第一侧表面（5a）接触，并且第一硅晶片（1）的第二主表面（1a）处于与凹部（5）的第三侧表面（5e）接触。

4. 发明授权

US06769111B2 Computer-implemented method of process analysis 失效
标题翻译：计算机实现的过程分析方法
公开(公告)号：US06769111B2
公开(公告)日：2004-07-27
申请号：US10216844
申请日：2002-08-13
申请人： Toshiaki Mugibayashi , Nobuyoshi Hattori
发明人： Toshiaki Mugibayashi , Nobuyoshi Hattori
IPC分类号： G06F1750
CPC分类号： H01L22/20
摘要： A computer-implemented method of process analysis allows for accurate analysis of the degree of achievement of a predetermined effect exhibited by a predetermined process included in a manufacturing operation. In a step S2, a first manufacturing operation including a predetermined cleaning process is performed to form chips on wafers to be cleaned. In a step S3, a second manufacturing operation including details identical to those of the first manufacturing operation except the predetermined cleaning process is performed to form chips on wafers not to be cleaned. In a step S4, an electric tester is applied to all the chips formed on the wafers to be cleaned and the wafers not to be cleaned, to determine the quality of each chip. In a step S5, all the chips are classified into four categories according to the kind of wafer (i.e., the wafer to be cleaned or the wafer not to be cleaned) and the quality as determined of each chip. Then, in a step S6, the effect of improving the quality of a chip achieved by the predetermined cleaning process is analyzed using the classification performed in the step S5 as “chip classification data”.
摘要翻译：计算机实现的过程分析方法允许对包括在制造操作中的预定处理所呈现的预定效果的实现程度进行准确分析。在步骤S2中，执行包括预定清洁处理的第一制造操作以在待清洁的晶片上形成芯片。在步骤S3中，执行包括与除了预定清洁处理之外的第一制造操作相同的细节的第二制造操作，以在不被清洁的晶片上形成芯片。在步骤S4中，将电测试器施加到待清洁的晶片上形成的所有芯片和不被清洁的晶片，以确定每个芯片的质量。在步骤S5中，根据晶片的种类（即要清洗的晶片或不被清洗的晶片）和每个芯片所确定的质量，将所有芯片分为四类。然后，在步骤S6中，使用在步骤S5中执行的分类作为“芯片分类数据”来分析提高通过预定清洁处理实现的芯片的质量的效果。

5. 发明授权

US06372593B1 Method of manufacturing SOI substrate and semiconductor device 失效
标题翻译：制造SOI衬底和半导体器件的方法
公开(公告)号：US06372593B1
公开(公告)日：2002-04-16
申请号：US09619579
申请日：2000-07-19
申请人： Nobuyoshi Hattori , Satoshi Yamakawa , Junji Nakanishi
发明人： Nobuyoshi Hattori , Satoshi Yamakawa , Junji Nakanishi
IPC分类号： H01L21331
CPC分类号： H01L21/76256 , H01L27/10873 , H01L27/1203 , Y10S438/933
摘要： First, a silicon germanium single-crystalline layer and a silicon single-crystalline layer are formed on a main surface of a bond wafer by epitaxy. The overall surface of the bond wafer is oxidized for forming a silicon oxide layer. Then, a base wafer is bonded to the bond wafer. The bond wafer and the base wafer bonded to each other are heated for reinforcing adhesion therebetween. Then, the bond wafer is removed by plasma etching with chlorine gas while making the silicon germanium single-crystalline layer serve as a stopper. Thereafter the silicon germanium single-crystalline layer is polished by chemical mechanical polishing to have a thickness suitable for forming a device. Thus implemented is a method of manufacturing an SOI substrate by bonding capable of employing a layer having a crystal state with small irregularity for serving as a stopper having selectivity for single-crystalline silicon and effectively using the stopper as a device forming layer.
摘要翻译：首先，通过外延在接合晶片的主表面上形成硅锗单晶层和硅单晶层。接合晶片的整个表面被氧化以形成氧化硅层。然后，将基底晶片接合到接合晶片。将接合晶片和彼此接合的基底晶片加热，以加强它们之间的粘合。然后，通过用氯气等离子体蚀刻除去接合晶片，同时使硅锗单晶层用作止动器。此后，通过化学机械抛光对硅锗单晶层进行抛光，以具有适于形成器件的厚度。这样实现的是通过接合制造SOI衬底的方法，该SOI衬底可以采用具有小的不规则性的晶体状态的层作为具有对单晶硅的选择性的阻挡层，并且有效地使用该阻挡件作为器件形成层。

6. 发明授权

US06202037B1 Quality management system and recording medium 失效
标题翻译：质量管理体系和记录介质
公开(公告)号：US06202037B1
公开(公告)日：2001-03-13
申请号：US09123457
申请日：1998-07-28
申请人： Nobuyoshi Hattori , Kaoru Yamana , Tomoki Tamada
发明人： Nobuyoshi Hattori , Kaoru Yamana , Tomoki Tamada
IPC分类号： G06F1900
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A quality management system (S100) comprises a data processing unit (11), a processed-data judgment unit (12) receiving an output from the data processing unit (11), a sampling unit (13) receiving an output from the processed-data judgment unit (12), a file making unit (14) receiving an output from the sampling unit (13), a data processing unit (15) receiving an output from an observation unit (20) and a processed-data judgment unit (16) receiving an output from the data processing unit (15). The system (S100) having this constitution allows reduction in labor and time from finding of a defect to recognition of occurrence of abnormal condition and improvement in accuracy of fatality rate of the defect.
摘要翻译：质量管理系统（S100）包括数据处理单元（11），接收来自数据处理单元（11）的输出的处理数据判断单元（12），接收来自处理单元（11）的输出的采样单元（13）数据判断单元（12），接收来自采样单元（13）的输出的文件制作单元（14），接收来自观察单元（20）和处理数据判断单元（20）的输出的数据处理单元（15） 16）接收来自数据处理单元（15）的输出。具有这种结构的系统（S100）允许减少从缺陷的发现到识别异常状况的发生的劳动和时间，并且提高缺陷的死亡率的精度。

7. 发明授权

US08242605B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08242605B2
公开(公告)日：2012-08-14
申请号：US12795863
申请日：2010-06-08
申请人： Hiroyuki Arie , Nobuaki Umemura , Nobuyoshi Hattori , Nobuto Nakanishi , Kimio Hara , Kyoya Nitta , Makoto Ishikawa
发明人： Hiroyuki Arie , Nobuaki Umemura , Nobuyoshi Hattori , Nobuto Nakanishi , Kimio Hara , Kyoya Nitta , Makoto Ishikawa
IPC分类号： H01L23/48
CPC分类号： H01L29/7835 , H01L21/02057 , H01L21/743 , H01L29/4175 , H01L29/66659 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.
摘要翻译：在具有LDMOSFET的半导体器件中，源电极位于其后表面。因此，为了降低顶表面的源极接触区域与后表面的源电极之间的电阻，提供了通过P型外延从上表面延伸到P +型衬底的多晶硅埋入式插塞并用硼重掺杂。在多晶硅埋塞塞周围的单晶硅区域发生位错，引起泄漏故障。半导体器件具有延伸穿过具有不同杂质浓度的第一和第二半导体层之间的边界表面的硅基插塞。至少插头的内部是多晶区域。在多晶区域的表面中，位于与其相邻的上述边界面的两侧的部分各自被固相外延区域覆盖。

8. 发明申请

US20100327349A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100327349A1
公开(公告)日：2010-12-30
申请号：US12795863
申请日：2010-06-08
申请人： Hiroyuki ARIE , Nobuaki UMEMURA , Nobuyoshi HATTORI , Nobuto NAKANISHI , Kimio HARA , Kyoya NITTA , Makoto ISHIKAWA
发明人： Hiroyuki ARIE , Nobuaki UMEMURA , Nobuyoshi HATTORI , Nobuto NAKANISHI , Kimio HARA , Kyoya NITTA , Makoto ISHIKAWA
IPC分类号： H01L29/78 , H01L21/768
CPC分类号： H01L29/7835 , H01L21/02057 , H01L21/743 , H01L29/4175 , H01L29/66659 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.
摘要翻译：在具有LDMOSFET的半导体器件中，源电极位于其后表面。因此，为了降低顶表面的源极接触区域与后表面的源电极之间的电阻，提供了通过P型外延从上表面延伸到P +型衬底的多晶硅埋入式插塞并用硼重掺杂。在多晶硅埋塞塞周围的单晶硅区域发生位错，引起泄漏故障。半导体器件具有延伸穿过具有不同杂质浓度的第一和第二半导体层之间的边界表面的硅基插塞。至少插头的内部是多晶区域。在多晶区域的表面中，位于与其相邻的上述边界面的两侧的部分各自被固相外延区域覆盖。

9. 发明授权

US07674668B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07674668B2
公开(公告)日：2010-03-09
申请号：US12005444
申请日：2007-12-26
申请人： Norio Ishitsuka , Nobuyoshi Hattori , Tomio Iwasaki
发明人： Norio Ishitsuka , Nobuyoshi Hattori , Tomio Iwasaki
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L21/26506 , H01L21/26513 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： After a gate electrode is formed on a main surface of a semiconductor substrate, low concentration layers are formed on the main surface of the semiconductor substrate by implanting impurities therein, with using the gate electrode as a mask. Thereafter, first sidewalls and second sidewalls are formed on the both side surfaces of the gate electrode. Subsequently, nitrogen or the like is ion-implanted into the semiconductor substrate, with using the first sidewalls, the second sidewalls and the gate electrode as a mask, thereby forming a crystallization-control region (CCR) on the main surface of the semiconductor substrate. Then, after the second sidewalls are removed, high concentration layers for a source and a drain are formed on the main surface of the semiconductor substrate.
摘要翻译：在半导体衬底的主表面上形成栅电极之后，通过使用栅电极作为掩模，在半导体衬底的主表面上注入杂质，形成低浓度层。此后，在栅电极的两个侧表面上形成第一侧壁和第二侧壁。随后，使用第一侧壁，第二侧壁和栅电极作为掩模，将氮等离子注入到半导体衬底中，从而在半导体衬底的主表面上形成结晶化控制区域（CCR）。然后，在去除第二侧壁之后，在半导体衬底的主表面上形成用于源极和漏极的高浓度层。

10. 发明授权

US06473665B2 Defect analysis method and process control method 失效
公开(公告)号：US06473665B2
公开(公告)日：2002-10-29
申请号：US09920818
申请日：2001-08-03
申请人： Toshiaki Mugibayashi , Nobuyoshi Hattori
发明人： Toshiaki Mugibayashi , Nobuyoshi Hattori
IPC分类号： G06F1900
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A defect analysis method makes it possible to quantitative grasp the influence of the number of new defects of a single process on the yield of a device. After the presence or absence of a new defect due to a specified process in each chip is judged, and defectiveness or non-defectiveness of the chip is judged by an electric tester, a plurality of chips on a wafer are classified into four groups: {circle around (1)} non-defective chip with no new defect; {circle around (2)} defective chip with no new defect; {circle around (3)} non-defective chip with new defect; and {circle around (4)} defective chip with new defect, to obtained the number of new defective chips considered to be caused only by the new defect of the specified process; a critical ratio of the new defect of the specified process, at which a chip is considered to become defective; and the number of process defective chips considered to be caused by the specified process.

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