专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050289269A1 Slave device, master device and stacked device 有权
标题翻译：从设备，主设备和堆叠设备
公开(公告)号：US20050289269A1
公开(公告)日：2005-12-29
申请号：US11149171
申请日：2005-06-10
申请人： Takeshi Nakayama , Eiji Takahashi , Yoshiyuki Saito , Yukihiro Ishimaru , Hideki Iwaki
发明人： Takeshi Nakayama , Eiji Takahashi , Yoshiyuki Saito , Yukihiro Ishimaru , Hideki Iwaki
IPC分类号： G06F13/00 , G06F13/40 , G06F13/42
CPC分类号： G06F13/409 , G06F13/4226 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/16145 , H01L2924/00014 , H01L2224/05599 , H01L2224/05099
摘要： A stacked device is disclosed which is easily manufactured while identifying a plurality of devices that are stacked in the stacked device. The stacked device includes a stack of a plurality of slave devices and a master device having identical terminal arrangements. Here, the master device includes command transmission unit configured to input an identification command to a terminal of an adjacent slave device. Furthermore, the slave device includes a through-wire for interconnecting at least one terminal of that same device and an adjacent slave device; command reception unit configured to receive the identification command; and ID (identifier) setting unit configured to set the ID of that same device based on the identification command; the positions of the terminals that are interconnected with the adjacent slave devices differing in each slave device, so that, in each slave device, the slave device command reception unit receive an identification command having a modified value as a result of transiting through-wires that are connected at differing positions in each slave device.
摘要翻译：公开了一种容易制造的堆叠式装置，同时识别堆叠在堆叠装置中的多个装置。堆叠式装置包括多个从装置的堆叠和具有相同端子装置的主装置。这里，主设备包括命令传输单元，其被配置为向相邻从设备的终端输入识别命令。此外，从设备包括用于互连同一设备的至少一个终端和相邻从设备的通线; 命令接收单元，被配置为接收所述识别命令; ID（识别符）设定部，其基于所述识别命令来设定同一设备的ID; 与相邻从设备互连的终端的位置在每个从设备中不同，从而在每个从设备中，从设备命令接收单元接收作为转接通线的结果具有修改值的标识命令，被连接在每个从设备中的不同位置。

2. 发明授权

US07346051B2 Slave device, master device and stacked device 有权
标题翻译：从设备，主设备和堆叠设备
公开(公告)号：US07346051B2
公开(公告)日：2008-03-18
申请号：US11149171
申请日：2005-06-10
申请人： Takeshi Nakayama , Eiji Takahashi , Yoshiyuki Saito , Yukihiro Ishimaru , Hideki Iwaki
发明人： Takeshi Nakayama , Eiji Takahashi , Yoshiyuki Saito , Yukihiro Ishimaru , Hideki Iwaki
IPC分类号： H04Q11/00 , H04L12/50 , H04L12/28 , H04L12/56 , H02J13/00 , G06F3/00 , G06F15/76
CPC分类号： G06F13/409 , G06F13/4226 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/16145 , H01L2924/00014 , H01L2224/05599 , H01L2224/05099
摘要： A stacked device is disclosed which is easily manufactured while identifying a plurality of devices that are stacked in the stacked device. The stacked device includes a stack of a plurality of slave devices and a master device having identical terminal arrangements. Here, the master device includes command transmission unit configured to input an identification command to a terminal of an adjacent slave device. Furthermore, the slave device includes a through-wire for interconnecting at least one terminal of that same device and an adjacent slave device; command reception unit configured to receive the identification command; and ID (identifier) setting unit configured to set the ID of that same device based on the identification command; the positions of the terminals that are interconnected with the adjacent slave devices differing in each slave device, so that, in each slave device, the slave device command reception unit receive an identification command having a modified value as a result of transiting through-wires that are connected at differing positions in each slave device.
摘要翻译：公开了一种容易制造的堆叠式装置，同时识别堆叠在堆叠装置中的多个装置。堆叠式装置包括多个从装置的堆叠和具有相同端子装置的主装置。这里，主设备包括命令传输单元，其被配置为向相邻从设备的终端输入识别命令。此外，从设备包括用于互连同一设备的至少一个终端和相邻从设备的通线; 命令接收单元，被配置为接收所述识别命令; ID（识别符）设定部，其基于所述识别命令来设定同一设备的ID; 与相邻从设备互连的终端的位置在每个从设备中不同，从而在每个从设备中，从设备命令接收单元接收作为转接通线的结果具有修改值的标识命令，被连接在每个从设备中的不同位置。

3. 发明授权

US07788076B2 Interference analysis method, interference analysis device, interference analysis program and recording medium with interference analysis program recorded thereon 有权
标题翻译：干扰分析方法，干扰分析装置，干扰分析程序和记录有干扰分析程序的记录介质
公开(公告)号：US07788076B2
公开(公告)日：2010-08-31
申请号：US11076212
申请日：2005-03-08
申请人： Hideki Iwaki , Tetsuyoshi Ogura , Naoki Komatsu , Takeshi Nakayama , Tomohiro Kinoshita
发明人： Hideki Iwaki , Tetsuyoshi Ogura , Naoki Komatsu , Takeshi Nakayama , Tomohiro Kinoshita
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： An interference analysis device can be provided, which analyzes interference between wirings of a circuit board with reduced load and for a short time period. The interference analysis device according to the present invention includes: a design data input part for inputting design data of the circuit board; a noise characteristics setting part that sets data representing electrical characteristics of noise for a wiring of the circuit board; a limit value setting part that sets an allowable limit value of noise received by a wiring; a selection part that selects a wiring group to be analyzed based on the noise characteristics data and the allowable limit value; an interference analysis part that calculates, concerning the selected wiring group, an amount of interference from a wiring giving the interference to a wiring receiving the interference; and a received noise level calculation part that calculates a noise level that the wiring receiving the interference will receive.
摘要翻译：可以提供干扰分析装置，其分析电路板的布线之间的负载和短时间内的干扰。根据本发明的干扰分析装置包括：设计数据输入部分，用于输入电路板的设计数据; 噪声特性设定部，其设定表示所述电路基板的布线的噪声的电特性的数据; 极限值设定部，其设定由布线接收到的噪声的允许限制值; 选择部，其基于所述噪声特性数据和所述容许极限值来选择要分析的布线组; 干扰分析部，其对与所述接线组相关的干扰分析部，计算与所述干扰对应的布线的干扰量的干扰量; 以及接收噪声电平计算部，其计算接收到干扰的接线的噪声电平。

4. 发明申请

US20050197817A1 Interference analysis method, interference analysis device, interference analysis program and recording medium with interference analysis program recorded thereon 有权
标题翻译：干扰分析方法，干扰分析装置，干扰分析程序和记录有干扰分析程序的记录介质
公开(公告)号：US20050197817A1
公开(公告)日：2005-09-08
申请号：US11076212
申请日：2005-03-08
申请人： Hideki Iwaki , Tetsuyoshi Ogura , Naoki Komatsu , Takeshi Nakayama , Tomohiro Kinoshita
发明人： Hideki Iwaki , Tetsuyoshi Ogura , Naoki Komatsu , Takeshi Nakayama , Tomohiro Kinoshita
IPC分类号： G01R31/28 , G06F17/50 , H01L21/82
CPC分类号： G06F17/5036
摘要： An interference analysis device can be provided, which analyzes interference between wirings of a circuit board with reduced load and for a short time period. The interference analysis device according to the present invention includes: a design data input part for inputting design data of the circuit board; a noise characteristics setting part that sets data representing electrical characteristics of noise for a wiring of the circuit board; a limit value setting part that sets an allowable limit value of noise received by a wiring; a selection part that selects a wiring group to be analyzed based on the noise characteristics data and the allowable limit value; an interference analysis part that calculates, concerning the selected wiring group, an amount of interference from a wiring giving the interference to a wiring receiving the interference; and a received noise level calculation part that calculates a noise level that the wiring receiving the interference will receive.
摘要翻译：可以提供干扰分析装置，其分析电路板的布线之间的负载和短时间内的干扰。根据本发明的干扰分析装置包括：设计数据输入部分，用于输入电路板的设计数据; 噪声特性设定部，其设定表示所述电路基板的布线的噪声的电特性的数据; 极限值设定部，其设定由布线接收到的噪声的允许限制值; 选择部，其基于所述噪声特性数据和所述容许极限值来选择要分析的布线组; 干扰分析部，其对与所述接线组相关的干扰分析部，计算与所述干扰对应的布线的干扰量的干扰量; 以及接收噪声电平计算部，其计算接收到干扰的接线的噪声电平。

5. 发明授权

US07061100B2 Semiconductor built-in millimeter-wave band module 有权
标题翻译：半导体内置毫米波段模块
公开(公告)号：US07061100B2
公开(公告)日：2006-06-13
申请号：US10405524
申请日：2003-04-02
申请人： Hideki Iwaki , Yutaka Taguchi , Tetsuyosi Ogura , Yasuhiro Sugaya , Toshiyuki Asahi , Tousaku Nishiyama , Yoshinobu Idogawa
发明人： Hideki Iwaki , Yutaka Taguchi , Tetsuyosi Ogura , Yasuhiro Sugaya , Toshiyuki Asahi , Tousaku Nishiyama , Yoshinobu Idogawa
IPC分类号： H01L23/10 , H01L23/34
CPC分类号： H01L23/66 , H01L21/481 , H01L21/56 , H01L23/552 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/162 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01079 , H01L2924/01322 , H01L2924/12042 , H01L2924/1305 , H01L2924/14 , H01L2924/1423 , H01L2924/1532 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/20752
摘要： A semiconductor built-in millimeter-wave band module includes: an insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin; a high thermal conductivity substrate made of a dielectric material having thermal conductivity higher than the insulating substrate and laminated on one surface of the insulating substrate; a plurality of wiring patterns formed on the high thermal conductivity substrate and the insulating substrate; a semiconductor device operating at millimeter-wave band, which is arranged inside of the insulating substrate, is packaged on the high thermal conductivity substrate in a face-up manner, and is connected electrically with the wiring patterns; and a distributed constant circuit element and an active element provided on the semiconductor device. In this module, a void is provided inside of the insulating substrate and in the vicinity of a surface of the distributed constant circuit element and the active element. With this configuration, heat from the semiconductor device operating at a millimeter-wave band can be dissipated effectively and the semiconductor and other circuit components can be packaged with high density.
摘要翻译：半导体内置毫米波段模块包括：绝缘基板，由含有无机填料和热固性树脂的混合物制成; 高导热性衬底，其由具有高于绝缘衬底的导热率的电介质材料制成并且层压在绝缘衬底的一个表面上; 形成在高导热性基板和绝缘基板上的多个布线图案; 布置在绝缘基板内部的以毫米波段工作的半导体器件以面朝上的方式封装在高导热性基板上，并与布线图形电连接; 以及设置在半导体器件上的分布常数电路元件和有源元件。在该模块中，在绝缘基板内部和分布常数电路元件和有源元件的表面附近设置有空隙。利用这种结构，可以有效地消耗来自在毫米波段工作的半导体器件的热量，并可以高密度地封装半导体和其它电路部件。

6. 发明授权

US06392164B1 Multi-level circuit substrate, method for manufacturing same and method for adjusting a characteristic impedance therefor 有权
标题翻译：多电平电路基板及其制造方法以及调整其特性阻抗的方法
公开(公告)号：US06392164B1
公开(公告)日：2002-05-21
申请号：US09417662
申请日：1999-10-14
申请人： Hideki Iwaki , Yutaka Taguchi , Tetsuyoshi Ogura
发明人： Hideki Iwaki , Yutaka Taguchi , Tetsuyoshi Ogura
IPC分类号： H05K111
CPC分类号： H05K1/0251 , H01L23/66 , H01L2223/6616 , H01L2924/0002 , H01L2924/3011 , H05K1/024 , H05K1/0298 , H05K1/116 , H05K2201/0715 , H05K2201/09454 , H05K2201/096 , H05K2201/09718 , H05K2201/09781 , H05K2201/09881 , H01L2924/00
摘要： An insulator is provided between interconnect layers oppositely placed. The interconnect layers are connected between by connection members provided through the insulator. The connection members at one and the other ends are connected between in their center positions. A shield layer is provided spaced from the intermediate connection layer generally on a same plane as the intermediate connection layer. The interconnect layers where considered generally as a circular cylinder have a diameter m, and the intermediate connection layer where considered generally as circular has a diameter r, r
摘要翻译：在相互布置的互连层之间设置绝缘体。互连层通过通过绝缘体提供的连接构件连接在一起。连接构件在一端和另一端连接在它们的中心位置之间。屏蔽层设置成与中间连接层间隔开，通常在与中间连接层相同的平面上。通常被认为是圆柱体的互连层具有直径m，并且被认为通常为圆形的中间连接层具有直径r，r

7. 发明授权

US6154940A Electronic part and a method of production thereof 失效
标题翻译：电子部件及其制造方法
公开(公告)号：US6154940A
公开(公告)日：2000-12-05
申请号：US90489
申请日：1998-06-03
申请人： Keiji Onishi , Hideki Iwaki , Shun-ichi Seki , Yutaka Taguchi , Tsukasa Shiraishi , Yoshihiro Bessho , Osamu Kawasaki , Kazuo Eda
发明人： Keiji Onishi , Hideki Iwaki , Shun-ichi Seki , Yutaka Taguchi , Tsukasa Shiraishi , Yoshihiro Bessho , Osamu Kawasaki , Kazuo Eda
IPC分类号： H03H3/08 , H03H9/10 , H04R17/00
CPC分类号： H03H9/0509 , H03H3/08 , H03H9/0585 , H03H9/059 , H03H9/1042 , H03H9/1071 , H03H9/1085 , H03H9/1092 , H01L2224/1134 , H01L2224/131 , H01L2224/13124 , H01L2224/13144 , H01L2224/45144 , H01L2924/00013 , H01L2924/09701 , H01L2924/16152 , Y10T29/42 , Y10T29/4913 , Y10T29/49146
摘要： The present invention relates to an electronic part used for mobile communications apparatuses and the like, and more particularly to an electronic part, such as an acoustic surface-wave device, a piezoelectric ceramic device or the like, which requires an oscillation space near the surface of the functional device chip thereof, and a method of production thereof. With this method, a space retainer for forming a sealed space at the functional portion of the chip can be hermetically sealed and have high moisture resistance, and the process of forming the space retainer can be carried out easily.The electronic part of the present invention comprises a functional device chip, a space retainer for forming a sealed space at the functional portion of the chip, a circuit substrate to which the chip is secured, electrode interconnection portions for establishing electric connection between the chip and the circuit substrate, and a sealing resin for covering and sealing at least the space retainer, wherein the space retainer comprises a support layer made of a synthetic resin film, provided with an opening enclosing the functional portion and joined onto the main surface, and a cover formed and joined onto the support layer so as to cover the functional portion and form a sealed space between the cover and the functional portion.
摘要翻译：本发明涉及用于移动通信设备等的电子部件，更具体地涉及需要在表面附近的振荡空间的诸如声表面波器件，压电陶瓷器件等的电子部件的功能元件芯片及其制造方法。利用这种方法，在芯片的功能部分处形成密封空间的空间保持器可以被气密地密封并且具有高的耐湿性，并且可以容易地进行形成空间保持器的工艺。本发明的电子部件包括功能元件芯片，用于在芯片的功能部分形成密封空间的空间保持器，固定有芯片的电路基板，用于建立芯片与芯片之间的电连接的电极互连部分电路基板和用于至少覆盖和密封空间保持器的密封树脂，其中，所述空间保持器包括由合成树脂膜制成的支撑层，所述支撑层设置有封闭所述功能部分并且接合到所述主表面上的开口，以及盖形成并接合到支撑层上以覆盖功能部分并在盖和功能部分之间形成密封空间。

8. 发明申请

US20090174476A1 NOISE REDUCTION CIRCUIT FOR CANCELING LEAKAGE SIGNAL 有权
标题翻译：消除噪声信号的噪声减少电路
公开(公告)号：US20090174476A1
公开(公告)日：2009-07-09
申请号：US12295480
申请日：2007-03-28
申请人： Naoki Komatsu , Hideki Iwaki , Toru Yamada
发明人： Naoki Komatsu , Hideki Iwaki , Toru Yamada
IPC分类号： H03F1/30
CPC分类号： H03F1/26 , H01L2223/6627 , H01L2924/19032 , H01L2924/19051 , H03F1/30 , H03F3/19 , H03F3/245 , H05K1/0228 , H05K1/0239 , H05K2201/10166
摘要： In a noise reduction circuit, a transistor circuit amplifies an input signal and outputs an output signal with supply of power from the DC voltage source via a power supply line circuit. The canceling signal adding circuit acquires and attenuates a part of the output signal, to generate a canceling signal having a phase substantially opposite to a phase of a leakage signal leaking to the power supply line circuit, and having an amplitude substantially the same as an amplitude of the leakage signal.
摘要翻译：在降噪电路中，晶体管电路对输入信号进行放大，并通过电源线电路输出来自直流电压源的电力的输出信号。取消信号添加电路获取并衰减输出信号的一部分，以产生具有与泄漏到电源线电路的泄漏信号的相位基本相反的相位并具有与振幅基本相同的振幅的消除信号的泄漏信号。

9. 发明申请

US20090019403A1 CIRCUIT WIRING INTERFERENCE ANALYSIS DEVICE, INTERFERENCE ANALYSIS PROGRAM, DATABASE USED IN INTERFERENCE ANALYSIS DEVICE, AND ASYMMETRICALLY CONNECTED LINE MODEL 有权
标题翻译：电路干扰分析设备，干扰分析程序，干扰分析设备中使用的数据库和非对称连接线路模型
公开(公告)号：US20090019403A1
公开(公告)日：2009-01-15
申请号：US11911609
申请日：2006-04-14
申请人： Hideki Iwaki , Naoki Komatsu , Tetsuyoshi Ogura , Toru Yamada
发明人： Hideki Iwaki , Naoki Komatsu , Tetsuyoshi Ogura , Toru Yamada
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H05K1/0216 , H05K3/0005
摘要： An interference analysis device that analyzes interference includes an input unit 2 that inputs design data, a selection unit 3 that selects an analysis region, a division unit 5 that divides a wire into segments, a calculation unit 6 that calculates a circuit matrix regarding a coupled line, and an analysis unit 7 that obtains a degree of electromagnetic interference, wherein the calculation unit 6 calculates a circuit matrix of the coupled line, using a parameter set obtained by adding an asymmetry parameter to RLGC parameters of a transmission line in the coupled line. Thus, a method for analyzing an interference of circuit wiring can be provided, which is capable of shortening a processing time substantially while maintaining high precision.
摘要翻译：分析干扰的干扰分析装置包括：输入设计数据的输入单元2，选择分析区域的选择单元3;将线分割成分段的分割单元5;计算单元6，线路和获得电磁干扰程度的分析单元7，其中计算单元6使用通过将耦合线路中的传输线路的RLGC参数相加不对称参数获得的参数集来计算耦合线路的电路矩阵。因此，可以提供用于分析电路布线的干扰的方法，其能够在保持高精度的同时基本上缩短处理时间。

10. 发明申请

US20060070015A1 Circuit board design system, design data analysis method and recording medium with analysis program recorded thereon 有权
标题翻译：电路板设计系统，设计数据分析方法和记录有分析程序的记录介质
公开(公告)号：US20060070015A1
公开(公告)日：2006-03-30
申请号：US11238166
申请日：2005-09-28
申请人： Hideki Iwaki , Yukinobu Furukawa
发明人： Hideki Iwaki , Yukinobu Furukawa
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5036
摘要： The design system, which is equipped with capability to analyze circuit board design data, comprises a storing section for recording design data, including structure data, circuit data, and element data; a selection section for selecting a pair of circuit elements subject to interference analysis among circuit elements placed on a circuit board, represented by the structure data; a substitution section for acquiring element data concerning circuit elements selected by the selection section from the design data and, based on element data, generating equivalent circuit data representing electromagnetic coupling within the pair of circuit elements with the help of an equivalent circuit; and an analysis section for calculating an amount of interference within the pair of circuit elements by analyzing data produced by combining the equivalent circuit data with the circuit data.
摘要翻译：具有分析电路板设计数据能力的设计系统包括用于记录设计数据的存储部分，包括结构数据，电路数据和元件数据; 选择部分，用于选择由结构数据表示的放置在电路板上的电路元件之间进行干扰分析的一对电路元件; 替代部分，用于从设计数据中获取关于由选择部分选择的电路元件的元件数据，并且基于元件数据，借助于等效电路产生表示该对电路元件内的电磁耦合的等效电路数据; 以及分析部分，用于通过分析通过组合等效电路数据与电路数据产生的数据来计算该对电路元件内的干扰量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式