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1. 发明授权

US4744063A Static memory utilizing transition detectors to reduce power consumption 失效
标题翻译：静态存储器利用转换检测器来降低功耗
公开(公告)号：US4744063A
公开(公告)日：1988-05-10
申请号：US613614
申请日：1984-05-24
申请人： Takayuki Ohtani , Takayasu Sakurai , Mitsuo Isobe , Tetsuya Iizuka
发明人： Takayuki Ohtani , Takayasu Sakurai , Mitsuo Isobe , Tetsuya Iizuka
IPC分类号： G11C11/41 , G11C8/18 , G11C11/418 , G11C16/06 , G11C8/00
CPC分类号： G11C11/418 , G11C8/18
摘要： A static memory has an address transition detector, an input data transition detector and a pulse signal generator. When a detector detects that an input address or input data has changed, the pulse signal generator produces a pulse signal having a width longer than the shorter of the data-reading or data-writing cycle. This pulse signal controls the period of time during which a penetrating DC current flows between two power sources via some of the components of the memory.
摘要翻译：静态存储器具有地址转换检测器，输入数据转换检测器和脉冲信号发生器。当检测器检测到输入地址或输入数据已经改变时，脉冲信号发生器产生具有比数据读取或数据写入周期更短的宽度的脉冲信号。该脉冲信号控制穿透DC电流通过存储器的一些部件在两个电源之间流动的时间段。

2. 发明授权

US4587638A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4587638A
公开(公告)日：1986-05-06
申请号：US630115
申请日：1984-07-12
申请人： Mitsuo Isobe , Takayasu Sakurai , Kazuhiro Sawada , Tetsuya Iizuka , Takayuki Ohtani , Akira Aono
发明人： Mitsuo Isobe , Takayasu Sakurai , Kazuhiro Sawada , Tetsuya Iizuka , Takayuki Ohtani , Akira Aono
IPC分类号： G11C29/00 , G11C7/02
CPC分类号： G11C29/84 , G11C29/832
摘要： In the semiconductor memory device according to the present invention, when there is a defective portion in the memory cells, those memory cells are replaced by redundant memory cells. When defective portions are discovered in the memory cells, the fuse elements corresponding to the memory cells having the defective portions are cut off. Voltages of the select lines connected to the memory cells having the defective portions are held at an L level by the resistors. Due to this, the memory cells having the defective portions are not selected.
摘要翻译：在根据本发明的半导体存储器件中，当存储单元中存在缺陷部分时，这些存储单元被冗余存储单元替换。当在存储单元中发现有缺陷的部分时，与具有缺陷部分的存储单元相对应的熔丝元件被切断。连接到具有缺陷部分的存储单元的选择线的电压由电阻器保持在L电平。因此，不选择具有缺陷部分的存储单元。

3. 发明授权

US4813022A Static memory with pull-up circuit for pulling-up a potential on a bit line 失效
标题翻译：具有上拉电路的静态存储器，用于提升位线上的电位
公开(公告)号：US4813022A
公开(公告)日：1989-03-14
申请号：US136769
申请日：1987-12-22
申请人： Masataka Matsui , Tetsuya Iizuka , Jun-ichi Tsujimoto , Takayuki Ohtani , Mitsuo Isobe
发明人： Masataka Matsui , Tetsuya Iizuka , Jun-ichi Tsujimoto , Takayuki Ohtani , Mitsuo Isobe
IPC分类号： G11C11/417 , G11C7/12 , G11C11/41 , G11C11/413 , G11C11/419 , G11C7/00 , G11C11/34
CPC分类号： G11C7/12 , G11C11/419
摘要： The threshold voltage of bit line percharge/equalize MOS transistors is smaller than that of normally ON type bit line pull-up transistors. With this feature, there is no current flows through a bit line from power source V.sub.DD during a read-out operation. The voltage difference between a pair of bit lines can be increased at high speed, thereby increasing the read-out speed.
摘要翻译：位线的每个充电/均衡MOS晶体管的阈值电压小于通常的ON型位线上拉晶体管的阈值电压。通过这一功能，在读出操作期间，没有电流从电源VDD流过位线。可以高速地增加一对位线之间的电压差，从而增加读出速度。

4. 发明授权

US4857763A MOS semiconductor integrated circuit in which the production of hot carriers near the drain of a short n channel conductivity type MOS transistor is decreased 失效
标题翻译： MOS半导体集成电路，其中在短沟道导电型MOS晶体管的漏极附近产生热载流子减少
公开(公告)号：US4857763A
公开(公告)日：1989-08-15
申请号：US140493
申请日：1988-01-06
申请人： Takayasu Sakurai , Tetsuya Iizuka
发明人： Takayasu Sakurai , Tetsuya Iizuka
IPC分类号： H01L27/092 , G11C5/14 , G11C7/10 , G11C7/22 , G11C8/08 , G11C11/407 , G11C11/409 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/00 , H03K17/687 , H03K19/00 , H03K19/003 , H03K19/094 , H03K19/0944 , H03K19/0948 , H03K19/0952
CPC分类号： G11C7/1057 , G11C5/14 , G11C7/1051 , G11C7/1078 , G11C7/1084 , G11C7/22 , G11C8/08 , H03K19/0013 , H03K19/00315 , H03K19/00361 , H03K19/0948
摘要： Semiconductor integrated circuit of the present invention comprises a signal output terminal, a load circuit connected to the signal output terminal, a transistor circuit which is constituted by at least one first channel MOS transistor and has an output terminal connected to the signal output terminal and an input terminal connected to a signal input terminal, and a first channel enhancement type MOS transistor that is inserted between the transistor circuit's output terminal and the signal output terminal and is made normally in an on state. It is an object of the present invention to provide a highly reliable semiconductor integrated circuit in which no deterioration of characteristics due to hot carriers occurs even when the circuit is constituted using short channel MOS transistors with an effective channel length of about 1 micron or less.

5. 发明授权

US4683382A Power-saving voltage supply 失效
标题翻译：省电电源
公开(公告)号：US4683382A
公开(公告)日：1987-07-28
申请号：US667417
申请日：1984-11-01
申请人： Takayasu Sakurai , Tetsuya Iizuka
发明人： Takayasu Sakurai , Tetsuya Iizuka
IPC分类号： G05F1/46 , G05F1/56 , G11C5/14 , G11C11/407 , H03K3/01 , G06G7/10 , H03K5/153
CPC分类号： G11C5/147
摘要： In a semiconductor device according to the invention, first and second voltage dropping circuits, for generating voltages respectively having smaller values than that of an external power supply voltage, are provided. The first voltage dropping circuit, which consumes relatively less power, is always in the operative mode, and the second voltage dropping circuit, which consumes more power than that of the first voltage dropping circuit, is operated during an interval other than a standby interval. The voltages generated by the first and second voltage dropping circuits are supplied to an internal power supply line in parallel with each other.
摘要翻译：在根据本发明的半导体器件中，提供了用于产生分别具有比外部电源电压小的值的电压的第一和第二降压电路。消耗相对较少功率的第一降压电路总是处于操作模式，并且在除了待机间隔之外的间隔中操作消耗比第一降压电路多的功率的第二降压电路。由第一和第二降压电路产生的电压彼此平行地供给到内部电源线。

6. 发明授权

US4677592A Dynamic RAM 失效
标题翻译：动态RAM
公开(公告)号：US4677592A
公开(公告)日：1987-06-30
申请号：US739171
申请日：1985-05-30
申请人： Takayasu Sakurai , Tetsuya Iizuka
发明人： Takayasu Sakurai , Tetsuya Iizuka
IPC分类号： G11C11/403 , G11C11/406 , G11C7/00
CPC分类号： G11C11/40615 , G11C11/406
摘要： In a dynamic RAM, the refreshing operation is performed during one cycle of the read or write operation. A switch circuit selects either a row address signal output from address input circuit or a refresh row address signal output from a refresh circuit. By controlling the switch circuit by a switch selector, the refresh is performed during the operation delay time of the address input circuit or an input/output circuit for inputting and outputting data.
摘要翻译：在动态RAM中，刷新操作在读取或写入操作的一个周期期间执行。开关电路选择从地址输入电路输出的行地址信号或从刷新电路输出的刷新行地址信号。通过开关选择器控制开关电路，在地址输入电路的操作延迟时间或输入和输出数据的输入/输出电路中进行刷新。

7. 发明授权

US4740713A MOS semiconductor integrated circuit in which the production of hot carriers near the drain of a short n channel conductivity type MOS transistor is decreased 失效
标题翻译： MOS半导体集成电路，其中在短沟道导电型MOS晶体管的漏极附近产生热载流子减少
公开(公告)号：US4740713A
公开(公告)日：1988-04-26
申请号：US815026
申请日：1985-12-30
申请人： Takayasu Sakurai , Tetsuya Iizuka
发明人： Takayasu Sakurai , Tetsuya Iizuka
IPC分类号： H01L27/092 , G11C5/14 , G11C7/10 , G11C7/22 , G11C8/08 , G11C11/407 , G11C11/409 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/00 , H03K17/687 , H03K19/00 , H03K19/003 , H03K19/094 , H03K19/0944 , H03K19/0948 , H03K19/0952 , H03K17/10 , H03K17/16
CPC分类号： G11C7/1057 , G11C5/14 , G11C7/1051 , G11C7/1078 , G11C7/1084 , G11C7/22 , G11C8/08 , H03K19/0013 , H03K19/00315 , H03K19/00361 , H03K19/0948
摘要： Semiconductor integrated circuit of the present invention comprises a signal output terminal, a load circuit connected to the signal output terminal, a transistor circuit which is constituted by at least one first channel MOS transistor and has an output terminal connected to the signal output terminal and an input terminal connected to a signal input terminal, and a first channel enhancement type MOS transistor that is inserted between the transistor circuit's output terminal and the signal output terminal and is made normally in an on state. It is an object of the present invention to provide a highly reliable semiconductor integrated circuit in which no deterioration of characteristics due to hot carriers occurs even when the circuit is constituted using short channel MOS transistors with an effective channel length of about 1 micron or less.
摘要翻译：本发明的半导体集成电路包括信号输出端子，连接到信号输出端子的负载电路，由至少一个第一沟道MOS晶体管构成并具有连接到信号输出端子的输出端子的晶体管电路，以及连接到信号输入端子的输入端子和插入在晶体管电路的输出端子和信号输出端子之间的第一沟道增强型MOS晶体管，并且正常地处于导通状态。本发明的目的是提供一种高可靠性的半导体集成电路，其中即使使用具有约1微米或更小的有效沟道长度的短沟道MOS晶体管构成电路，也不会发生由于热载流子引起的特性劣化。

8. 发明授权

US4682306A Self-refresh control circuit for dynamic semiconductor memory device 失效
标题翻译：动态半导体存储器件的自刷新控制电路
公开(公告)号：US4682306A
公开(公告)日：1987-07-21
申请号：US767602
申请日：1985-08-20
申请人： Takayasu Sakurai , Tetsuya Iizuka
发明人： Takayasu Sakurai , Tetsuya Iizuka
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A self-refresh control circuit for a dynamic memory device having memory cells and a self-refresh circuit on a single chip. The circuit includes a leak current monitor circuit representing the leakage of a memory cell and an inverter circuit for detecting the leakage of the monitor circuit so as to control the refresh operation automatically.
摘要翻译：一种用于在单个芯片上具有存储单元和自刷新电路的动态存储器件的自刷新控制电路。电路包括表示存储单元泄漏的泄漏电流监视电路和用于检测监视电路的泄漏的逆变器电路，以便自动控制刷新操作。

9. 发明授权

US4618945A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4618945A
公开(公告)日：1986-10-21
申请号：US517419
申请日：1983-07-26
申请人： Takayasu Sakurai , Tetsuya Iizuka
发明人： Takayasu Sakurai , Tetsuya Iizuka
IPC分类号： G11C11/4096 , G11C7/00
CPC分类号： G11C11/4096
摘要： A semiconductor memory device has a plurality of memory cells arranged in a two-dimensional matrix array, word lines for connecting memory cells of each row to a row decoder, and bit lines for connecting memory cells of each column to a column decoder. The word lines include first word lines each of which is connected to several memory cells in each column section of one row. The word lines also include a second word line connected to the first word lines of each row through corresponding switches. In response to a column address signal, one of the switches of each row is turned on, so that one of the first word lines is connected to the corresponding second word line.
摘要翻译：半导体存储器件具有布置在二维矩阵阵列中的多个存储器单元，用于将每行的存储单元连接到行解码器的字线和用于将每列的存储单元连接到列解码器的位线。字线包括第一字线，每条字线连接到一行的每个列部分中的多个存储器单元。字线还包括通过相应的开关连接到每行的第一字线的第二字线。响应于列地址信号，每行的开关之一被接通，使得第一字线中的一个连接到对应的第二字线。

10. 发明授权

US4594519A Low power consumption, high speed CMOS signal input circuit 失效
标题翻译：低功耗，高速CMOS信号输入电路
公开(公告)号：US4594519A
公开(公告)日：1986-06-10
申请号：US534691
申请日：1983-09-22
申请人： Takayuki Ohtani , Tetsuya Iizuka
发明人： Takayuki Ohtani , Tetsuya Iizuka
IPC分类号： H03K19/20 , G11C8/00 , H03K19/00 , H03K19/094 , H03K19/003
CPC分类号： H03K19/09425 , H03K19/09429
摘要： A signal input circuit particularly well suited for use in MOS integrated circuits. The signal input circuit includes: and input gate circuit for receiving an input signal and an enable control signal, and for generating an output signal equal to the input signal when the enable control signal is in an "enable" state, and for providing a high output impedance when the enable control signal is in a "disable" state; and a holding circuit coupled to an output of the input gate circuit and to receiving the enable control signal, for holding, during the disable state, the output state of the input gate circuit immediately before the enable control signal changes to a disable state, the output impedance being high when the enable control signal is in an enable state.
摘要翻译：特别适用于MOS集成电路的信号输入电路。信号输入电路包括：输入门电路，用于接收输入信号和使能控制信号，并且在使能控制信号处于“使能”状态时，产生等于输入信号的输出信号，并提供高电平当使能控制信号处于“禁止”状态时的输出阻抗; 以及保持电路，其耦合到所述输入门电路的输出并且接收所述使能控制信号，以在所述禁止状态期间保持所述输入门电路的输出状态，所述输入门电路在所述使能控制信号变为禁用状态之前，当使能控制信号处于使能状态时，输出阻抗为高。

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