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1. 发明授权

US06060946A Semiconductor device having improved immunity to power supply voltage fluctuations 失效
标题翻译：具有提高的对电源电压波动的抗扰性的半导体器件
公开(公告)号：US06060946A
公开(公告)日：2000-05-09
申请号：US25662
申请日：1998-02-18
申请人： Takayuki Harima , Kenichi Nakamura , Masami Masuda
发明人： Takayuki Harima , Kenichi Nakamura , Masami Masuda
IPC分类号： H01L21/822 , G11C11/401 , G11C11/409 , H01L21/82 , H01L27/04 , H03K19/003 , H03K5/00
CPC分类号： H03K19/00361
摘要： An input buffer circuit is connected to a first power supply voltage pad for applying a first power supply voltage, and a first ground line. An internal circuit larger in power consumption than the input buffer circuit is connected to a second power supply voltage pad for applying a second power supply voltage, and a second ground line. The parasitic resistance of the first ground line is higher than that of the second ground line. By connecting a capacitance between a power supply line connected to the first power supply voltage pad, and the first ground line, fluctuations in first power supply voltage are suppressed to prevent the input buffer circuit from malfunctioning.
摘要翻译：输入缓冲电路连接到用于施加第一电源电压的第一电源电压焊盘和第一接地线。与输入缓冲电路相比，功耗大的内部电路连接到用于施加第二电源电压的第二电源电压焊盘和第二接地线。第一接地线的寄生电阻高于第二接地线的寄生电阻。通过连接连接到第一电源电压焊盘的电源线与第一接地线之间的电容，抑制第一电源电压的波动，以防止输入缓冲电路发生故障。

2. 再颁专利

USRE36404E Semiconductor memory device for use in apparatus requiring high-speed access to memory cells 失效
标题翻译：用于需要高速存取存储器单元的设备中的半导体存储器件
公开(公告)号：USRE36404E
公开(公告)日：1999-11-23
申请号：US970780
申请日：1997-11-14
申请人： Yasushi Kameda , Kenichi Nakamura , Hiroshi Takamoto , Takayuki Harima , Makoto Segawa
发明人： Yasushi Kameda , Kenichi Nakamura , Hiroshi Takamoto , Takayuki Harima , Makoto Segawa
IPC分类号： G11C11/41 , G11C8/14 , G11C11/40 , G11C7/00
CPC分类号： G11C8/14
摘要： A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition. Each logical circuit includes a first inverter, a CMOS type second inverter and an N-channel transistor. Each main word line is connected to the input terminals of the first and second inverters. Each section select line is connected to the drain of the N-type transistor and the source of a P-channel transistor of the second inverter. The gate of the N-channel transistor is connected to the output terminal of the first inverter and each section word line is connected to the source of the N-channel transistor and the output terminal of the second inverter. Bit lines are connected to each memory cell for receiving data from a selected memory cell and outputting the data.
摘要翻译：一种半导体存储器件，包括多个单元阵列部分，每个单元阵列部分具有以矩阵形式设置的多个存储单元，所述多个单元阵列部分在行方向上并置。主字线各自为每行中的所有多个单元阵列部分共同设置，行选择信号被应用于每个主字线。部分字线连接到每行的每个单元阵列部分中的存储单元，用于激活存储单元。为每个单元阵列区段提供区段选择线，区段选择信号被应用于每个区段选择线。为每个单元阵列部提供逻辑电路，每个逻辑电路连接到每个主字线和选区线，执行行选择信号和区段选择信号之间的逻辑运算，并且当逻辑运算结果满足规定的逻辑条件。每个逻辑电路包括第一反相器，CMOS型第二反相器和N沟道晶体管。每个主字线连接到第一和第二逆变器的输入端。各段选择线连接到N型晶体管的漏极和第二反相器的P沟道晶体管的源极。 N沟道晶体管的栅极连接到第一反相器的输出端子，并且每个部分字线连接到N沟道晶体管的源极和第二反相器的输出端子。位线连接到每个存储器单元，用于从所选存储单元接收数据并输出数据。

3. 发明授权

US5467317A Semiconductor memory device for use an apparatus requiring high-speed access to memory cells 失效
标题翻译：用于使用需要高速存取存储器单元的装置的半导体存储器件
公开(公告)号：US5467317A
公开(公告)日：1995-11-14
申请号：US328049
申请日：1994-10-24
申请人： Yasushi Kameda , Kenichi Nakamura , Hiroshi Takamoto , Takayuki Harima , Makoto Segawa
发明人： Yasushi Kameda , Kenichi Nakamura , Hiroshi Takamoto , Takayuki Harima , Makoto Segawa
IPC分类号： G11C11/41 , G11C8/14 , G11C11/40 , G11C11/34
CPC分类号： G11C8/14
摘要： A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition. Each logical circuit includes a first inverter, a CMOS type second inverter and an N-channel transistor. Each main word line is connected to the input terminals of the first and second inverters. Each section select line is connected to the drain of the N-type transistor and the source of a P-channel transistor of the second inverter. The gate of the N-channel transistor is connected to the output terminal of the first inverter and each section word line is connected to the source of the N-channel transistor and the output terminal of the second inverter. Bit lines are connected to each memory cell for receiving data from a selected memory cell and outputting the data.
摘要翻译：一种半导体存储器件，包括多个单元阵列部分，每个单元阵列部分具有以矩阵形式设置的多个存储单元，所述多个单元阵列部分在行方向上并置。主字线各自为每行中的所有多个单元阵列部分共同设置，行选择信号被应用于每个主字线。部分字线连接到每行的每个单元阵列部分中的存储单元，用于激活存储单元。为每个单元阵列区段提供区段选择线，区段选择信号被应用于每个区段选择线。为每个单元阵列部提供逻辑电路，每个逻辑电路连接到每个主字线和选区线，执行行选择信号和区段选择信号之间的逻辑运算，并且当逻辑运算结果满足规定的逻辑条件。每个逻辑电路包括第一反相器，CMOS型第二反相器和N沟道晶体管。每个主字线连接到第一和第二逆变器的输入端。各段选择线连接到N型晶体管的漏极和第二反相器的P沟道晶体管的源极。 N沟道晶体管的栅极连接到第一反相器的输出端子，并且每个部分字线连接到N沟道晶体管的源极和第二反相器的输出端子。位线连接到每个存储器单元，用于从所选存储单元接收数据并输出数据。

4. 发明授权

US5942784A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5942784A
公开(公告)日：1999-08-24
申请号：US891558
申请日：1997-07-11
申请人： Takayuki Harima , Kenichi Nakamura , Mitsugi Ogura
发明人： Takayuki Harima , Kenichi Nakamura , Mitsugi Ogura
IPC分类号： H01L21/8238 , H01L27/08 , H01L27/092 , H03K19/094 , H01L29/76 , H01L29/94
CPC分类号： H01L27/0921
摘要： A semiconductor device which achieves high-speed access and prevents the latch-up for any power inputting sequence by a plurality of power sources is disclosed. Where the chip voltage VDD is earlier inputted, an N well bias circuit 9 and a P well bias circuit 10 are activated, and an N-type well 12 and a P-type well 13 are biased respectively. After that, although the interface voltage VDDQ is inputted, the latch-up is not generated. On the other hand, where the interface voltage VDDQ is earlier inputted to a terminal 8, the N well bias circuit 9 and the P well bias circuit 10 are activated through a bypass circuit 15, and the N-type well 12 and the P-type well 13 are biased. Accordingly, although the chip voltage VDD is inputted after that, the latch-up is not generated.
摘要翻译：公开了一种实现高速访问并且防止由多个电源对闩锁进行任何功率输入序列的半导体器件。在芯片电压VDD较早输入的地方，N阱偏置电路9和P阱偏置电路10被激活，N型阱12和P型阱13分别被偏置。之后，虽然输入了接口电压VDDQ，但是不产生闭锁。另一方面，在接口电压VDDQ较早地输入端子8的情况下，N阱偏压电路9和P阱偏置电路10通过旁路电路15被激活，N型阱12和P- 类型井13有偏差。因此，尽管在此之后输入芯片电压VDD，但是不产生闩锁。

5. 发明授权

US06515938B2 Semiconductor memory device having an echo signal generating circuit 失效
标题翻译：具有回波信号发生电路的半导体存储器件
公开(公告)号：US06515938B2
公开(公告)日：2003-02-04
申请号：US09946189
申请日：2001-09-04
申请人： Takahiro Tsuruto , Takayuki Harima
发明人： Takahiro Tsuruto , Takayuki Harima
IPC分类号： G11C800
CPC分类号： G11C7/1051 , G11C7/1072
摘要： A semiconductor memory device includes a memory cell array, an address register for taking in an address synchronizing with a clock, a decode circuit for selecting a memory cell of the memory cell array by decoding the address retained in the address register, a reading/writing circuit for reading data from the memory cell array and writing the data to the memory cell array, a data register for temporarily retaining the data read from and written to the memory cell array, synchronizing with the clock, and an echo signal generation circuit, synchronizing with the clock, for outputting an echo signal composed of a predetermined expected value pattern for notifying the outside of a data output with a delay time equal to a transmission delay time of the output data read from the memory cell array.
摘要翻译：半导体存储器件包括存储单元阵列，用于取入与时钟同步的地址的地址寄存器，用于通过解码保存在地址寄存器中的地址来选择存储单元阵列的存储单元的解码电路，读/写用于从存储单元阵列读取数据并将数据写入存储单元阵列的电路，用于暂时保持与时钟同步的从存储单元阵列读取和写入数据的数据寄存器和回波信号发生电路，同步用于输出由预定期望值模式组成的回波信号，用于以等于从存储单元阵列读取的输出数据的传输延迟时间的延迟时间通知外部数据输出。

6. 发明授权

US5661429A Bi-CMOS circuit 失效
标题翻译：双CMOS电路
公开(公告)号：US5661429A
公开(公告)日：1997-08-26
申请号：US423613
申请日：1995-04-17
申请人： Takao Nakajima , Takayuki Harima , Makoto Segawa
发明人： Takao Nakajima , Takayuki Harima , Makoto Segawa
IPC分类号： H01L27/06 , H01L21/8249 , H03K19/013 , H03K19/08 , H03K19/0944 , H03K19/02 , H03K17/16 , H03K17/60
CPC分类号： H03K19/0136 , H03K19/09448
摘要： A BiCMOS circuit includes a CMOS circuit for inverting data applied to an input terminal and a first bipolar transistor, having a base connected to an output point of this CMOS circuit, a collector connected to a power supply voltage and an emitter connected to an output terminal, for charging the output terminal. The BiCMOS circuit also includes a second bipolar transistor, having a collector connected to the output terminal, for discharging the output terminal, a first MOS transistor of a first conductivity type connected in parallel between the base and the collector of the second bipolar transistor and a second MOS transistor of the first conductivity type connected in series with the first MOS transistor and having a gate connected to an output point of the CMOS circuit. The Bi-CMOS circuit further includes a third MOS transistor of the first conductivity type connected between the input terminal and the gate of the first MOS transistor of the first conductivity type and having a gate receiving a first reference voltage, and a fourth MOS transistor of a second conductivity type connected between the first reference voltage and the gate of the first MOS transistor. A large variation width of an output voltage can be ensured, and hence the Bi-CMOS circuit normally operates even at a low voltage without any deterioration in terms of delay time.
摘要翻译： BiCMOS电路包括用于将施加到输入端子的数据反相的CMOS电路和具有连接到该CMOS电路的输出点的基极，连接到电源电压的集电极和连接到输出端子的发射极的第一双极晶体管，用于对输出端子充电。 BiCMOS电路还包括第二双极晶体管，其具有连接到输出端子的集电极，用于对输出端子进行放电，第一导电类型的第一MOS晶体管并联连接在第二双极晶体管的基极和集电极之间，所述第一导电类型的第二MOS晶体管与所述第一MOS晶体管串联连接，并且具有连接到所述CMOS电路的输出点的栅极。 Bi-CMOS电路还包括连接在第一导电类型的第一MOS晶体管的输入端和栅极之间的第一导电类型的第三MOS晶体管，并具有接收第一参考电压的栅极，以及第四MOS晶体管连接在第一参考电压和第一MOS晶体管的栅极之间的第二导电类型。可以确保输出电压的大的变化幅度，因此即使在低电压下，Bi-CMOS电路也能正常工作，而且延迟时间方面没有任何劣化。

7. 发明授权

US07188267B2 Semiconductor device having a first clock signal configured to operate sychronously with a second clock signal by use of a measuring and setting circuit 失效
标题翻译：具有第一时钟信号的半导体器件，其被配置为通过使用测量和设置电路与第二时钟信号同步地操作
公开(公告)号：US07188267B2
公开(公告)日：2007-03-06
申请号：US10370404
申请日：2003-02-19
申请人： Takayuki Harima
发明人： Takayuki Harima
IPC分类号： G06F1/12
CPC分类号： G06F5/06 , G06F1/025
摘要： A first circuit is disposed on the semiconductor substrate, operates synchronously with a first clock signal, and outputs a first output signal delayed by a first delay time from the first clock signal. A first measuring circuit measures indirectly a first increase and a first decrease of the first delay time. A setting circuit operates synchronously with the first clock signal, outputs a second clock signal delayed from the first clock signal by a second delay time adding the first increase and subtracting the first decrease. A second circuit inputs the first output signal and operates synchronously with the second clock signal.
摘要翻译：第一电路设置在半导体衬底上，与第一时钟信号同步工作，并从第一时钟信号输出延迟了第一延迟时间的第一输出信号。第一测量电路间接测量第一延迟时间的第一次增加和第一次减小。设置电路与第一时钟信号同步地操作，从第一时钟信号延迟第二延迟时间的第二时钟信号，加上第一次增加并减去第一次减小。第二电路输入第一输出信号并与第二时钟信号同步地操作。

8. 发明授权

US5715202A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5715202A
公开(公告)日：1998-02-03
申请号：US577205
申请日：1995-12-21
申请人： Takayuki Harima
发明人： Takayuki Harima
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , G11C13/00
CPC分类号： G11C29/80 , G11C29/808
摘要： A semiconductor memory device includes memory cell array blocks and row spare cell groups provided for the memory cell array blocks adjacent to each other and each of the row spare cell groups having a plurality of spare cells for relieving defective memory cells in the adjacent memory cell array blocks. The row spare cell groups are shared by the plurality of adjacent memory cell array blocks, hence the spare cells are allocated corresponding to the defective cells found in the memory cell array blocks, thus enhancing a relieving rate by a redundancy circuit.
摘要翻译：一种半导体存储器件包括为相邻的存储单元阵列块提供的存储单元阵列块和行备用单元组，并且每个行备用单元组具有多个备用单元，用于释放相邻存储单元阵列中的有缺陷的存储单元块。行备用单元组由多个相邻的存储单元阵列块共享，因此对应于在存储单元阵列块中找到的缺陷单元分配备用单元，从而通过冗余电路提高缓解率。

9. 发明授权

US06388937B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06388937B2
公开(公告)日：2002-05-14
申请号：US09812361
申请日：2001-03-20
申请人： Yoshikazu Takeyama , Takayuki Harima
发明人： Yoshikazu Takeyama , Takayuki Harima
IPC分类号： G11C800
CPC分类号： G11C7/1018 , G11C7/1072 , G11C11/418
摘要： A semiconductor memory device according to the present invention includes a burst counter for sequentially automatically generating an address of a predetermined bit number in synchronism with a clock on the basis of a predetermined sequence in the subsequent operation cycle in accordance with the inputted initial address, and a plurality of memory cell sub-arrays which is formed by dividing a memory cell array. The semiconductor memory device further comprises a plurality of block decoder selection-time adjusting circuits for sequentially outputting a first block selecting signal, which is the base of a signal for selecting each of the memory cell sub-arrays, as a second block selecting signal at a timing corresponding to a read latency and for outputting the first block selecting signal as a third block selecting signal which has a length corresponding to the read latency.
摘要翻译：根据本发明的半导体存储器件包括：突发计数器，用于根据所输入的初始地址，根据随后的操作周期中的预定顺序，与时钟同步地顺序自动生成预定位数的地址;以及通过划分存储单元阵列形成的多个存储单元子阵列。半导体存储器件还包括多个块解码器选择时间调整电路，用于顺序地输出作为用于选择每个存储单元子阵列的信号的基础的第一块选择信号作为第二块选择信号，作为第二块选择信号对应于读等待时间的定时，以及用于输出第一块选择信号作为具有对应于读等待时间的长度的第三块选择信号。

10. 发明授权

US5835423A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5835423A
公开(公告)日：1998-11-10
申请号：US838508
申请日：1997-04-08
申请人： Takayuki Harima
发明人： Takayuki Harima
IPC分类号： G11C11/419 , G11C7/06 , G11C7/12 , G11C7/22 , H01L27/10 , G11C7/00
CPC分类号： G11C7/22 , G11C7/06 , G11C7/12
摘要： A semiconductor device comprises: a memory cell array which has a plurality of memory cell to output data from a memory cell selected on the basis of an externally input signal; a sense amplifier for receiving the data output from said memory cell array, amplifying the data, and outputting the data; and a pulse generator for receiving the input signal and outputting a pulse for determining a timing at which said sense amplifier is activated, wherein said pulse generator includes a circuit pattern electrically equivalent to elements included in said memory cell. According to the above device, the pulse generator includes the same pattern as that of elements included in the memory cell. When the operation speed of the memory cell varies due to the manufacturing process, etc, the variation can be canceled by a similar variation, so that an erroneous operation of the sense amplifier is prevented and the operation speed can be increased.
摘要翻译：一种半导体器件包括：具有多个存储单元的存储单元阵列，用于从基于外部输入信号选择的存储单元输出数据; 读出放大器，用于接收从所述存储单元阵列输出的数据，放大数据并输出数据; 以及脉冲发生器，用于接收所述输入信号并输出用于确定所述读出放大器被激活的定时的脉冲，其中所述脉冲发生器包括与所述存储单元中包含的元件电气等效的电路图案。根据上述装置，脉冲发生器包括与包含在存储单元中的元件相同的图案。当存储单元的操作速度由于制造过程等而变化时，可以通过类似的变化消除变化，从而防止读出放大器的错误操作并且可以提高操作速度。

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