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1. 再颁专利

USRE36404E Semiconductor memory device for use in apparatus requiring high-speed access to memory cells 失效
标题翻译：用于需要高速存取存储器单元的设备中的半导体存储器件
公开(公告)号：USRE36404E
公开(公告)日：1999-11-23
申请号：US970780
申请日：1997-11-14
申请人： Yasushi Kameda , Kenichi Nakamura , Hiroshi Takamoto , Takayuki Harima , Makoto Segawa
发明人： Yasushi Kameda , Kenichi Nakamura , Hiroshi Takamoto , Takayuki Harima , Makoto Segawa
IPC分类号： G11C11/41 , G11C8/14 , G11C11/40 , G11C7/00
CPC分类号： G11C8/14
摘要： A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition. Each logical circuit includes a first inverter, a CMOS type second inverter and an N-channel transistor. Each main word line is connected to the input terminals of the first and second inverters. Each section select line is connected to the drain of the N-type transistor and the source of a P-channel transistor of the second inverter. The gate of the N-channel transistor is connected to the output terminal of the first inverter and each section word line is connected to the source of the N-channel transistor and the output terminal of the second inverter. Bit lines are connected to each memory cell for receiving data from a selected memory cell and outputting the data.
摘要翻译：一种半导体存储器件，包括多个单元阵列部分，每个单元阵列部分具有以矩阵形式设置的多个存储单元，所述多个单元阵列部分在行方向上并置。主字线各自为每行中的所有多个单元阵列部分共同设置，行选择信号被应用于每个主字线。部分字线连接到每行的每个单元阵列部分中的存储单元，用于激活存储单元。为每个单元阵列区段提供区段选择线，区段选择信号被应用于每个区段选择线。为每个单元阵列部提供逻辑电路，每个逻辑电路连接到每个主字线和选区线，执行行选择信号和区段选择信号之间的逻辑运算，并且当逻辑运算结果满足规定的逻辑条件。每个逻辑电路包括第一反相器，CMOS型第二反相器和N沟道晶体管。每个主字线连接到第一和第二逆变器的输入端。各段选择线连接到N型晶体管的漏极和第二反相器的P沟道晶体管的源极。 N沟道晶体管的栅极连接到第一反相器的输出端子，并且每个部分字线连接到N沟道晶体管的源极和第二反相器的输出端子。位线连接到每个存储器单元，用于从所选存储单元接收数据并输出数据。

2. 发明授权

US5467317A Semiconductor memory device for use an apparatus requiring high-speed access to memory cells 失效
标题翻译：用于使用需要高速存取存储器单元的装置的半导体存储器件
公开(公告)号：US5467317A
公开(公告)日：1995-11-14
申请号：US328049
申请日：1994-10-24
申请人： Yasushi Kameda , Kenichi Nakamura , Hiroshi Takamoto , Takayuki Harima , Makoto Segawa
发明人： Yasushi Kameda , Kenichi Nakamura , Hiroshi Takamoto , Takayuki Harima , Makoto Segawa
IPC分类号： G11C11/41 , G11C8/14 , G11C11/40 , G11C11/34
CPC分类号： G11C8/14
摘要： A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition. Each logical circuit includes a first inverter, a CMOS type second inverter and an N-channel transistor. Each main word line is connected to the input terminals of the first and second inverters. Each section select line is connected to the drain of the N-type transistor and the source of a P-channel transistor of the second inverter. The gate of the N-channel transistor is connected to the output terminal of the first inverter and each section word line is connected to the source of the N-channel transistor and the output terminal of the second inverter. Bit lines are connected to each memory cell for receiving data from a selected memory cell and outputting the data.
摘要翻译：一种半导体存储器件，包括多个单元阵列部分，每个单元阵列部分具有以矩阵形式设置的多个存储单元，所述多个单元阵列部分在行方向上并置。主字线各自为每行中的所有多个单元阵列部分共同设置，行选择信号被应用于每个主字线。部分字线连接到每行的每个单元阵列部分中的存储单元，用于激活存储单元。为每个单元阵列区段提供区段选择线，区段选择信号被应用于每个区段选择线。为每个单元阵列部提供逻辑电路，每个逻辑电路连接到每个主字线和选区线，执行行选择信号和区段选择信号之间的逻辑运算，并且当逻辑运算结果满足规定的逻辑条件。每个逻辑电路包括第一反相器，CMOS型第二反相器和N沟道晶体管。每个主字线连接到第一和第二逆变器的输入端。各段选择线连接到N型晶体管的漏极和第二反相器的P沟道晶体管的源极。 N沟道晶体管的栅极连接到第一反相器的输出端子，并且每个部分字线连接到N沟道晶体管的源极和第二反相器的输出端子。位线连接到每个存储器单元，用于从所选存储单元接收数据并输出数据。

3. 发明授权

US5079612A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：US5079612A
公开(公告)日：1992-01-07
申请号：US564615
申请日：1990-08-09
申请人： Hiroshi Takamoto , Makoto Segawa
发明人： Hiroshi Takamoto , Makoto Segawa
IPC分类号： H01L21/822 , H01L27/02 , H01L27/04
CPC分类号： H01L27/0248
摘要： A semiconductor IC device including a main circuit block and at least one subcircuit block, each having a ground terminal, a supply voltage terminal and an input or output terminal. A first ground line is connected to the ground terminal of the main circuit block and arranged within a wiring domain of the main circuit block and adjacent to the subcircuit blocks. A second ground line is connected to the ground terminal of the subcircuit block and arranged within a wiring domain of the subcircuit block and adjacent to the main circuit block. Protective elements are connected between the first and second ground lines so as to form short circuits through at least one of the first and second ground lines. In the IC device thus configured, all of the input and output terminals resist overvoltage, in every case where any one of the ground terminals and the supply voltage terminals is determined as a reference potential terminal, without complicating the protective element wiring arrangement or increasing the chip area and the cost thereof.

4. 发明授权

US5345122A Cascade sense amplifier for reading out data stored in semiconductor memory device 失效
标题翻译：用于读出存储在半导体存储器件中的数据的级联读出放大器
公开(公告)号：US5345122A
公开(公告)日：1994-09-06
申请号：US51305
申请日：1993-04-22
申请人： Hiroshi Takamoto , Takenori Nakamura , Kenichi Nakamura
发明人： Hiroshi Takamoto , Takenori Nakamura , Kenichi Nakamura
IPC分类号： G11C11/416 , G11C7/06 , H01L27/10 , H03K5/24 , H03F3/45 , H03K5/22
CPC分类号： G11C7/062 , H03K5/2418 , H03K5/2427
摘要： A cascade sense amplifier includes section separated sense amplifiers, a cascade wiring and a main sense amplifier. The main sense amplifier has a capacitance regulation element provided at a base potential of input transistors constituting a data input end. The element is comprised of a metal oxide semiconductor (MOS) transistor for forming a capacitance corresponding to a potential V.sub.SS mainly forming a capacitance by the cascade wiring. A size of the element is determined in the manner that the base potential drop time of the transistors is equal to a potential drop time of the cascade wiring when a power source voltage V.sub.CC drops. Even though the power source voltage V.sub.CC drops, the transistors have no cut-off condition so as to prevent the read-out time from delaying. Especially, if the element is comprised of a MOS transistor, it is possible to use an extremely thin gate insulation layer as a dielectric, thereby suppressing an increase of a chip size.
摘要翻译：级联感测放大器包括分段读出放大器，级联布线和主读出放大器。主感测放大器具有设置在构成数据输入端的输入晶体管的基极电位的电容调节元件。该元件由金属氧化物半导体（MOS）晶体管构成，该金属氧化物半导体用于形成主要由级联布线形成电容的电位VSS对应的电容。在电源电压VCC下降时，以晶体管的基极电位下降时间等于级联布线的电位下降时间的方式确定元件的尺寸。即使电源电压VCC下降，晶体管也没有截止条件，以防止读出时间延迟。特别地，如果元件由MOS晶体管组成，则可以使用非常薄的栅极绝缘层作为电介质，从而抑制芯片尺寸的增加。

5. 发明授权

US5440418A Method and apparatus for alarm surveillance for an optical transmission system 失效
标题翻译：光传输系统报警监控方法及装置
公开(公告)号：US5440418A
公开(公告)日：1995-08-08
申请号：US80113
申请日：1993-06-23
申请人： Katsuhiro Ishimura , Hiroshi Takamoto , Shusei Aoki
发明人： Katsuhiro Ishimura , Hiroshi Takamoto , Shusei Aoki
IPC分类号： H04B10/07 , H04B10/077 , H04B10/29 , H04B10/08
CPC分类号： H04B10/291 , H04B10/0777 , H04B2210/078
摘要： Each optical repeater in an optical transmission system includes an optical amplifier, and a control circuit for controlling the optical transmission. Furthermore, each optical repeater transmits management information to the next optical repeater. The control circuit checks the status of the optical amplifier and obtains monitoring information. The control circuit generates management information in accordance with the monitoring information and the management information transmitted from the upstream side optical repeater. The management information is converted to an optical signal and transmitted to the next optical repeater. A receiving station receives the management information. The management information includes an ID code for an optical repeater which has failed and the status of the failure. Different categories of management information have priorities which can be changed by the receiving station, and thus the receiving station can detect the status of the optical transmission line easily and flexibly.
摘要翻译：光传输系统中的每个光中继器包括光放大器和用于控制光传输的控制电路。此外，每个光中继器向下一个光中继器发送管理信息。控制电路检查光放大器的状态并获得监控信息。控制电路根据从上游侧光中继器发送的监视信息和管理信息，生成管理信息。管理信息被转换为光信号并传送到下一个光中继器。接收站接收管理信息。管理信息包括已经失败的光中继器的ID码和故障状态。不同类别的管理信息具有可由接收站改变的优先级，因此接收站可以容易且灵活地检测光传输线的状态。

6. 发明授权

US5378950A Semiconductor integrated circuit for producing activation signals at different cycle times 失效
标题翻译：用于在不同周期时间产生激活信号的半导体集成电路
公开(公告)号：US5378950A
公开(公告)日：1995-01-03
申请号：US829473
申请日：1992-02-03
申请人： Hiroshi Takamoto , Mikio Etou
发明人： Hiroshi Takamoto , Mikio Etou
IPC分类号： H03K5/15 , H03K17/28 , H03K5/159
CPC分类号： H03K5/1504
摘要： A semiconductor integrated circuit has n number of operating circuits that each operate at a predetermined cycle time; n number of wirings that transmit activation signals with respect to said n number of wirings; and a selector drive circuit that sends activation signals to said n number of wirings at respectively different cycle times. By avoiding the simultaneous drive of the operation circuits, the widths of wirings are maintained.
摘要翻译：半导体集成电路具有n个操作电路，每个操作电路以预定的周期时间运行; n个相对于所述n条布线发送激活信号的布线; 以及选择器驱动电路，其分别在不同的周期时间向所述n条布线发送激活信号。通过避免操作电路的同时驱动，维持布线的宽度。

7. 发明授权

US5335207A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5335207A
公开(公告)日：1994-08-02
申请号：US729561
申请日：1991-07-15
申请人： Hiroshi Takamoto
发明人： Hiroshi Takamoto
IPC分类号： G11C11/41 , G11C7/12 , G11C8/18 , G11C7/00 , H01L27/00
CPC分类号： G11C7/12 , G11C8/18
摘要： A semiconductor IC device includes a memory cell group; a pair of bit lines connected to the cell group; plural equalization transistors T.sub.R connected between the bit lines; address transition detectors ATD for detecting changes in address bits; and plural equalizing pulse generating circuits composed of plural logical gates, 15 to 22, respectively and provided for each equalization transistor to generate an equalizing pulse signal to each equalization transistor so that the levels of the two bit lines can be equalized with each other. Since signals outputted from the address transition detectors are synthesized, in particular at a node to which the equalizing pulse signal is applied, the number of logical gate stages to synthesize the detector output signals can be reduced and the wire lengths (e.g. wire capacitances) of the logical gates can be well balanced, thus improving the equalizing speed of the IC device.
摘要翻译：半导体IC器件包括存储单元组; 连接到单元组的一对位线; 连接在位线之间的多个均衡晶体管TR; 用于检测地址位变化的地址转换检测器ATD; 以及多个均衡脉冲发生电路，分别由多个逻辑门15至22组成，并为每个均衡晶体管提供均衡脉冲信号，以产生均衡脉冲信号给每个均衡晶体管，使两个位线的电平相互相等。由于从地址转换检测器输出的信号被合成，特别是在施加了均衡脉冲信号的节点处，可以减少用于合成检测器输出信号的逻辑门级数，并且可以减少线长度（例如线电容）逻辑门可以很好地平衡，从而提高了IC器件的均衡速度。

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