专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5893743A Process of fabricating semiconductor device 失效
标题翻译：制造半导体器件的工艺
公开(公告)号：US5893743A
公开(公告)日：1999-04-13
申请号：US877422
申请日：1997-06-17
申请人： Takayuki Gomi , Hiroaki Ammo
发明人： Takayuki Gomi , Hiroaki Ammo
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8228 , H01L27/082 , H01L29/732
CPC分类号： H01L21/82285
摘要： A process for forming a first bipolar transistor having a single polysilicon structure and a second bipolar transistor having a single polysilicon structure and being of a conducting type opposite to that of the first bipolar transistor on the same substrate. In the process of fabricating a semiconductor device in which a first bipolar transistor having a single polysilicon structure, a second bipolar transistor having a single polysilicon structure and being of a conducting type opposite to that of the first bipolar transistor, and a third bipolar transistor having a double polysilicon structure are provided on the same semiconductor substrate, a base contact portion of the first bipolar transistor and an emitter of the second bipolar transistor are formed in the same step, and an emitter of the first bipolar transistor and base contact portions of the second and third bipolar transistors are formed in the same step.
摘要翻译：一种用于形成具有单个多晶硅结构的第一双极晶体管和具有单个多晶硅结构并且在同一衬底上具有与第一双极晶体管相反的导电类型的第二双极晶体管的工艺。在制造其中具有单个多晶硅结构的第一双极晶体管，具有单个多晶硅结构并且具有与第一双极晶体管相反的导电类型的第二双极晶体管的半导体器件的过程中，以及第三双极晶体管，在相同的半导体衬底上设置双重多晶硅结构，第一双极晶体管的基极接触部分和第二双极晶体管的发射极在同一步骤中形成，并且第一双极晶体管和基极接触部分的发射极在同一步骤中形成第二和第三双极晶体管。

2. 发明授权

US5976940A Method of making plurality of bipolar transistors 失效
标题翻译：制造多个双极晶体管的方法
公开(公告)号：US5976940A
公开(公告)日：1999-11-02
申请号：US762779
申请日：1996-12-10
申请人： Takayuki Gomi , Hiroaki Ammo
发明人： Takayuki Gomi , Hiroaki Ammo
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L27/06 , H01L29/732
CPC分类号： H01L21/8222
摘要： In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substrate the first bipolar transistor has an N.sup.+ -type first embedded diffusion layer having an impurity concentration higher than that of the epitaxial layer and the second bipolar transistor has an N-type second embedded diffusion layer having a lower impurity concentration and a deeper diffusion layer depth than the first embedded diffusion layer, whereby a high speed bipolar transistor and a high voltage bipolar transistor are formed on the same substrate.
摘要翻译：在包括通过在硅衬底上形成外延层制成的半导体衬底上形成的具有不同电压的第一双极晶体管和第二双极晶体管的半导体器件中，在硅衬底的上部中，第一双极晶体管具有N +型具有比外延层高的杂质浓度的第一嵌入扩散层和第二双极晶体管具有N型第二嵌入扩散层，其具有比第一嵌入扩散层更低的杂质浓度和更深的扩散层深度，由此高高速双极晶体管和高电压双极晶体管形成在同一衬底上。

3. 发明授权

US6034402A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US6034402A
公开(公告)日：2000-03-07
申请号：US95043
申请日：1998-06-10
申请人： Hiroaki Ammo , Takayuki Gomi
发明人： Hiroaki Ammo , Takayuki Gomi
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L29/76
CPC分类号： H01L21/8249 , H01L27/0623
摘要： A semiconductor device comprises: a substrate; a first buried layer of a first conduction type formed in the substrate; a second buried layer of the first conduction type formed in the substrate; a third buried layer of the first conduction type formed in the substrate; an epitaxial layer of the first conduction type formed on the substrate; a well region of a second conduction type formed in the epitaxial layer above the third buried layer; source/drain regions of the first conduction type formed in the well region; a first base region of the second conduction type formed in the epitaxial layer above the first buried layer; a first impurity region of the first conduction type formed on the first base region; a second base region of the second conduction type formed in the epitaxial layer above the second buried layer; a second impurity region of the first conduction type formed on the second base region; a first lead-out layer of the first conduction type connected to the first buried layer; and a second lead-out layer of the first conduction type connected to the second buried layer. The second buried layer has an impurity concentration substantially equal to that of the third buried layer.
摘要翻译：半导体器件包括：衬底; 形成在基板中的第一导电类型的第一掩埋层; 形成在基板中的第一导电类型的第二掩埋层; 在衬底中形成第一导电类型的第三掩埋层; 在基板上形成第一导电类型的外延层; 形成在第三掩埋层上方的外延层中的第二导电类型的阱区; 在该区域中形成的第一导电类型的源极/漏极区域; 形成在第一掩埋层上方的外延层中的第二导电类型的第一基极区; 形成在第一基极区上的第一导电类型的第一杂质区; 在第二掩埋层上方的外延层中形成的第二导电类型的第二基极区; 形成在第二基极区上的第一导电类型的第二杂质区; 连接到第一掩埋层的第一导电类型的第一引出层; 以及连接到第二掩埋层的第一导电类型的第二引出层。第二掩埋层的杂质浓度基本上等于第三掩埋层的杂质浓度。

4. 发明授权

US06977426B1 Semiconductor device including high speed transistors and high voltage transistors disposed on a single substrate 失效
标题翻译：半导体装置包括设置在单个基板上的高速晶体管和高压晶体管
公开(公告)号：US06977426B1
公开(公告)日：2005-12-20
申请号：US08965286
申请日：1997-11-06
申请人： Takayuki Gomi , Hiroaki Ammo
发明人： Takayuki Gomi , Hiroaki Ammo
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L27/06 , H01L29/732 , H01L29/00 , H01L27/082
CPC分类号： H01L21/8222
摘要： In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substrate the first bipolar transistor has an N+-type first embedded diffusion layer having an impurity concentration higher than that of the epitaxial layer and the second bipolar transistor has an N-type second embedded diffusion layer having a lower impurity concentration and a deeper diffusion layer depth than the first embedded diffusion layer, whereby a high speed bipolar transistor and a high voltage bipolar transistor are formed on the same substrate.
摘要翻译：在包括形成在通过在硅衬底上形成外延层而制成的半导体衬底上的不同电压的第一双极晶体管和第二双极晶体管的半导体器件中，在硅衬底的上部中，第一双极晶体管具有N < 具有比外延层高的杂质浓度的第一嵌入扩散层和第二双极晶体管具有N型第二嵌入扩散层，其具有较低的杂质浓度和较深的扩散层深度第一嵌入式扩散层，由此在相同的衬底上形成高速双极晶体管和高电压双极晶体管。

5. 发明授权

US5846867A Method of producing Si-Ge base heterojunction bipolar device 失效
标题翻译：生产Si-Ge基极异质结双极器件的方法
公开(公告)号：US5846867A
公开(公告)日：1998-12-08
申请号：US768171
申请日：1996-12-17
申请人： Takayuki Gomi , Hiroaki Ammo
发明人： Takayuki Gomi , Hiroaki Ammo
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/7378 , Y10S148/01 , Y10S148/058 , Y10S148/059 , Y10S148/072
摘要： A method of producing a bipolar transistor includes the step of forming an emitter contact layer containing a high concentration of impurity by means of plasma doping or solid-state diffusion without causing diffusion of impurity in a base layer. This makes it possible to realize a thin base layer having a high impurity concentration. The invention also provides a method of producing a semiconductor device including a bipolar transistor and another device element such as a resistor element including a polysilicon layer containing an activated impurity in such a manner that both the bipolar transistor and the device element are disposed on the same single substrate, the method including the steps of: forming a polysilicon layer containing an activated impurity on the surface of a substrate; and then forming a base layer of the bipolar transistor. This method prevents the base layer from being affected by heat treatment on the polysilicon layer.
摘要翻译：制造双极晶体管的方法包括通过等离子体掺杂或固态扩散形成含有高浓度杂质的发射极接触层的步骤，而不会引起杂质在基底层中的扩散。这使得可以实现具有高杂质浓度的薄基底层。本发明还提供了一种制造半导体器件的方法，该半导体器件包括双极晶体管和另一器件元件，例如包括含有活性杂质的多晶硅层的电阻元件，使得双极晶体管和器件元件都位于同一位置所述方法包括以下步骤：在衬底的表面上形成含有活化杂质的多晶硅层; 然后形成双极晶体管的基极层。该方法防止了基底层受多晶硅层上的热处理的影响。

6. 发明授权

US5830799A Method for forming embedded diffusion layers using an alignment mark 失效
标题翻译：使用对准标记形成嵌入扩散层的方法
公开(公告)号：US5830799A
公开(公告)日：1998-11-03
申请号：US700081
申请日：1996-08-20
申请人： Hiroaki Ammo , Shigeru Kanematsu , Takayuki Gomi
发明人： Hiroaki Ammo , Shigeru Kanematsu , Takayuki Gomi
IPC分类号： H01L29/73 , H01L21/265 , H01L21/331 , H01L21/74 , H01L21/8228 , H01L23/544 , H01L27/082 , H01L29/732 , H01L27/06
CPC分类号： H01L21/26513 , H01L21/74 , H01L21/8228 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S148/102 , Y10S438/975
摘要： To form NPN and PNP transistors on the same base for example to obtain a complementary bipolar transistor it has been necessary to make an epitaxial layer a thick film, and this has resulted in deterioration of the characteristics of the NPN transistor. Also, because a step of forming an alignment mark has been necessary this has increased the number of manufacturing steps needed to make a complementary bipolar transistor. This invention provides a semiconductor device manufacturing method which solves this problem as follows: After a first opening 13 (alignment mark 16) and a second opening 14 are formed in an insulating film 12 formed on a semiconductor base 11 and a doping mask 15 is then formed on the semiconductor base 11, a third opening 17 is formed thereon with the alignment mark 16 as a reference. After an impurity 18 is introduced into the semiconductor base 11 through the third opening 17, the doping mask 15 is removed and after that an impurity 19 is introduced into the semiconductor base 11 by solid-phase diffusion through the second opening 14 and a first embedded diffusion layer 20 is thereby formed and at the same time the impurity 18 is caused to diffuse and form a second embedded diffusion layer 21. Then, after an epitaxial layer is formed, an impurity diffusion layer is formed therein by ion injection (not shown).
摘要翻译：为了在相同的基底上形成NPN和PNP晶体管以获得互补双极晶体管，必须使外延层成为厚膜，这导致NPN晶体管的特性劣化。此外，由于需要形成对准标记的步骤，这增加了制造互补双极晶体管所需的制造步骤的数量。本发明提供如下解决该问题的半导体器件制造方法：在形成在半导体基底11上的绝缘膜12和掺杂掩模15中形成第一开口13（对准标记16）和第二开口14之后形成在半导体基板11上的第三开口17上形成有对准标记16作为基准。在通过第三开口17将杂质18引入半导体基底11之后，去除掺杂掩模15，然后通过固相扩散通过第二开口14将杂质19引入半导体基底11中，并且第一嵌入从而形成扩散层20，同时使杂质18扩散并形成第二嵌入扩散层21.然后，在形成外延层之后，通过离子注入（未示出）在其中形成杂质扩散层，。

7. 发明授权

US6159784A Method of producing semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US6159784A
公开(公告)日：2000-12-12
申请号：US332038
申请日：1999-06-14
申请人： Hiroaki Ammo , Hiroyuki Miwa
发明人： Hiroaki Ammo , Hiroyuki Miwa
IPC分类号： H01L21/8249 , H01L27/06
CPC分类号： H01L21/8249 , H01L27/0635
摘要： A method of producing a semiconductor device by which the resistivities of the base, collector, and source/drain regions in a Bi-CMOS are decreased and the production step is simplified. A method of producing a semiconductor device comprising the steps of forming a gate electrode (the first semiconductor layer) on a substrate; forming an insulating film; forming a second semiconductor layer; leaving the second semiconductor layer and the insulating film on the bipolar part and removing them on the CMOS part to form sidewalls on the side faces of the gate electrode; forming source/drain regions; forming a Ti layer over the entire surface and forming silicide on the surfaces of the second semiconductor layer, the source/drain regions, and the gate electrode; and forming a base electrode by patterning the second semiconductor layer.
摘要翻译：制造半导体器件的方法，其中Bi-CMOS中的基极，集电极和源极/漏极区的电阻率降低，并且制造步骤简化。一种制造半导体器件的方法，包括以下步骤：在衬底上形成栅电极（第一半导体层）; 形成绝缘膜; 形成第二半导体层; 将第二半导体层和绝缘膜留在双极部上，并在CMOS部分上去除它们，以在栅电极的侧面上形成侧壁; 形成源/漏区; 在整个表面上形成Ti层，并在第二半导体层，源/漏区和栅电极的表面上形成硅化物; 以及通过图案化所述第二半导体层形成基极。

8. 发明授权

US06136634A Method of manufacturing semiconductor resistors 失效
标题翻译：制造半导体电阻的方法
公开(公告)号：US06136634A
公开(公告)日：2000-10-24
申请号：US86208
申请日：1998-05-28
申请人： Katsuyuki Kato , Hiroyuki Miwa , Hiroaki Ammo
发明人： Katsuyuki Kato , Hiroyuki Miwa , Hiroaki Ammo
IPC分类号： H01L21/02 , H01L21/84 , H01L27/08 , H01L27/12 , H01L21/8238 , H01L21/8222 , H01L29/00 , H01L29/76
CPC分类号： H01L28/20 , H01L21/84 , H01L27/0802 , H01L27/1203
摘要： A high-resistance polycrystalline Si resistor having a stable resistance value even when micro-sized and a low-resistance polycrystalline Si resistor having a sufficiently low desired resistance value wherein a polycrystalline Si film is formed on an insulation film located on a Si substrate, high-resistance-making ion implantation is applied to the entire surface and medium-resistance-making ion implantation is selectively applied to a medium-resistance-making region of the polycrystalline Si film. Low-resistance-making ion implantation is selectively applied to a low-resistance-making region of the polycrystalline Si film. The product is annealed to grow the polycrystalline Si film by solid-phase growth, the film is patterned to form a high-resistance polycrystalline Si resistor, medium-resistance polycrystalline Si resistor, and low-resistance polycrystalline Si resistor.
摘要翻译：即使在具有足够低的期望电阻值的微小尺寸的情况下也具有稳定的电阻值的高电阻多晶Si电阻器，其中在位于Si衬底上的绝缘膜上形成多晶Si膜，高对整个表面施加电阻制造离子注入，并且将中等电阻制造离子注入选择性地施加到多晶Si膜的中阻制造区域。选择性地将低电阻制造离子注入施加到多晶Si膜的低电阻制造区域。将产物退火以通过固相生长生长多晶Si膜，该膜被图案化以形成高电阻多晶硅电阻器，中等电阻多晶Si电阻器和低电阻多晶Si电阻器。

9. 发明授权

US08178933B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08178933B2
公开(公告)日：2012-05-15
申请号：US13039684
申请日：2011-03-03
申请人： Akira Mizumura , Hiroaki Ammo , Tetsuya Oishi
发明人： Akira Mizumura , Hiroaki Ammo , Tetsuya Oishi
IPC分类号： H01L27/088
CPC分类号： H01L21/845 , H01L21/823431 , H01L27/0207 , H01L27/088 , H01L27/0886 , H01L27/1203 , H01L29/66795 , H01L29/785
摘要： A semiconductor device including first and second transistors, each of the first and second transistors being formed with a plurality of fin transistors, and the first and second transistors being connected in parallel to electrically share a source, wherein the plurality of fin transistors each include a fin activation layer, the fin activation layer protruding from a semiconductor substrate, a source layer serving as the source being formed on one end, and a drain layer on the other end of the fin activation layer so as to form a channel region, the fin activation layers are arranged adjacent to each other in parallel, and the drain layers are disposed so that the currents flow through the plurality of fin transistors in opposite directions between the first and second transistors.
摘要翻译：一种包括第一和第二晶体管的半导体器件，第一和第二晶体管中的每一个形成有多个鳍式晶体管，并且第一和第二晶体管并联连接以电共享源，其中多个鳍式晶体管每个包括翅片活化层，从半导体衬底突出的翅片活化层，在一端形成源极的源极层和翅片活化层的另一端的漏极层，以形成沟道区域，鳍状物激活层平行地彼此相邻布置，并且漏极层被布置成使得电流在第一和第二晶体管之间沿相反方向流过多个鳍式晶体管。

10. 发明申请

US20110186932A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110186932A1
公开(公告)日：2011-08-04
申请号：US13039684
申请日：2011-03-03
申请人： Akira Mizumura , Hiroaki Ammo , Tetsuya Oishi
发明人： Akira Mizumura , Hiroaki Ammo , Tetsuya Oishi
IPC分类号： H01L27/088
CPC分类号： H01L21/845 , H01L21/823431 , H01L27/0207 , H01L27/088 , H01L27/0886 , H01L27/1203 , H01L29/66795 , H01L29/785
摘要： A semiconductor device including first and second transistors, each of the first and second transistors being formed with a plurality of fin transistors, and the first and second transistors being connected in parallel to electrically share a source, wherein the plurality of fin transistors each include a fin activation layer, the fin activation layer protruding from a semiconductor substrate, a source layer serving as the source being formed on one end, and a drain layer on the other end of the fin activation layer so as to form a channel region, the fin activation layers are arranged adjacent to each other in parallel, and the drain layers are disposed so that the currents flow through the plurality of fin transistors in opposite directions between the first and second transistors.
摘要翻译：一种包括第一和第二晶体管的半导体器件，第一和第二晶体管中的每一个形成有多个鳍式晶体管，并且第一和第二晶体管并联连接以电共享源，其中多个鳍式晶体管每个包括翅片活化层，从半导体衬底突出的翅片活化层，在一端形成源极的源极层和翅片活化层的另一端的漏极层，以形成沟道区域，鳍状物激活层平行地彼此相邻布置，并且漏极层被布置成使得电流在第一和第二晶体管之间沿相反方向流过多个鳍式晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式