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1. 发明授权

US5856228A Manufacturing method for making bipolar device having double polysilicon structure 失效
标题翻译：制造具有双重多晶硅结构的双极器件的制造方法
公开(公告)号：US5856228A
公开(公告)日：1999-01-05
申请号：US757335
申请日：1996-11-27
申请人： Hiroyuki Miwa , Shigeru Kanematsu , Takayuki Gomi , Hiroaki Anmo , Takashi Noguchi , Katsuyuki Kato , Hirokazu Ejiri , Norikazu Ouchi
发明人： Hiroyuki Miwa , Shigeru Kanematsu , Takayuki Gomi , Hiroaki Anmo , Takashi Noguchi , Katsuyuki Kato , Hirokazu Ejiri , Norikazu Ouchi
IPC分类号： H01L21/331 , H01L29/732
CPC分类号： H01L29/7322 , H01L29/66272 , Y10S148/01 , Y10S148/011
摘要： A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.
摘要翻译：一种半导体器件及其制造方法，其可以通过减小基极宽度同时实现基极通过时间的减少，并且通过降低基极电阻降低基极电阻。半导体器件通过包括以下步骤的方法制造：在半导体衬底中形成第一导电类型的第一杂质扩散层; 形成连接到第一杂质扩散层的导电膜; 在导电膜上形成第一绝缘膜; 通过由第一绝缘膜和导电膜构成的层压膜形成第一孔; 在暴露于第一孔的半导体衬底中形成第一导电类型的第二杂质扩散层; 从所述第一孔中的第二绝缘膜形成侧壁以形成第二孔; 以及在暴露于第二孔的半导体衬底中形成第一导电类型的第三杂质扩散层。

2. 发明授权

US5643806A Manufacturing method for making bipolar device 失效
标题翻译：制造双极器件的方法
公开(公告)号：US5643806A
公开(公告)日：1997-07-01
申请号：US472869
申请日：1995-06-07
申请人： Hiroyuki Miwa , Shigeru Kanematsu , Takayuki Gomi , Hiroaki Anmo , Takashi Noguchi , Katsuyuki Kato , Hirokazu Ejiri , Norikazu Ouchi
发明人： Hiroyuki Miwa , Shigeru Kanematsu , Takayuki Gomi , Hiroaki Anmo , Takashi Noguchi , Katsuyuki Kato , Hirokazu Ejiri , Norikazu Ouchi
IPC分类号： H01L21/331 , H01L29/732 , H01L21/265
CPC分类号： H01L29/7322 , H01L29/66272 , Y10S148/01 , Y10S148/011
摘要： A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.
摘要翻译：一种半导体器件及其制造方法，其可以通过减小基极宽度同时实现基极通过时间的减少，并且通过降低基极电阻降低基极电阻。半导体器件通过包括以下步骤的方法制造：在半导体衬底中形成第一导电类型的第一杂质扩散层; 形成连接到第一杂质扩散层的导电膜; 在导电膜上形成第一绝缘膜; 通过由第一绝缘膜和导电膜构成的层压膜形成第一孔; 在暴露于第一孔的半导体衬底中形成第一导电类型的第二杂质扩散层; 从所述第一孔中的第二绝缘膜形成侧壁以形成第二孔; 以及在暴露于第二孔的半导体衬底中形成第一导电类型的第三杂质扩散层。

3. 发明授权

US5541124A Method for making bipolar transistor having double polysilicon structure 失效
标题翻译：制造具有双重多晶硅结构的双极晶体管的方法
公开(公告)号：US5541124A
公开(公告)日：1996-07-30
申请号：US477471
申请日：1995-06-07
申请人： Hiroyuki Miwa , Shigeru Kanematsu , Takayuki Gomi , Hiroaki Anmo , Takashi Noguchi , Katsuyuki Kato , Hirokazu Ejiri , Norikazu Ouchi
发明人： Hiroyuki Miwa , Shigeru Kanematsu , Takayuki Gomi , Hiroaki Anmo , Takashi Noguchi , Katsuyuki Kato , Hirokazu Ejiri , Norikazu Ouchi
IPC分类号： H01L21/331 , H01L29/732 , H01L21/265
CPC分类号： H01L29/7322 , H01L29/66272 , Y10S148/01 , Y10S148/011
摘要： A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.
摘要翻译：一种半导体器件及其制造方法，其可以通过减小基极宽度同时实现基极通过时间的减少，并且通过降低基极电阻降低基极电阻。半导体器件通过包括以下步骤的方法制造：在半导体衬底中形成第一导电类型的第一杂质扩散层; 形成连接到第一杂质扩散层的导电膜; 在导电膜上形成第一绝缘膜; 通过由第一绝缘膜和导电膜构成的层压膜形成第一孔; 在暴露于第一孔的半导体衬底中形成第一导电类型的第二杂质扩散层; 从所述第一孔中的第二绝缘膜形成侧壁以形成第二孔; 以及在暴露于第二孔的半导体衬底中形成第一导电类型的第三杂质扩散层。

4. 发明授权

US5163178A Semiconductor device having enhanced impurity concentration profile 失效
标题翻译：具有增强浓度浓度特性的半导体器件
公开(公告)号：US5163178A
公开(公告)日：1992-11-10
申请号：US634454
申请日：1990-12-27
申请人： Takayuki Gomi , Minoru Nakamura , Hiroaki Anmo , Norikazu Chuchi , Hiroyuki Miwa , Akio Kayanuma , Koji Kobayashi
发明人： Takayuki Gomi , Minoru Nakamura , Hiroaki Anmo , Norikazu Chuchi , Hiroyuki Miwa , Akio Kayanuma , Koji Kobayashi
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L21/8224 , H01L27/06 , H01L29/08 , H01L29/732 , H01L29/735
CPC分类号： H01L29/6625 , H01L21/8222 , H01L21/8224 , H01L29/735
摘要： A semiconductor device comprises a semiconductor substrate provided with a collector region a base region and an emitter region in a lateral arrangement. Respective portions having peak impurity concentrations of the collector region and the emitter region are formed within the semiconductor substrate. A method of fabricating a semiconductor device comprises a step of forming a collector region of a second conduction type and an emitter region of a second conduction type in a lateral arrangement in a semiconductor substrate serving as a base region of a first conduction type by using a first mask provided with a pair of openings, and a step of forming heavily doped regions of the second conduction type so as to be connected respectively to the collector region and the emitter region by using a second mask provided with a pair of openings separated from each other by a distance greater than the distance between the openings of the first mask.

5. 发明授权

US5641692A Method for producing a Bi-MOS device 失效
标题翻译： Bi-MOS器件的制造方法
公开(公告)号：US5641692A
公开(公告)日：1997-06-24
申请号：US574363
申请日：1995-12-18
申请人： Hiroyuki Miwa , Hiroaki Anmo
发明人： Hiroyuki Miwa , Hiroaki Anmo
IPC分类号： H01L29/73 , H01L21/331 , H01L21/76 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L21/265
CPC分类号： H01L21/8249 , Y10S148/009
摘要： A method for producing a semiconductor device which decrease the number of processes at the time of producing BiCMOSLSI than the usual. Impurities are introduced into a semiconductor substrate under a second insulating film and a first electric conductive film utilizing a first insulating film and the first conductive film formed on the semiconductor substrate as masks. Therefore, it is able to perform concurrent introduction of impurities into the gate electrode, the source and the drain of the MOSFET, the base electrode of the bipolar transistor, the emitter and the collector contact of the lateral bipolar transistor, the outlet electrode of the capacitor, and the resistor, so that the number of process steps can be reduced.
摘要翻译：一种半导体器件的制造方法，其减少生产BiCMOSLSI时的处理次数。杂质在第二绝缘膜和第一导电膜的第二绝缘膜之下引入到半导体衬底中，并且第一导电膜利用第一绝缘膜和形成在半导体衬底上的第一导电膜作为掩模。因此，能够同时引入杂质到栅电极，MOSFET的源极和漏极，双极晶体管的基极，横向双极晶体管的发射极和集电极接触，电容器和电阻器，从而可以减少工艺步骤的数量。

6. 发明授权

US5324672A Manufacturing method for bipolar transistor 失效
标题翻译：双极晶体管的制造方法
公开(公告)号：US5324672A
公开(公告)日：1994-06-28
申请号：US966085
申请日：1992-10-23
申请人： Hiroaki Anmo , Hiroyuki Miwa
发明人： Hiroaki Anmo , Hiroyuki Miwa
IPC分类号： H01L21/331 , H01L21/8249 , H01L29/732 , H01L21/265 , H01L29/70
CPC分类号： H01L29/66272 , H01L21/8249 , H01L29/732 , Y10S148/01
摘要： A bipolar transistor including a semiconductor layer formed on a semiconductor substrate; a base region formed at an upper portion of the semiconductor layer; a graft base region formed at the upper portion of the semiconductor layer so as to connect with a periphery of the base region; an emitter region formed at an upper portion of the base region; an offset insulating film formed on the base region around the emitter region; a collector buried region formed in the semiconductor layer below the base region; a collector drawn region formed in the semiconductor layer so as to connect with the collector buried region and be arranged on the side of the base region adjacent to an element isolating region; an emitter electrode formed on the offset insulating film so as to connect with the emitter region; an emitter insulating film formed so as to cover the emitter electrode; a base electrode formed so as to connect with the graft base region and contact with the emitter insulating film; and a collector electrode formed so as to connect with the collector drawn region.
摘要翻译：一种双极晶体管，包括形成在半导体衬底上的半导体层; 形成在所述半导体层的上部的基极区域; 形成在所述半导体层的上部以与所述基底区域的周边连接的移植物基底区域; 形成在所述基极区域的上部的发射极区域; 形成在发射极区域周围的基极区域上的偏移绝缘膜; 集电极掩埋区域，形成在所述基极区域下方的所述半导体层中; 集电极引出区域，形成在所述半导体层中，以与所述集电极掩埋区域连接并且布置在所述基极区域与元件隔离区域相邻的一侧; 形成在所述偏移绝缘膜上以与所述发射极区域连接的发射电极; 形成为覆盖发射极的发射极绝缘膜; 形成为与移植物基底区域连接并与发射极绝缘膜接触的基极; 以及与集电极引出区域连接而形成的集电极。

7. 发明授权

US5055905A Semiconductor device 失效
公开(公告)号：US5055905A
公开(公告)日：1991-10-08
申请号：US599869
申请日：1990-10-19
申请人： Hiroaki Anmo
发明人： Hiroaki Anmo
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8249 , H01L27/06 , H01L29/94
CPC分类号： H01L27/0629 , H01L29/94
摘要： A semiconductor device with a capacitive element of an MIS structure comprising an electrode lead segment and an MIS segment in which an electrode is formed through a dielectric layer on an impurity region over to an aperture in a field insulator film. A high-concentration impurity region which connects the impurity region of the MIS segment to the electrode lead region of the electrode lead segment is formed only in the junction between the impurity region and the electrode lead region. The parasitic capacitance between the capacitive element and the semiconductor substrate is reduced without increasing the parasitic resistance so as to consequently achieve high precision in forming the capacitive element.

8. 发明授权

US5101258A Semiconductor integrated circuit device of master slice approach 失效
标题翻译：半导体集成电路主要方法的设备
公开(公告)号：US5101258A
公开(公告)日：1992-03-31
申请号：US476606
申请日：1990-02-07
申请人： Shigeru Moriuchi , Masashi Takeda , Takayuki Mogi , Hiroaki Anmo
发明人： Shigeru Moriuchi , Masashi Takeda , Takayuki Mogi , Hiroaki Anmo
IPC分类号： H01L27/118
CPC分类号： H01L27/11801 , H01L27/11896
摘要： In a semiconductor integrated circuit device of master slice approach according to this invention, regions on basic elements which are not used and isolation areas serve as wiring regions. Resistive elements are formed on the regions on the basic elements which are not used and the isolation areas. A high integration level can be obtained, circuit layout can be facilitated, and versatility of circuit design can be improved.

9. 发明授权

US5665615A Method of making BiCMOS semiconductor device 失效
标题翻译：制造BiCMOS半导体器件的方法
公开(公告)号：US5665615A
公开(公告)日：1997-09-09
申请号：US600539
申请日：1996-02-13
申请人： Hiroaki Anmo
发明人： Hiroaki Anmo
IPC分类号： H01L29/70 , H01L21/33 , H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L21/265
CPC分类号： H01L27/0623 , H01L21/8249
摘要： A BiCMOS semiconductor device comprising a substrate, a vertical bipolar transistor provided on the substrate and having a first conductive base terminal electrode formed in a portion of a first semiconductor film provided on the substrate, a second conductive semiconductor terminal electrode formed in a second semiconductor film provided through an insulating layer on the first semiconductor film, the first and second conductive electrodes being disposed such that portions thereof overlap each other, and an LDD (lightly doped drain)-type MOS transistor provided on the substrate and having a gate electrode formed in a portion of said first semiconductor film and a gate side wall formed on a side wall of said gate electrode, wherein the insulating layer is caused to exist selectively in a region in which the first and second conductive electrodes are overlapped, and constitutes at least a portion of the gate side wall.
摘要翻译：一种BiCMOS半导体器件，包括衬底，设置在衬底上的垂直双极晶体管，并且具有形成在设置在衬底上的第一半导体膜的一部分中的第一导电基极端子电极，形成在第二半导体膜中的第二导电半导体端子电极通过所述第一半导体膜上的绝缘层提供，所述第一和第二导电电极被布置成使得其部分彼此重叠，以及设置在所述基板上并具有栅电极的LDD（轻掺杂漏极）型MOS晶体管所述第一半导体膜的一部分和形成在所述栅电极的侧壁上的栅极侧壁，其中所述绝缘层选择性地存在于所述第一和第二导电电极重叠的区域中，并且至少构成门侧壁的一部分。

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