专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5761728A Asynchronous access system controlling processing modules making requests to a shared system memory 失效
标题翻译：控制处理模块的异步访问系统向共享系统存储器发出请求
公开(公告)号：US5761728A
公开(公告)日：1998-06-02
申请号：US777184
申请日：1996-12-27
申请人： Hiroshi Saito , Takatsugu Sasaki , Hirohide Sugahara , Akira Kabemoto , Hajime Takahashi , Jun Funaki
发明人： Hiroshi Saito , Takatsugu Sasaki , Hirohide Sugahara , Akira Kabemoto , Hajime Takahashi , Jun Funaki
IPC分类号： G06F12/00 , G06F13/16 , G06F15/16 , G06F9/38
CPC分类号： G06F13/1673
摘要： An asynchronous access system for a computer system includes processing modules performing processes, at least one shared system memory module, and a system bus connecting the processing modules and the shared system memory module. Each of the processing modules includes a processor, a plurality of buffers coupled to the processor and to the system bus, and a controlling unit for writing data from the plurality of processors into the shared system memory module. Data is written into the shared system memory module by a processor generating write instructions to write data via the plurality of buffers and the system bus. The controlling unit controls the writing such that one writing instruction writes data into a plurality of buffers, then transfers the data to the shared system memory module via the system bus, with another writing instruction writing additional data into another plurality of buffers and transferring the additional data to the shared system memory module.
摘要翻译：用于计算机系统的异步访问系统包括执行处理的处理模块，至少一个共享系统存储器模块以及连接处理模块和共享系统存储器模块的系统总线。每个处理模块包括处理器，耦合到处理器和系统总线的多个缓冲器，以及用于将数据从多个处理器写入共享系统存储器模块的控制单元。通过处理器将数据写入共享系统存储器模块，该处理器产生写入指令以经由多个缓冲器和系统总线写入数据。控制单元控制写入，使得一个写入指令将数据写入多个缓冲器，然后经由系统总线将数据传送到共享系统存储器模块，另一个写入指令将另外的数据写入另一个多个缓冲器并传送附加的数据数据到共享系统内存模块。

2. 发明授权

US5634037A Multiprocessor system having a shared memory with exclusive access for a requesting processor which is maintained until normal completion of a process and for retrying the process when not normally completed 失效
标题翻译：具有对请求处理器的独占访问的共享存储器的多处理器系统，其被维持直到进程正常完成并且当正常完成时重试该进程
公开(公告)号：US5634037A
公开(公告)日：1997-05-27
申请号：US200964
申请日：1994-02-24
申请人： Takatsugu Sasaki , Akira Kabemoto , Hirohide Sugahara , Hajime Takahashi
发明人： Takatsugu Sasaki , Akira Kabemoto , Hirohide Sugahara , Hajime Takahashi
IPC分类号： G06F12/00 , G06F9/46 , G06F9/52 , G06F13/00 , G06F15/16 , G06F15/177
CPC分类号： G06F9/52
摘要： An exclusive control system is provided in a system having a memory module and a plurality of processing modules sharing the memory module, each of the plurality of processing modules exclusively accessing the memory module while prohibiting other processing modules from accessing the memory module. The exclusive control system includes a determination unit for determining whether or not a process executed in response to an access request from a processor module among the plurality of processing modules is normally completed in the memory module, and a retry unit for, when the determination unit determines that the process executed in response to the access request is not normally completed, retrying the process while maintaining a state in which other processing modules are prohibited from accessing the memory module.
摘要翻译：在具有共享存储器模块的存储器模块和多个处理模块的系统中提供排他控制系统，所述多个处理模块中的每一个处理模块独占地访问存储器模块，同时禁止其他处理模块访问存储器模块。排他控制系统包括确定单元，用于确定在多个处理模块中的来自处理器模块的访问请求执行的处理是否在存储器模块中正常完成;以及重试单元，用于当确定单元确定响应于访问请求而执行的处理未正常完成，在保持禁止其他处理模块访问存储器模块的状态的同时重试该过程。

3. 发明授权

US6092173A Multiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data transfer system, data transfer system, and bus control method for data transfer system 失效
公开(公告)号：US6092173A
公开(公告)日：2000-07-18
申请号：US824871
申请日：1997-03-26
申请人： Takatsugu Sasaki , Akira Kabemoto , Hirohide Sugahara , Junji Nishioka , Yozo Nakayama , Jun Sakurai , Toshiyuki Muta , Takayuki Shimamura
发明人： Takatsugu Sasaki , Akira Kabemoto , Hirohide Sugahara , Junji Nishioka , Yozo Nakayama , Jun Sakurai , Toshiyuki Muta , Takayuki Shimamura
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0813 , G06F12/0808
摘要： A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

4. 发明授权

US5890217A Coherence apparatus for cache of multiprocessor 失效
标题翻译：多处理器缓存的一致性设备
公开(公告)号：US5890217A
公开(公告)日：1999-03-30
申请号：US598243
申请日：1996-02-07
申请人： Akira Kabemoto , Naohiro Shibata , Toshiyuki Muta , Takayuki Shimamura , Hirohide Sugahara , Junji Nishioka , Takatsugu Sasaki , Satoshi Shinohara , Yozo Nakayama , Jun Sakurai , Hiroaki Ishihata , Takeshi Horie , Toshiyuki Shimizu
发明人： Akira Kabemoto , Naohiro Shibata , Toshiyuki Muta , Takayuki Shimamura , Hirohide Sugahara , Junji Nishioka , Takatsugu Sasaki , Satoshi Shinohara , Yozo Nakayama , Jun Sakurai , Hiroaki Ishihata , Takeshi Horie , Toshiyuki Shimizu
IPC分类号： G06F12/08 , G06F15/17 , G06F13/00
CPC分类号： G06F12/0817 , G06F12/0831 , G06F2212/2542
摘要： A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.
摘要翻译：多个处理器，每个处理器具有为多个处理器模块提供的高速缓存和其中分配和布置主存储器的本地存储器通过内部监听总线相互连接。处理器模块通过第二系统总线相互连接。通过使用两个单独的总线，处理器组内的高速缓存一致性操作与处理器组之外的高速缓存一致性操作保持分开。

5. 发明授权

US6038674A Multiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data transfer system, data transfer system, and bus control method for data transfer system 有权
标题翻译：数据传输系统中的多处理器，多处理器，发送和接收器的多处理器，存储器访问方法，数据传输系统和数据传输系统的总线控制方法
公开(公告)号：US6038674A
公开(公告)日：2000-03-14
申请号：US352343
申请日：1999-07-13
申请人： Takatsugu Sasaki , Akira Kabemoto , Hirohide Sugahara , Junji Nishioka , Satoshi Shinohara , Yozo Nakayama , Jun Sakurai , Naohiro Shibata , Toshiyuki Muta , Takayuki Shimamura
发明人： Takatsugu Sasaki , Akira Kabemoto , Hirohide Sugahara , Junji Nishioka , Satoshi Shinohara , Yozo Nakayama , Jun Sakurai , Naohiro Shibata , Toshiyuki Muta , Takayuki Shimamura
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0813 , G06F12/0808
摘要： A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.
摘要翻译：多处理器，其中多个处理器经由系统总线连接。多处理器包括每个具有至少一个处理器，主存储器，高速缓冲存储器，高速缓存控制单元，目录存储器和目录控制单元的处理器组。目录控制单元包括无效命令发布单元，其向存储在高速缓存行中的目录存储器中的所有参考指定发出高速缓存行无效命令。因此，可以通过减少从缓存存储器发出高速缓存无效命令的频率来缩短设备处理时间。

6. 发明授权

US5727151A Message control system specifying message storage buffer for data communication system with general purpose and arbitrary form buffers 失效
标题翻译：消息控制系统指定用于具有通用和任意形式缓冲区的数据通信系统的消息存储缓冲器
公开(公告)号：US5727151A
公开(公告)日：1998-03-10
申请号：US859397
申请日：1992-05-28
申请人： Hirohide Sugahara , Hajime Takahashi , Akira Kabemoto , Hideki Nakagawa
发明人： Hirohide Sugahara , Hajime Takahashi , Akira Kabemoto , Hideki Nakagawa
IPC分类号： G06F13/362 , G06F15/17 , G06F15/163
CPC分类号： G06F13/362 , G06F15/17
摘要： A message control system is for a data communication system which takes the form of a loosely coupled multiprocessing system in which a plurality of processing modules respectively having a memory unit are coupled to each other via a system bus. In this message control system, a memory unit (13) within each processing module (10) includes a data processing part (14) which is a software running on a central processing unit (11) within its own processing module, and a buffer (16, 17) which stores a transmitting message. A connection unit (13) within each processing module (10) at least includes a plurality of logical transmitting ports (21) for successively reading out the message which is expanded in the buffer (16, 17) and transmits the same as a continuous message, a plurality of logical receiving ports (22) for storing the message, a transmission system connecting means (23), and a reception system connecting means (24).
摘要翻译： PCT No.PCT / JP91 / 01305 Sec。 371日期：1992年5月28日 102（e）日期1992年5月28日PCT 1991年9月27日PCT公布。出版物WO92 / 06435 日期1992年04月16日消息控制系统用于采用松散耦合的多处理系统形式的数据通信系统，其中分别具有存储器单元的多个处理模块经由系统总线相互耦合。在该消息控制系统中，每个处理模块（10）内的存储单元（13）包括数据处理部分（14），该数据处理部分是在其自己的处理模块内的中央处理单元（11）上运行的软件，以及缓冲器 16,17），其存储发送消息。每个处理模块（10）内的连接单元（13）至少包括多个逻辑发送端口（21），用于连续地读出在缓冲器（16,17）中扩展的消息，并将其作为连续消息发送，用于存储消息的多个逻辑接收端口（22），传输系统连接装置（23）和接收系统连接装置（24）。

7. 发明授权

US5592624A Data communication for controlling message transmission and reception among processing modules using information stored in descriptor to form a loosely coupled multiprocessing system 失效
标题翻译：数据通信，用于使用存储在描述符中的信息来控制处理模块之间的消息发送和接收，以形成松散耦合的多处理系统
公开(公告)号：US5592624A
公开(公告)日：1997-01-07
申请号：US859318
申请日：1992-05-28
申请人： Hajime Takahashi , Hirohide Sugahara , Akira Kabemoto
发明人： Hajime Takahashi , Hirohide Sugahara , Akira Kabemoto
IPC分类号： G06F15/17 , G06F13/00 , G06F13/14
CPC分类号： G06F15/17
摘要： A message control system for a data communication system in the form of a loosely coupled multiprocessing system, in which a plurality of processing modules having a memory unit are coupled to each other via a system bus. In this message control system, a memory unit, within each processing module, includes a data processing part which is in software running on a central processing unit within its own processing module, a descriptor which manages address and data length information of a storage region for a message in the form of a chain, and a buffer which decomposes and stores a transmitting message. A connection unit within each processing module includes logical transmitting ports and a logical receiving port.
摘要翻译： PCT No.PCT / JP91 / 01306 Sec。 371日期：1992年5月28日 102（e）日期1992年5月28日PCT 1991年9月27日PCT公布。出版物WO92 / 06430 日期1992年04月16日用于松散耦合的多处理系统形式的数据通信系统的消息控制系统，其中具有存储器单元的多个处理模块经由系统总线相互耦合。在该消息控制系统中，每个处理模块内的存储器单元包括在其自身的处理模块内的中央处理单元上运行的软件的数据处理部，管理存储区域的地址和数据长度信息的描述符，以链的形式的消息，以及分解和存储发送消息的缓冲器。每个处理模块内的连接单元包括逻辑发送端口和逻辑接收端口。

8. 发明授权

US5737573A Asynchronous access system having an internal buffer control circuit which invalidates an internal buffer 失效
标题翻译：具有使内部缓冲器无效的内部缓冲器控制电路的异步访问系统
公开(公告)号：US5737573A
公开(公告)日：1998-04-07
申请号：US733721
申请日：1996-10-16
申请人： Jun Funaki , Akira Kabemoto , Hirohide Sugahara
发明人： Jun Funaki , Akira Kabemoto , Hirohide Sugahara
IPC分类号： G06F15/16 , G06F12/00 , G06F12/08 , G06F12/16 , G06F13/36 , G06F15/177 , G06F12/12
CPC分类号： G06F12/0815
摘要： An asynchronous access system includes a system bus, at least one processing module provided with a main memory, a central processing unit and a first connection unit which connects to the system bus, and at least one shared memory module provided with a shared memory unit and a second connection unit which connects to the system bus. The first connection unit within the processing module makes a block read request to the shared memory module via the system bus when the first connection unit recognizes a read from the shared memory module requested from the central processing unit. The first connection unit within the processing module comprises an internal bus, an internal buffer storing data read from the shared memory module, a system bus control circuit coupled to the system bus, an internal bus control circuit coupled to the central processing unit via the internal bus, and an internal buffer control circuit controlling write/read of the internal buffer based on a signal from the internal bus control circuit. One of the internal buffer control circuit and the internal bus control circuit invalidates a content of the internal buffer when one of a plurality of invalidating conditions is satisfied.
摘要翻译：异步访问系统包括系统总线，至少一个具有主存储器的处理模块，中央处理单元和连接到系统总线的第一连接单元，以及至少一个设有共享存储单元的共享存储器模块，连接到系统总线的第二连接单元。当第一连接单元识别从中央处理单元请求的共享存储器模块的读取时，处理模块内的第一连接单元经由系统总线向共享存储器模块发送块读请求。处理模块内的第一连接单元包括内部总线，存储从共享存储器模块读取的数据的内部缓冲器，耦合到系统总线的系统总线控制电路，经由内部耦合到中央处理单元的内部总线控制电路总线和内部缓冲器控制电路，其基于来自内部总线控制电路的信号来控制内部缓冲器的写入/读取。当满足多个无效条件中的一个时，内部缓冲器控制电路和内部总线控制电路之一使内部缓冲器的内容无效。

9. 发明授权

US5708795A Asynchronous access system for multiprocessor system and processor module used in the asynchronous access system 失效
标题翻译：用于异步访问系统的多处理器系统和处理器模块的异步访问系统
公开(公告)号：US5708795A
公开(公告)日：1998-01-13
申请号：US188774
申请日：1994-01-31
申请人： Jun Funaki , Akira Kabemoto , Hirohide Sugahara
发明人： Jun Funaki , Akira Kabemoto , Hirohide Sugahara
IPC分类号： G06F12/06 , G06F12/00 , G06F13/16 , G06F15/16 , G06F15/167 , G06F13/14
CPC分类号： G06F15/167 , G06F13/1673
摘要： In an asynchronous access system for a multiprocessor system having a plurality of processor modules connected to a system bus and at least one shared memory module connected to the system bus, each of the processor modules includes a processor and an internal buffer. The processor writes data into the internal buffer, and the data is read from the internal buffer and is written into the shared memory via the system bus. The asynchronous access system includes a first unit, provided in each of the processor modules, for detecting a predetermined situation regarding a data write from the processor to the shared memory, and a second unit, provided in each of the processor modules, for causing the data stored in the internal buffer to be written into the shared memory module when the first unit detects the predetermined situation.
摘要翻译：在具有连接到系统总线的多个处理器模块和连接到系统总线的至少一个共享存储器模块的多处理器系统的异步访问系统中，每个处理器模块包括处理器和内部缓冲器。处理器将数据写入内部缓冲区，数据从内部缓冲区读取，并通过系统总线写入共享存储器。异步访问系统包括设置在每个处理器模块中的用于检测关于从处理器到共享存储器的数据写入的预定情况的第一单元，以及设置在每个处理器模块中的第二单元，用于使当第一单元检测到预定情况时，存储在内部缓冲器中的数据被写入共享存储器模块。

10. 发明授权

US06799219B1 Method and apparatus for avoiding starvation in computer network 有权
标题翻译：避免计算机网络中的饥饿的方法和装置
公开(公告)号：US06799219B1
公开(公告)日：2004-09-28
申请号：US09653154
申请日：2000-08-31
申请人： Hirohide Sugahara , Takashi Miyoshi , Takeshi Horie , Jeffrey D. Larson
发明人： Hirohide Sugahara , Takashi Miyoshi , Takeshi Horie , Jeffrey D. Larson
IPC分类号： G06F1516
CPC分类号： H04L47/15 , H04L47/70 , H04L47/745 , H04L47/821 , H04L47/826
摘要： A method and apparatus for avoiding starvation at an initiator node in a computer network to which are connected at least one target node which provides service and a plurality of initiator nodes which request service from the target node. The method includes: when a request is received from the initiator node during a period that the target node is unable to provide service, returning a reject reply by attaching thereto reject time information that matches the period; when the target node is in a state capable of providing service, preferentially accepting a retry request carrying older reject time information; and when the target node is in the state capable of providing service, returning a reject reply by attaching thereto new reject time information in response to any first request received before retry requests arising from previously rejected requests are all accepted.
摘要翻译：一种用于避免在计算机网络中的发起者节点处的饥饿的方法和装置，至少一个提供服务的目标节点和从目标节点请求服务的多个发起方节点连接到该节点。该方法包括：当在目标节点不能提供服务的时段期间从发起者节点接收到请求时，通过附加拒绝回复的拒绝时间信息返回拒绝回复; 当目标节点处于能够提供服务的状态时，优先地接收携带较早拒绝时间信息的重试请求; 并且当目标节点处于能够提供服务的状态时，响应于在先前拒绝的请求引起的重试请求之前接收到的任何第一请求全部被接受，通过附加到新的拒绝时间信息来返回拒绝答复。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式