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1. 发明申请

US20050069032A1 Analog equalizer 审中-公开
标题翻译：模拟均衡器
公开(公告)号：US20050069032A1
公开(公告)日：2005-03-31
申请号：US10947382
申请日：2004-09-23
申请人： Takashi Hirata , Toru Iwata , Noriaki Takeda
发明人： Takashi Hirata , Toru Iwata , Noriaki Takeda
IPC分类号： H03K5/00 , H03K5/13 , H03K5/159 , H03L7/06 , H03L7/081 , H04B1/12 , H04B3/04 , H04B7/005 , H04L25/03
CPC分类号： H03L7/06 , H03K5/133 , H03K2005/00026 , H03L7/0805 , H03L7/0812 , H04L25/03885
摘要： An analog equalizer includes a mixer and an analog delay circuit. The mixer mixes an input signal and a delayed signal output from the analog delay circuit to output a mixed signal. The analog delay circuit delays the mixed signal output from the mixer to output a delayed signal.
摘要翻译：模拟均衡器包括混频器和模拟延迟电路。混合器混合输入信号和从模拟延迟电路输出的延迟信号以输出混合信号。模拟延迟电路延迟从混频器输出的混合信号以输出延迟信号。

2. 发明申请

US20070183175A1 Charge pumping circuit 有权
标题翻译：充电泵电路
公开(公告)号：US20070183175A1
公开(公告)日：2007-08-09
申请号：US11637687
申请日：2006-12-13
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
IPC分类号： H02M7/00
CPC分类号： H02M3/07 , H03L7/0895 , H03L7/0896
摘要： A charge pumping circuit includes a first switch for controlling one of push and pull operations in accordance with a first control signal; a current mirror circuit constructed from transistors each having a different polarity from the first switch; a second switch for controlling current input to the current mirror circuit in accordance with a second control signal, the second switch being constructed from a transistor having the same characteristic as a transistor used for constructing the first switch; a first MOS capacitor one end of which is connected to an input side of the current mirror circuit; a second MOS capacitor receiving, at one end thereof, a current concerned with the push and pull operations; and a voltage buffer connected to the first and second MOS capacitors. The other of the push and pull operations is performed with an output current of the current mirror circuit.
摘要翻译：电荷泵浦电路包括：第一开关，用于根据第一控制信号控制推挽操作中的一个; 由与所述第一开关具有不同极性的晶体管构成的电流镜电路; 第二开关，用于根据第二控制信号控制到电流镜电路的电流输入，第二开关由具有与用于构造第一开关的晶体管相同的特性的晶体管构成; 第一MOS电容器，其一端连接到电流镜电路的输入侧; 在其一端接收与推挽操作有关的电流的第二MOS电容器; 以及连接到第一和第二MOS电容器的电压缓冲器。推挽操作中的另一个用电流镜电路的输出电流进行。

3. 发明授权

US06943595B2 Synchronization circuit 有权
标题翻译：同步电路
公开(公告)号：US06943595B2
公开(公告)日：2005-09-13
申请号：US10670510
申请日：2003-09-26
申请人： Hirokazu Sugimoto , Toru Iwata , Takashi Hirata
发明人： Hirokazu Sugimoto , Toru Iwata , Takashi Hirata
IPC分类号： H04L25/40 , H03K5/00 , H03K5/135 , H04L7/00 , H04L7/02 , H04L7/04 , H03L7/00
CPC分类号： H03K5/135 , H03K2005/00156 , H04L7/0008 , H04L7/02
摘要： A synchronization circuit includes a state detection circuit for outputting a control signal according to the temporal relationship between a transition point of an input signal and an edge of a synchronization clock, a delay selection circuit for adding a delay to the input signal based on the control signal, and a latch circuit for synchronizing the signal outputted from the delay selection circuit with the synchronization clock. Therefore, synchronization of the input signal can be carried out without adding latency to the input signal.
摘要翻译：同步电路包括：状态检测电路，用于根据输入信号的转变点和同步时钟的边沿之间的时间关系输出控制信号;延迟选择电路，用于根据控制信号向输入信号添加延迟信号和用于使从延迟选择电路输出的信号与同步时钟同步的锁存电路。因此，可以在不增加输入信号的延迟的情况下执行输入信号的同步。

4. 发明授权

US06208567B1 Semiconductor device capable of cutting off a leakage current in a defective array section 失效
标题翻译：能够切断缺陷阵列部分的漏电流的半导体装置
公开(公告)号：US06208567B1
公开(公告)日：2001-03-27
申请号：US09014775
申请日：1998-01-28
申请人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
发明人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
IPC分类号： G11C2900
CPC分类号： G01R31/3004 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.
摘要翻译：本发明的半导体器件包括：包括多个电路块的阵列部分; 泄漏电流切断部，切断在所述阵列部中的所述多个电路块中的至少一个电路中发生的漏电流; 以及控制部分，用于根据泄漏电流切断信息控制漏电流切断部分。

5. 发明授权

US07705645B2 Delay locked loop circuit 有权
标题翻译：延时锁定回路电路
公开(公告)号：US07705645B2
公开(公告)日：2010-04-27
申请号：US12033707
申请日：2008-02-19
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/07 , H03L7/0891 , H03L7/0895
摘要： A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.
摘要翻译：延迟元件产生延迟的时钟信号，该时钟信号以基于参考时钟信号的上升（或下降）的延迟从基于环路滤波器的输出确定的延迟量转变。信号产生电路产生根据参考时钟信号的上升和下降以及延迟的时钟信号的转变而互补地变化的两个信号。电荷泵电路根据这两个信号执行环路滤波器，在从参考时钟信号的上升（或下降）延迟到延迟的时钟信号的转换的延迟期间进行推（或拉）（或推动）操作在从延迟的时钟信号的转变延迟到参考时钟信号的下降（或上升）的间隔期间。

6. 发明授权

US06944003B2 Semiconductor integrated circuit with voltage-detecting circuit and signal transmitting and receiving system 失效
标题翻译：具有电压检测电路和信号发射和接收系统的半导体集成电路
公开(公告)号：US06944003B2
公开(公告)日：2005-09-13
申请号：US10365527
申请日：2003-02-13
申请人： Hirokazu Sugimoto , Takashi Hirata , Hironori Akamatsu , Toru Iwata , Satoshi Takahashi
发明人： Hirokazu Sugimoto , Takashi Hirata , Hironori Akamatsu , Toru Iwata , Satoshi Takahashi
IPC分类号： G01R31/28 , H01L21/66 , H02H9/04 , H02H3/24
CPC分类号： H02H9/046
摘要： A first semiconductor integrated circuit is connected to a second semiconductor integrated circuit with a cable. In the first semiconductor integrated circuit, when a power supply voltage becomes less than a set voltage detection level, a voltage-detecting circuit outputs a voltage-detected signal to lower the voltage of the cable and to stop the operation. The second semiconductor integrated circuit detects the decrease in the voltage of the cable to recognize the halt of the operation of the first semiconductor integrated circuit. In the first semiconductor integrated circuit thus configured, in testing the operation under low-voltage conditions in which the power supply voltage is less than the set voltage detection level, the voltage-detecting circuit receives a control signal from an external terminal to stop the operation forcibly. Consequently, even when the power supply voltage is made lower than the set voltage-detecting level, the first semiconductor integrated circuit properly operates until the power supply voltage reaches a predetermined lower limit of operating voltage. Thus, evaluation of operation is possible under low-voltage conditions.
摘要翻译：第一半导体集成电路通过电缆连接到第二半导体集成电路。在第一半导体集成电路中，当电源电压变得小于设定电压检测电平时，电压检测电路输出电压检测信号来降低电缆的电压并停止工作。第二半导体集成电路检测电缆的电压的降低以识别第一半导体集成电路的操作停止。在这样配置的第一半导体集成电路中，在电源电压小于设定电压检测电平的低电压条件下进行测试时，电压检测电路从外部端子接收控制信号，停止动作强制。因此，即使电源电压低于设定电压检测电平，第一半导体集成电路也可以正常工作，直到电源电压达到预定的工作电压下限。因此，在低电压条件下可以进行运行评估。

7. 发明申请

US20050024084A1 Semiconductor integrated circuit and signal sending/receiving system 审中-公开
标题翻译：半导体集成电路和信号发送/接收系统
公开(公告)号：US20050024084A1
公开(公告)日：2005-02-03
申请号：US10855351
申请日：2004-05-28
申请人： Takashi Hirata , Toru Iwata
发明人： Takashi Hirata , Toru Iwata
IPC分类号： G05F1/56 , H04L25/02 , H03K19/003
CPC分类号： H04L25/0278 , G05F1/56 , H04L25/028 , H04L25/0292
摘要： A terminal resistor built in a signal-sending or signal-receiving semiconductor integrated circuit is composed of a parallel circuit of a polysilicon resistor element having excellent frequency characteristic and a P-type MOS transistor. The resistance value of the polysilicon resistor element is set so as to be an approximate value of the characteristic impedance of a transmission line to be connected. The gate voltage of the P-type MOS transistor is controlled by a gate bias voltage adjustment circuit. The resistance value of the P-type MOS transistor is variably adjusted. Variation in the resistance value of the polysilicon resistor element due to dispersion in its manufacturing process is absorbed by variably adjusting the resistance value of the P-type MOS transistor. The combined resistance value of the polysilicon resistor element and the P-type MOS transistor is adjusted with high precision just to the characteristic impedance of the transmission line. Thus, a signal-sending or signal-receiving semiconductor integrated circuit in which the terminal resistor having excellent frequency and DC characteristics is built can be obtained.
摘要翻译：内置在信号发送或信号接收半导体集成电路中的端子电阻由具有优异频率特性的多晶硅电阻元件和P型MOS晶体管的并联电路组成。将多晶硅电阻元件的电阻值设定为要连接的传输线的特性阻抗的近似值。 P型MOS晶体管的栅极电压由栅极偏置电压调节电路控制。可变地调节P型MOS晶体管的电阻值。通过可变地调节P型MOS晶体管的电阻值来吸收由于其制造过程中的分散而导致的多晶硅电阻元件的电阻值的变化。与传输线的特性阻抗相比，多晶硅电阻元件和P型MOS晶体管的组合电阻值被高精度地调整。因此，可以获得其中构建具有优异的频率和DC特性的端子电阻器的信号发送或信号接收半导体集成电路。

8. 发明授权

US06794912B2 Multi-phase clock transmission circuit and method 失效
标题翻译：多相时钟传输电路及方法
公开(公告)号：US06794912B2
公开(公告)日：2004-09-21
申请号：US10361610
申请日：2003-02-11
申请人： Takashi Hirata , Toru Iwata
发明人： Takashi Hirata , Toru Iwata
IPC分类号： H03D324
CPC分类号： H03L7/0805 , H03K5/133 , H03K5/1504 , H03L7/07 , H03L7/08 , H03L7/0812 , H03L7/0814
摘要： A multi-phase clock transmission circuit includes: a clock generator for generating a clock synchronizing with a reference clock and a control signal responsive to the phase difference between the reference clock and the generated clock; and a delay circuit for generating a multi-phase clock based on the clock and the control signal. The clock generator generates a signal having a frequency equal to an integral multiple of the frequency of the reference clock and outputs the signal as the clock. The delay circuit has a circuit receiving the clock and including a plurality of delay elements in cascade connection each giving a delay according to the control signal to an input signal. Signals output from the plurality of delay elements are used as signals constituting the multi-phase clock.
摘要翻译：多相时钟传输电路包括：时钟发生器，用于响应于参考时钟和所产生的时钟之间的相位差，产生与参考时钟同步的时钟和控制信号; 以及用于基于时钟和控制信号产生多相时钟的延迟电路。时钟发生器产生具有等于参考时钟的频率的整数倍的频率的信号，并将该信号作为时钟输出。延迟电路具有接收时钟并且包括多个级联连接的延迟元件的电路，每个延迟元件根据与输入信号的控制信号给出延迟。将从多个延迟元件输出的信号用作构成多相时钟的信号。

9. 发明授权

US06201412B1 Semiconductor integrated circuit with driver stabilization using parasitic capacitance 失效
标题翻译：具有驱动器稳定的半导体集成电路使用寄生电容
公开(公告)号：US06201412B1
公开(公告)日：2001-03-13
申请号：US09123902
申请日：1998-07-28
申请人： Toru Iwata , Hironori Akamatsu , Takashi Hirata
发明人： Toru Iwata , Hironori Akamatsu , Takashi Hirata
IPC分类号： H03K190175
CPC分类号： H03K19/01707
摘要： The semiconductor integrated circuit of this invention includes: a driver including a MOS transistor for driving a load; and a stabilizer for stabilizing a change in a voltage at a source of the MOS transistor due to a gate-source parasitic capacitance of the MOS transistor.
摘要翻译：本发明的半导体集成电路包括：驱动器，其包括用于驱动负载的MOS晶体管; 以及用于稳定由于MOS晶体管的栅极 - 源极寄生电容而在MOS晶体管的源极处的电压变化的稳定器。

10. 发明授权

US6073245A Skewing-suppressive output buffer circuit 有权
标题翻译：偏移抑制输出缓冲电路
公开(公告)号：US6073245A
公开(公告)日：2000-06-06
申请号：US234708
申请日：1999-01-21
申请人： Takashi Hirata , Toru Iwata
发明人： Takashi Hirata , Toru Iwata
IPC分类号： G06F5/06 , G06F1/12
CPC分类号： G06F5/06
摘要： In an output buffer circuit, an input signal is transmitted through a bus by way of a latch circuit and a driver. A stable-state interval detector detects an interval during which the input signal remains in the same logical state. If the stable-state interval detected is relatively short, a drivability controller controls the drivability of the driver at a normal value. To the contrary, if the interval detected is relatively long, the controller increases the drivability of the driver. In general, if the stable-state interval of an input signal is relatively long, then the time taken for the subsequent logical state transition of the signal tends to be longer as compared with a signal having a shorter stable-state interval. However, if the drivability of the driver is increased, then the state transition time is shortened, and substantially equalized with that of a signal having a relatively short stable-state interval. As a result, signal skewing can be minimized.
摘要翻译：在输出缓冲电路中，输入信号通过一个总线通过一个锁存电路和一个驱动器传输。稳态区间检测器检测输入信号保持在相同逻辑状态的间隔。如果检测到的稳态间隔相对较短，则驾驶员控制器将驾驶员的驾驶性能控制在正常值。相反，如果检测到的间隔相对较长，则控制器增加驾驶员的驾驶性能。一般来说，如果输入信号的稳态间隔相对较长，则与具有较短稳态间隔的信号相比，信号的后续逻辑状态转换所花费的时间趋于变长。然而，如果驾驶员的驾驶性能增加，则状态转移时间缩短，并且与具有相对较短的稳态间隔的信号基本相等。结果，信号偏移可以最小化。

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