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1. 发明授权

US06246627B1 Semiconductor device capable of cutting off a leakage current in a defective array section and method thereof 有权
标题翻译：能够切断缺陷阵列部分的漏电流的半导体装置及其方法
公开(公告)号：US06246627B1
公开(公告)日：2001-06-12
申请号：US09397239
申请日：1999-09-16
申请人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
发明人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
IPC分类号： G11C514
CPC分类号： G01R31/3004 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.
摘要翻译：本发明的半导体器件包括：包括多个电路块的阵列部分; 泄漏电流切断部，切断在所述阵列部中的所述多个电路块中的至少一个电路中发生的漏电流; 以及控制部分，用于根据泄漏电流切断信息控制漏电流切断部分。

2. 发明授权

US6145065A Memory access buffer and reordering apparatus using priorities 失效
标题翻译：使用优先级的存储器访问缓冲器和重新排序装置
公开(公告)号：US6145065A
公开(公告)日：2000-11-07
申请号：US67899
申请日：1998-04-29
申请人： Satoshi Takahashi , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Yutaka Terada , Takashi Hirata
发明人： Satoshi Takahashi , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Yutaka Terada , Takashi Hirata
IPC分类号： G06F13/16 , G06F12/02
CPC分类号： G06F13/1631
摘要： A current problem is that when a DRAM is to be accessed through a data bus, the DRAM is accessed independently of a bank, a row address, etc., and therefore, is inefficient. To solve this problem, an address bus and a data bus are connected to a main memory part independently of each other, a temporary memory part for holding a plurality of addresses in advance is disposed on the address bus side and holds addresses for every access to the main memory part regardless of transfer of data, thereby pipelining address inputting cycles. Further, for the purpose of an effective operation of the main memory part, using the addresses which are held, the addresses are rearranged in such a manner that addresses with the same row addresses become continuous to each other, or when there are not addresses with the same row addresses, addresses different banks from each other become continuous to each other, and the memory is thereafter accessed. This reduces the number of precharges, shortens a standby period which is necessary for a precharge, and realizes accessing while reducing a wasteful use of time.
摘要翻译：目前的问题在于，当通过数据总线访问DRAM时，独立于存储体，行地址等访问DRAM，因此是低效的。为了解决这个问题，地址总线和数据总线彼此独立地连接到主存储器部分，预先存储多个地址的临时存储器部分设置在地址总线侧，并且保存地址以进行每次访问主存储部分不管数据传输，从而流水线地址输入周期。此外，为了主存储器部分的有效操作，使用所保存的地址，地址被重新排列，使得具有相同行地址的地址彼此连续，或者当没有地址与相同的行地址，彼此不同的存储体彼此变得连续，并且此后访问存储器。这减少了预充电次数，缩短了预充电所需的待机时间，并实现了访问，同时减少了浪费时间的使用。

3. 发明授权

US6009024A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US6009024A
公开(公告)日：1999-12-28
申请号：US46880
申请日：1998-03-24
申请人： Takashi Hirata , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Satoshi Takahashi , Yutaka Terada
发明人： Takashi Hirata , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Satoshi Takahashi , Yutaka Terada
IPC分类号： G11C7/06 , G11C7/00
CPC分类号： G11C7/06
摘要： A semiconductor memory of the present invention includes: a plurality of memory cells; a pair of local bit lines connected to the plurality of memory cells; a local sense amplifier for amplifying a potential difference between the pair of local bit lines; a pair of global bit lines electrically connected to the pair of local bit lines through a switch; and a global sense amplifier for amplifying a potential difference between the pair of global bit lines, wherein the local sense amplifier includes a plurality of transistors, each of the plurality of transistors included in the local sense amplifier is a transistor of a first conductivity type, and the global sense amplifier includes a transistor of a second conductivity type different from the first conductivity type.
摘要翻译：本发明的半导体存储器包括：多个存储单元; 连接到所述多个存储器单元的一对局部位线; 本地读出放大器，用于放大一对局部位线之间的电位差; 一对全局位线通过开关电连接到该对局部位线; 以及用于放大所述一对全局位线之间的电位差的全局读出放大器，其中所述局部读出放大器包括多个晶体管，所述局部读出放大器中包括的所述多个晶体管中的每一个是第一导电类型的晶体管，并且全球感测放大器包括不同于第一导电类型的第二导电类型的晶体管。

4. 发明授权

US06208567B1 Semiconductor device capable of cutting off a leakage current in a defective array section 失效
标题翻译：能够切断缺陷阵列部分的漏电流的半导体装置
公开(公告)号：US06208567B1
公开(公告)日：2001-03-27
申请号：US09014775
申请日：1998-01-28
申请人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
发明人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
IPC分类号： G11C2900
CPC分类号： G01R31/3004 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.
摘要翻译：本发明的半导体器件包括：包括多个电路块的阵列部分; 泄漏电流切断部，切断在所述阵列部中的所述多个电路块中的至少一个电路中发生的漏电流; 以及控制部分，用于根据泄漏电流切断信息控制漏电流切断部分。

5. 发明授权

US5828717A Time counting circuit and counter circuit 失效
标题翻译：计时电路和计数器电路
公开(公告)号：US5828717A
公开(公告)日：1998-10-27
申请号：US624960
申请日：1996-03-27
申请人： Keiichi Kusumoto , Shiro Dosho , Yutaka Terada , Akira Matsuzawa
发明人： Keiichi Kusumoto , Shiro Dosho , Yutaka Terada , Akira Matsuzawa
IPC分类号： G01R29/027 , G01C21/00
CPC分类号： G01R29/0273
摘要： There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption. An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition. A time-difference operating circuit corrects the numeric data outputted from the signal converting circuit based on the number of circulations of signal transition outputted from the counter circuit to provide time data, while calculating and outputting the pulse spacing of the pulse signal to be measured.
摘要翻译：提供了一种用于以高精度和低功耗测量脉冲信号的脉冲间隔的时间计数电路。由连接在环上的奇数个反相器组成的逆变器环振荡，并且一个信号转换发生在似乎在逆变器环周围似乎循环。连接到构成逆变器环的逆变器的各个输出端子的保持电路在待测脉冲信号的上升沿同时输出从逆变器输出的信号。然后，输出的信号由信号转换电路转换成数字数据。连接到构成逆变器环的逆变器之一的输出端的计数器电路对信号转换的循环数进行计数。时差操作电路根据从计数器电路输出的信号转换的循环数来校正从信号转换电路输出的数字数据，以提供时间数据，同时计算并输出要测量的脉冲信号的脉冲间隔。

6. 发明授权

US5982841A Time counting circuit, pulse converting circuit and FM demodulating circuit 失效
标题翻译：时间计数电路，脉冲转换电路和FM解调电路
公开(公告)号：US5982841A
公开(公告)日：1999-11-09
申请号：US747180
申请日：1996-11-12
申请人： Yutaka Terada , Keiichi Kusumoto , Akira Matsuzawa
发明人： Yutaka Terada , Keiichi Kusumoto , Akira Matsuzawa
IPC分类号： G01R29/027 , H03D3/04 , H03K9/06 , H03M1/50 , G01M3/00
CPC分类号： G04F10/005 , G01R29/027 , H03D3/04 , H03K9/06
摘要： Provided is a time counting circuit which can measure the time taken from the rising edge to the falling edge of a pulse signal and the time from the falling edge to the rising edge thereof. The time counting circuit according to the present invention comprises a measuring circuit for measuring the time between either of the rising and falling edges of the pulse signal, and a pulse converting circuit for converting a pulse signal to be measured to a pulse signal having either of the edges in accordance with the rising edge of the pulse signal to be measured and having either of the edges in accordance with the falling edge of the pulse signal to be measured. The time between either of the edges of the pulse signal converted by the pulse converting circuit is measured by the measuring circuit. The time obtained by measurement is the time taken from the rising edge to the falling edge of the pulse signal to be measured or the time taken from the falling edge to the rising edge thereof.
摘要翻译：提供了一种时间计数电路，其可以测量从脉冲信号的上升沿到下降沿的时间以及从下降沿到上升沿的时间。根据本发明的计时电路包括：测量脉冲信号的上升沿和下降沿之间的时间的测量电路;以及脉冲转换电路，用于将要测量的脉冲信号转换成具有根据要测量的脉冲信号的上升沿的边缘，并根据要测量的脉冲信号的下降沿具有任一边缘。由脉冲转换电路转换的脉冲信号的任一边之间的时间由测量电路测量。通过测量获得的时间是从要测量的脉冲信号的上升沿到下降沿或从下降沿到其上升沿的时间所花费的时间。

7. 发明授权

US5717624A Analog memory circuit and method for recording analog signal 失效
标题翻译：模拟记忆电路和记录模拟信号的方法
公开(公告)号：US5717624A
公开(公告)日：1998-02-10
申请号：US739867
申请日：1996-10-31
申请人： Keiichi Kusumoto , Kenji Murata , Yutaka Terada , Akira Matsuzawa
发明人： Keiichi Kusumoto , Kenji Murata , Yutaka Terada , Akira Matsuzawa
IPC分类号： G11C27/02 , G11C27/00
CPC分类号： G11C27/026
摘要： An analog memory circuit of the present invention includes: a recording circuit for recording and holding an input analog signal as a charge and for reading out the analog signal after deterioration of the analog signal caused by leakage of the charge in a holding operation is eliminated; a selecting circuit for controlling an operation of the recording circuit; and a driving circuit for supplying a predetermined constant voltage to the recording circuit, wherein the recording circuit includes: an input/output terminal for inputting and outputting the analog signal; a first capacitor having a first electrode and a second electrode, for recording and holding the analog signal as the charge; and a second capacitor connected between the second electrode of the first capacitor and a reference potential, for holding a charge leaked from the first capacitor, and wherein an amount of charge corresponding to an amount of leaked charge held in the second capacitor is restored to the first capacitor with predetermined timing.
摘要翻译：本发明的模拟存储器电路包括：记录电路，用于记录和保持作为电荷的输入模拟信号，并且用于在由保持操作中的电荷泄漏引起的模拟信号劣化后读出模拟信号; 用于控制记录电路的操作的选择电路; 以及用于向所述记录电路提供预定的恒定电压的驱动电路，其中所述记录电路包括：用于输入和输出所述模拟信号的输入/输出端子; 具有第一电极和第二电极的第一电容器，用于记录和保持模拟信号作为电荷; 以及连接在第一电容器的第二电极和参考电位之间的第二电容器，用于保持从第一电容器泄漏的电荷，并且其中对应于保持在第二电容器中的泄漏电荷量的电荷量恢复到具有预定定时的第一电容器。

8. 发明授权

US5999586A Time counting circuit and pulse signal generating method 失效
标题翻译：时间计数电路和脉冲信号产生方法
公开(公告)号：US5999586A
公开(公告)日：1999-12-07
申请号：US795907
申请日：1997-03-04
申请人： Yutaka Terada , Keiichi Kusumoto , Akira Matsuzawa
发明人： Yutaka Terada , Keiichi Kusumoto , Akira Matsuzawa
IPC分类号： G01D3/00
CPC分类号： G01D3/00
摘要： There is provided a small-size time counting circuit which measures time with high accuracy and low power consumption. Around a differential inverter ring composed of an odd number of differential inverters of identical structure connected in a ring configuration, signal transition is caused to circulate by oscillation. A first signal group is composed of normal output signals from the odd-numbered differential inverters and inverted output signals from the even-numbered differential inverters, which rise and fall sequentially at equal time intervals corresponding to delay times in the individual differential inverters. A second signal group is composed of inverted output signals from the odd-numbered differential inverters and normal output signals from the even-numbered differential inverters, which similarly rise and fall sequentially at equal time intervals. Accordingly, even when the rise time of an output signal from each of the differential inverters composing the differential inverter ring is different from the fall time thereof, the use of the first and second signal groups provides equal increments of time for time measurement.
摘要翻译：提供了一种小型时间计数电路，以高精度和低功耗测量时间。围绕由具有相同结构的奇数差分逆变器组成的差动逆变器环以环形结构连接，使信号转变通过振荡循环。第一信号组由来自奇数编号的差分逆变器的正常输出信号和来自偶数编号的差分逆变器的反相输出信号组成，其以与各个差分逆变器中的延迟时间相对应的等时间间隔顺序上升和下降。第二信号组由来自奇数编号的差分逆变器的反相输出信号和来自偶数编号差动逆变器的正常输出信号组成，其类似地以相等的时间间隔顺序地上升和下降。因此，即使来自构成差分逆变器环的各差分逆变器的输出信号的上升时间与其下降时间不同，所以使用第一和第二信号组提供相等的时间测量时间。

9. 发明授权

US5835552A Time counting circuit and counter circuit 失效
公开(公告)号：US5835552A
公开(公告)日：1998-11-10
申请号：US747129
申请日：1996-11-12
申请人： Keiichi Kusumoto , Shiro Dosho , Yutaka Terada , Akira Matsuzawa
发明人： Keiichi Kusumoto , Shiro Dosho , Yutaka Terada , Akira Matsuzawa
IPC分类号： G01R29/027 , H03D3/04 , H03K9/06 , H03M1/50 , G01B7/00
CPC分类号： G04F10/005 , G01R29/027 , H03D3/04 , H03K9/06
摘要： There is provided a time counting circuit for measuring a pulse spacing of a pulse signal with high accuracy and with low power consumption. An inverter ring composed of an odd number of inverters connected in a ring oscillates and one signal transition occurs after another as though seemingly circulating around the inverter ring. Holding circuits connected to respective output terminals of the inverters composing the inverter ring output, on the rising edge of a pulse signal to be measured, signals outputted from the inverters at the same time. The outputted signals are then converted by a signal converting circuit to numeric data. A counter circuit connected to the output terminal of one of the inverters composing the inverter ring counts the number of circulations of signal transition. A time-difference operating circuit corrects the numeric data outputted from the signal converting circuit based on the number of circulations of signal transition outputted from the counter circuit to provide time data, while calculating and outputting the pulse spacing of the pulse signal to be measured.

10. 发明授权

US06172557B2 Time counting circuit, pulse converting circuit and FM demodulating circuit 失效
标题翻译：时间计数电路，脉冲转换电路和FM解调电路
公开(公告)号：US06172557B2
公开(公告)日：2001-01-09
申请号：US09398817
申请日：1999-09-20
申请人： Yutaka Terada , Keiichi Kusumoto , Akira Matsuzawa
发明人： Yutaka Terada , Keiichi Kusumoto , Akira Matsuzawa
IPC分类号： H03D300
CPC分类号： G04F10/005 , G01R29/027 , H03D3/04 , H03K9/06
摘要： Provided is a time counting circuit which can measure the time taken from the rising edge to the falling edge of a pulse signal and the time from the falling edge to the rising edge thereof. The time counting circuit according to the present invention comprises a measuring circuit for measuring the time between either of the rising and falling edges of the pulse signal, and a pulse converting circuit for converting a pulse signal to be measured to a pulse signal having either of the edges in accordance with the rising edge of the pulse signal to be measured and having either of the edges in accordance with the falling edge of the pulse signal to be measured. The time between either of the edges of the pulse signal converted by the pulse converting circuit is measured by the measuring circuit. The time obtained by measurement is the time taken from the rising edge to the falling edge of the pulse signal to be measured or the time taken from the falling edge to the rising edge thereof.
摘要翻译：提供了一种时间计数电路，其可以测量从脉冲信号的上升沿到下降沿的时间以及从下降沿到上升沿的时间。根据本发明的计时电路包括：测量脉冲信号的上升沿和下降沿之间的时间的测量电路;以及脉冲转换电路，用于将要测量的脉冲信号转换成具有根据要测量的脉冲信号的上升沿的边缘，并根据要测量的脉冲信号的下降沿具有任一边缘。由脉冲转换电路转换的脉冲信号的任一边之间的时间由测量电路测量。通过测量获得的时间是从要测量的脉冲信号的上升沿到下降沿或从下降沿到其上升沿的时间所花费的时间。

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