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1. 发明授权

US06944003B2 Semiconductor integrated circuit with voltage-detecting circuit and signal transmitting and receiving system 失效
标题翻译：具有电压检测电路和信号发射和接收系统的半导体集成电路
公开(公告)号：US06944003B2
公开(公告)日：2005-09-13
申请号：US10365527
申请日：2003-02-13
申请人： Hirokazu Sugimoto , Takashi Hirata , Hironori Akamatsu , Toru Iwata , Satoshi Takahashi
发明人： Hirokazu Sugimoto , Takashi Hirata , Hironori Akamatsu , Toru Iwata , Satoshi Takahashi
IPC分类号： G01R31/28 , H01L21/66 , H02H9/04 , H02H3/24
CPC分类号： H02H9/046
摘要： A first semiconductor integrated circuit is connected to a second semiconductor integrated circuit with a cable. In the first semiconductor integrated circuit, when a power supply voltage becomes less than a set voltage detection level, a voltage-detecting circuit outputs a voltage-detected signal to lower the voltage of the cable and to stop the operation. The second semiconductor integrated circuit detects the decrease in the voltage of the cable to recognize the halt of the operation of the first semiconductor integrated circuit. In the first semiconductor integrated circuit thus configured, in testing the operation under low-voltage conditions in which the power supply voltage is less than the set voltage detection level, the voltage-detecting circuit receives a control signal from an external terminal to stop the operation forcibly. Consequently, even when the power supply voltage is made lower than the set voltage-detecting level, the first semiconductor integrated circuit properly operates until the power supply voltage reaches a predetermined lower limit of operating voltage. Thus, evaluation of operation is possible under low-voltage conditions.
摘要翻译：第一半导体集成电路通过电缆连接到第二半导体集成电路。在第一半导体集成电路中，当电源电压变得小于设定电压检测电平时，电压检测电路输出电压检测信号来降低电缆的电压并停止工作。第二半导体集成电路检测电缆的电压的降低以识别第一半导体集成电路的操作停止。在这样配置的第一半导体集成电路中，在电源电压小于设定电压检测电平的低电压条件下进行测试时，电压检测电路从外部端子接收控制信号，停止动作强制。因此，即使电源电压低于设定电压检测电平，第一半导体集成电路也可以正常工作，直到电源电压达到预定的工作电压下限。因此，在低电压条件下可以进行运行评估。

2. 发明授权

US06201412B1 Semiconductor integrated circuit with driver stabilization using parasitic capacitance 失效
标题翻译：具有驱动器稳定的半导体集成电路使用寄生电容
公开(公告)号：US06201412B1
公开(公告)日：2001-03-13
申请号：US09123902
申请日：1998-07-28
申请人： Toru Iwata , Hironori Akamatsu , Takashi Hirata
发明人： Toru Iwata , Hironori Akamatsu , Takashi Hirata
IPC分类号： H03K190175
CPC分类号： H03K19/01707
摘要： The semiconductor integrated circuit of this invention includes: a driver including a MOS transistor for driving a load; and a stabilizer for stabilizing a change in a voltage at a source of the MOS transistor due to a gate-source parasitic capacitance of the MOS transistor.
摘要翻译：本发明的半导体集成电路包括：驱动器，其包括用于驱动负载的MOS晶体管; 以及用于稳定由于MOS晶体管的栅极 - 源极寄生电容而在MOS晶体管的源极处的电压变化的稳定器。

3. 发明授权

US06246627B1 Semiconductor device capable of cutting off a leakage current in a defective array section and method thereof 有权
标题翻译：能够切断缺陷阵列部分的漏电流的半导体装置及其方法
公开(公告)号：US06246627B1
公开(公告)日：2001-06-12
申请号：US09397239
申请日：1999-09-16
申请人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
发明人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
IPC分类号： G11C514
CPC分类号： G01R31/3004 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.
摘要翻译：本发明的半导体器件包括：包括多个电路块的阵列部分; 泄漏电流切断部，切断在所述阵列部中的所述多个电路块中的至少一个电路中发生的漏电流; 以及控制部分，用于根据泄漏电流切断信息控制漏电流切断部分。

4. 发明授权

US6145065A Memory access buffer and reordering apparatus using priorities 失效
标题翻译：使用优先级的存储器访问缓冲器和重新排序装置
公开(公告)号：US6145065A
公开(公告)日：2000-11-07
申请号：US67899
申请日：1998-04-29
申请人： Satoshi Takahashi , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Yutaka Terada , Takashi Hirata
发明人： Satoshi Takahashi , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Yutaka Terada , Takashi Hirata
IPC分类号： G06F13/16 , G06F12/02
CPC分类号： G06F13/1631
摘要： A current problem is that when a DRAM is to be accessed through a data bus, the DRAM is accessed independently of a bank, a row address, etc., and therefore, is inefficient. To solve this problem, an address bus and a data bus are connected to a main memory part independently of each other, a temporary memory part for holding a plurality of addresses in advance is disposed on the address bus side and holds addresses for every access to the main memory part regardless of transfer of data, thereby pipelining address inputting cycles. Further, for the purpose of an effective operation of the main memory part, using the addresses which are held, the addresses are rearranged in such a manner that addresses with the same row addresses become continuous to each other, or when there are not addresses with the same row addresses, addresses different banks from each other become continuous to each other, and the memory is thereafter accessed. This reduces the number of precharges, shortens a standby period which is necessary for a precharge, and realizes accessing while reducing a wasteful use of time.
摘要翻译：目前的问题在于，当通过数据总线访问DRAM时，独立于存储体，行地址等访问DRAM，因此是低效的。为了解决这个问题，地址总线和数据总线彼此独立地连接到主存储器部分，预先存储多个地址的临时存储器部分设置在地址总线侧，并且保存地址以进行每次访问主存储部分不管数据传输，从而流水线地址输入周期。此外，为了主存储器部分的有效操作，使用所保存的地址，地址被重新排列，使得具有相同行地址的地址彼此连续，或者当没有地址与相同的行地址，彼此不同的存储体彼此变得连续，并且此后访问存储器。这减少了预充电次数，缩短了预充电所需的待机时间，并实现了访问，同时减少了浪费时间的使用。

5. 发明授权

US06208567B1 Semiconductor device capable of cutting off a leakage current in a defective array section 失效
标题翻译：能够切断缺陷阵列部分的漏电流的半导体装置
公开(公告)号：US06208567B1
公开(公告)日：2001-03-27
申请号：US09014775
申请日：1998-01-28
申请人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
发明人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
IPC分类号： G11C2900
CPC分类号： G01R31/3004 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.
摘要翻译：本发明的半导体器件包括：包括多个电路块的阵列部分; 泄漏电流切断部，切断在所述阵列部中的所述多个电路块中的至少一个电路中发生的漏电流; 以及控制部分，用于根据泄漏电流切断信息控制漏电流切断部分。

6. 发明授权

US6140864A Circuit for controlling leakage current in large scale integrated circuits 失效
标题翻译：用于控制大规模集成电路中的漏电流的电路
公开(公告)号：US6140864A
公开(公告)日：2000-10-31
申请号：US927061
申请日：1997-09-10
申请人： Takashi Hirata , Toru Iwata , Hironori Akamatsu
发明人： Takashi Hirata , Toru Iwata , Hironori Akamatsu
IPC分类号： G06F1/26 , G05F3/02
CPC分类号： G06F1/26
摘要： In an LSI circuit, respective voltages on power-source lines connected to the respective sources of transistors which are turned OFF in a circuit block in the standby state are controlled by a power-source-voltage control circuit to vary in response to variations in the threshold voltages of the transistors. Consequently, the differential voltage (Vgs-Vt) between the gate-to-source voltage Vgs of each of the transistors and the threshold voltage Vt thereof is held constant at a given value, so that an OFF-state leakage current flowing through the transistor in the circuit block in the standby state is reduced and held constant at a given value. What results is a reduction in the power consumption of the circuit block in the standby state.
摘要翻译：在LSI电路中，通过电源电压控制电路来控制在待机状态下在电路块中断开的与晶体管的各个源连接的电源线上的各个电压，以响应于晶体管的阈值电压。因此，每个晶体管的栅 - 源电压Vgs与其阈值电压Vt之间的差分电压（Vgs-Vt）保持恒定在给定值，使得流过晶体管的截止状态漏电流处于待机状态的电路块减小并保持恒定在给定值。在待机状态下电路块的功耗降低是什么结果。

7. 发明授权

US6009024A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US6009024A
公开(公告)日：1999-12-28
申请号：US46880
申请日：1998-03-24
申请人： Takashi Hirata , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Satoshi Takahashi , Yutaka Terada
发明人： Takashi Hirata , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Satoshi Takahashi , Yutaka Terada
IPC分类号： G11C7/06 , G11C7/00
CPC分类号： G11C7/06
摘要： A semiconductor memory of the present invention includes: a plurality of memory cells; a pair of local bit lines connected to the plurality of memory cells; a local sense amplifier for amplifying a potential difference between the pair of local bit lines; a pair of global bit lines electrically connected to the pair of local bit lines through a switch; and a global sense amplifier for amplifying a potential difference between the pair of global bit lines, wherein the local sense amplifier includes a plurality of transistors, each of the plurality of transistors included in the local sense amplifier is a transistor of a first conductivity type, and the global sense amplifier includes a transistor of a second conductivity type different from the first conductivity type.
摘要翻译：本发明的半导体存储器包括：多个存储单元; 连接到所述多个存储器单元的一对局部位线; 本地读出放大器，用于放大一对局部位线之间的电位差; 一对全局位线通过开关电连接到该对局部位线; 以及用于放大所述一对全局位线之间的电位差的全局读出放大器，其中所述局部读出放大器包括多个晶体管，所述局部读出放大器中包括的所述多个晶体管中的每一个是第一导电类型的晶体管，并且全球感测放大器包括不同于第一导电类型的第二导电类型的晶体管。

8. 发明授权

US06356144B1 LSI core including voltage generation circuit and system LSI including the LSI core 有权
标题翻译： LSI核心，包括具有LSI核心的电压产生电路和系统LSI
公开(公告)号：US06356144B1
公开(公告)日：2002-03-12
申请号：US09580139
申请日：2000-05-30
申请人： Hironori Akamatsu , Yutaka Terada , Takashi Hirata , Tadahiro Yoshida , Yoshihide Komatsu
发明人： Hironori Akamatsu , Yutaka Terada , Takashi Hirata , Tadahiro Yoshida , Yoshihide Komatsu
IPC分类号： H01L2500
CPC分类号： G06F13/4086 , H01L2224/05554
摘要： An LSI core includes a first terminal; a second terminal; and a voltage generation circuit for generating a voltage. The first terminal is connected to a first external line provided outside the LSI core. The second terminal is connected to the first external line and to a second external line provided outside the LSI core. The voltage generation circuit includes a voltage generation section for generating the voltage, an output section for outputting the voltage generated by the voltage generation section to the first external line through the first terminal, and an input section for receiving the voltage, output to the first external line by the output section, through the second external line and the second terminal.
摘要翻译： LSI核心包括第一终端; 第二个终端以及用于产生电压的电压产生电路。第一端子连接到设置在LSI核心外部的第一外部线路。第二端子连接到第一外部线路和连接到设置在LSI核心外部的第二外部线路。电压产生电路包括用于产生电压的电压产生部分，用于通过第一端子将由电压产生部分产生的电压输出到第一外部线路的输出部分和用于接收电压的输入部分，输出到第一外部线由输出部分，通过第二个外部线路和第二个终端。

9. 发明授权

US06297675B1 Semiconductor integrated circuit and semiconductor integrated circuit system having serially interconnectable data buses 有权
标题翻译：具有串行可互连数据总线的半导体集成电路和半导体集成电路系统
公开(公告)号：US06297675B1
公开(公告)日：2001-10-02
申请号：US09478530
申请日：2000-01-06
申请人： Hironori Akamatsu , Yutaka Terada , Takashi Hirata , Yukio Arima , Satoshi Takahashi , Tadahiro Yoshida , Yoshihide Komatsu , Hiroyuki Yamauchi
发明人： Hironori Akamatsu , Yutaka Terada , Takashi Hirata , Yukio Arima , Satoshi Takahashi , Tadahiro Yoshida , Yoshihide Komatsu , Hiroyuki Yamauchi
IPC分类号： H03B100
CPC分类号： H03K19/018514 , Y10T307/549
摘要： A data line pair and a strobe line pair are provided between first and second chips to exchange data therebetween. The first chip includes an output circuit and a controller for controlling the output circuit. The second chip includes an input circuit. For example, the output circuit supplies a direct current from a power supply to one of the data lines. Then, the input circuit feeds back the received current to the output circuit through a pair of terminal resistors and the other data line. Subsequently, the output circuit supplies the fed back direct current to one of the strobe lines. In response, the input circuit feeds back the received current again to the output circuit through another pair of terminal resistors and the other strobe line. And then the fed back current is drained to the ground. Thus, compared to driving the data and strobe line pairs separately with the same amount of current supplied, the current dissipation can be halved. In this manner, the present invention is applicable to reduction of current dissipation when data should be transmitted at high speeds through multiple data bus pairs that are driven with a current supplied.
摘要翻译：在第一和第二芯片之间提供数据线对和选通线对，以在它们之间交换数据。第一芯片包括输出电路和用于控制输出电路的控制器。第二芯片包括输入电路。例如，输出电路将电流从电源提供给数据线之一。然后，输入电路通过一对端子电阻和另一条数据线将接收的电流反馈到输出电路。随后，输出电路将反馈的直流电流提供给选通线之一。作为响应，输入电路通过另一对端子电阻器和另一个选通线路将接收到的电流再次反馈到输出电路。然后将反馈电流排到地面。因此，与以相同的电流量驱动数据和选通线对相比，电流消耗可以减半。以这种方式，本发明可应用于当通过以所提供的电流驱动的多个数据总线对以高速传输数据时，减少电流消耗。

10. 发明授权

US06215192B1 Integrated circuit package and integrated circuit package control system 失效
标题翻译：集成电路封装和集成电路封装控制系统
公开(公告)号：US06215192B1
公开(公告)日：2001-04-10
申请号：US09095211
申请日：1998-06-10
申请人： Takashi Hirata , Hironori Akamatsu
发明人： Takashi Hirata , Hironori Akamatsu
IPC分类号： H01L2348
CPC分类号： H01L24/06 , H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/06136 , H01L2224/16145 , H01L2224/32145 , H01L2224/45124 , H01L2224/45144 , H01L2224/48137 , H01L2224/48247 , H01L2224/4826 , H01L2224/48624 , H01L2224/48724 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2225/06562 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： The integrated circuit package of this invention includes a first integrated circuit chip and a second integrated circuit chip having a same function, wherein the first integrated circuit chip and the second integrated circuit chip are connected to a common bus.
摘要翻译：本发明的集成电路封装包括具有相同功能的第一集成电路芯片和第二集成电路芯片，其中第一集成电路芯片和第二集成电路芯片连接到公共总线。

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