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1. 发明授权

US4994411A Process of producing semiconductor device 失效
标题翻译：半导体器件制造工艺
公开(公告)号：US4994411A
公开(公告)日：1991-02-19
申请号：US321385
申请日：1989-03-10
申请人： Takahiro Naito , Gen Murakami , Hiromichi Suzuki , Hajime Sato , Wahei Kitamura , Masachika Masuda
发明人： Takahiro Naito , Gen Murakami , Hiromichi Suzuki , Hajime Sato , Wahei Kitamura , Masachika Masuda
IPC分类号： H01L23/495
CPC分类号： H01L24/27 , H01L23/4951 , H01L23/49548 , H01L23/49558 , H01L24/32 , H01L2224/32014 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/92147 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/12044 , H01L2924/181 , Y10T29/49121
摘要： A process of producing a semiconductor device involving the steps of providing a lead frame having inner leads spaced from each other and connected together by a connecting portion; bonding a layer of an insulating material to the connecting portion and to surrounding portions of the inner leads; removing the connecting portion and a portion of the layer of insulating material to form end portions of the inner leads which are separated from each other and retained in a spaced arrangement by a remaning portion of the layer of insulating material; joining a semiconductor chip having bonding pads to the end portions of the inner leads; connecting the bonding pads on the semiconductor chip and the inner leads by wires; and encapsulating the semiconductor chip, the remaining portion of the layer of insulating material, the inner leads and the wires within a resin material; a peripheral portion of one face of the semiconductor chip partially overlapping faces of the end portions.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：提供具有彼此间隔开并通过连接部连接在一起的内部引线的引线框架; 将绝缘材料层粘合到连接部分和内引线的周围部分; 去除所述连接部分和所述绝缘材料层的一部分以形成所述内部引线的端部，所述端部彼此分离并且通过所述绝缘材料层的剩余部分以间隔布置保持; 将具有接合焊盘的半导体芯片接合到所述内引线的端部; 通过电线连接半导体芯片上的接合焊盘和内部引线; 将半导体芯片，绝缘材料层的剩余部分，内部引线和电线封装在树脂材料内; 半导体芯片的一个面的周边部分与端部的部分重叠面。

2. 发明授权

US07261207B2 Method for carrying a semiconductor device 有权
标题翻译：携带半导体器件的方法
公开(公告)号：US07261207B2
公开(公告)日：2007-08-28
申请号：US10770581
申请日：2004-02-04
申请人： Hiromichi Suzuki , Wahei Kitamura , Tokuji Toida , Toshimasa Shirai
发明人： Hiromichi Suzuki , Wahei Kitamura , Tokuji Toida , Toshimasa Shirai
IPC分类号： B65D85/48
CPC分类号： H01L21/67294 , G05B19/128 , G05B2219/31095 , Y02P90/10 , Y10S414/14 , Y10T29/49121 , Y10T29/4913 , Y10T29/53091 , Y10T29/53174 , Y10T29/53178
摘要： A method for carrying a semiconductor device includes: (a) providing semiconductor devices each having a main surface, a back surface, and a plurality of external terminals; (b) providing a tray having a front surface, a rear surface, an electronic tag imbedded in the tray, first concaved portions formed on the front surface, second concaved portions formed on the rear surface, the electronic tag constituted by a non-contact recognition type chip having a memory circuit in which recognizable information is stored, a depth of the first concaved portion is deeper than a depth of the second concaved portion; (c) housing the semiconductor devices into the first concaved portions respectively in such a manner that the back surface of the semiconductor device being oppose to a bottom of the first concaved portion; and (d) carrying the tray with the semiconductor devices.
摘要翻译：一种用于承载半导体器件的方法包括：（a）提供各自具有主表面，背表面和多个外部端子的半导体器件; （b）提供具有前表面，后表面，嵌入在托盘中的电子标签的托盘，形成在前表面上的第一凹部，形成在后表面上的第二凹部，由非接触形成的电子标签识别型芯片，其具有存储可识别信息的存储电路，所述第一凹部的深度比所述第二凹部的深度深; （c）分别将半导体器件分别容纳在第一凹部中，使得半导体器件的背面相对于第一凹部的底部; 和（d）用半导体器件托盘。

3. 发明申请

US20090176333A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090176333A1
公开(公告)日：2009-07-09
申请号：US12400892
申请日：2009-03-10
申请人： Yoshihisa MATSUBARA , Hiromichi Suzuki , Wahei Kitamura , Kosho Akiyama , Seiji Kato
发明人： Yoshihisa MATSUBARA , Hiromichi Suzuki , Wahei Kitamura , Kosho Akiyama , Seiji Kato
IPC分类号： H01L21/78 , H01L21/60
CPC分类号： H01L21/67333 , H01L2924/0002 , H01L2924/00
摘要： To prevent semiconductor chips from adhering to the trays during transport, a method is employed which transports semiconductor chips in the following state. When trays provided with a plurality of accommodating portions having a recessed cross section for accommodating semiconductor chips on a main surface thereof are stacked in a plurality of stages, the semiconductor chips are accommodated in spaces defined by the accommodating portions formed over the main surface of the lower-stage tray and corresponding accommodating portions formed over the back surface of the upper-stage tray. Here, on bottom surfaces of the accommodating portions formed over the back surface of the upper-stage tray, isolated projections having a height which prevents the projections from coming into contact with the semiconductor chips are arranged in a scattered manner. In this way, it is possible to prevent the semiconductor chips from adhering to the back surface of the upper-stage tray.
摘要翻译：为了防止半导体芯片在运输期间粘附到托盘，采用以下状态传输半导体芯片的方法。当具有多个具有用于在其主表面上容纳半导体芯片的凹入截面的容纳部分的托盘被堆叠成多级时，半导体芯片被容纳在形成在主表面上的容纳部分所形成的空间中下级托盘和形成在上级托盘的后表面上的相应的容纳部分。这里，在形成在上层托盘的后表面上的容纳部分的底表面上，以散射方式布置具有防止突起与半导体芯片接触的高度的隔离突起。以这种方式，可以防止半导体芯片粘附到上层托盘的后表面。

4. 发明授权

US06223893B1 Surface package type semiconductor package and method of producing semiconductor memory 失效
标题翻译：表面封装型半导体封装及半导体存储器的制造方法
公开(公告)号：US06223893B1
公开(公告)日：2001-05-01
申请号：US09387049
申请日：1999-08-31
申请人： Wahei Kitamura , Gen Murakami , Kunihiko Nishi
发明人： Wahei Kitamura , Gen Murakami , Kunihiko Nishi
IPC分类号： B65D7302
CPC分类号： B32B27/08 , B32B27/18 , B32B27/304 , B32B27/32 , B32B2307/7246 , B32B2311/24 , B32B2323/04 , B32B2327/06 , B32B2439/00 , B65D79/02 , B65D81/266 , H01L21/67121 , H01L23/3107 , H01L23/3135 , H01L23/49506 , H01L23/49582 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/49171 , H01L2224/73265 , H01L2224/8592 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/20753 , H05K13/0084 , Y10S174/08 , Y10S428/922 , Y10T29/49121 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： In surface packaging of thin resin packages such as surface mount resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging. To solve this problem, the devices are sealed, by heat-sealing, in a bag moisture-tight at an assembly step of the resin molded devices where the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging. The devices are packaged in a moisture-proofing bag made of a laminate film, and a desiccant is sealed, by heat-sealing the bag, in the moisture-proofing bag together with the, e.g., surface mount semiconductor device having a plastic package encapsulating the semiconductor device.
摘要翻译：在诸如表面贴装树脂模制存储器IC等的薄树脂封装的表面封装中，由于树脂在包装之前吸收了水分，所以在焊料回流步骤中经常发生热冲击作用于封装的封装裂纹。为了解决这个问题，这些装置在树脂模制装置的树脂干燥的组装步骤中通过热封在袋子中被密封地密封，并且在执行表面之前从袋子中取出打包。将装置包装在由层压膜制成的防潮袋中，并且通过将防潮袋热封在防潮袋中，并与例如具有塑料封装的表面贴装半导体装置密封干燥剂半导体器件。

5. 发明授权

US07785986B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07785986B2
公开(公告)日：2010-08-31
申请号：US12400892
申请日：2009-03-10
申请人： Yoshihisa Matsubara , Hiromichi Suzuki , Wahei Kitamura , Kosho Akiyama , Seiji Kato
发明人： Yoshihisa Matsubara , Hiromichi Suzuki , Wahei Kitamura , Kosho Akiyama , Seiji Kato
IPC分类号： H01L21/30 , H01L23/34
CPC分类号： H01L21/67333 , H01L2924/0002 , H01L2924/00
摘要： To prevent semiconductor chips from adhering to the trays during transport, a method is employed which transports semiconductor chips in the following state. When trays provided with a plurality of accommodating portions having a recessed cross section for accommodating semiconductor chips on a main surface thereof are stacked in a plurality of stages, the semiconductor chips are accommodated in spaces defined by the accommodating portions formed over the main surface of the lower-stage tray and corresponding accommodating portions formed over the back surface of the upper-stage tray. Here, on bottom surfaces of the accommodating portions formed over the back surface of the upper-stage tray, isolated projections having a height which prevents the projections from coming into contact with the semiconductor chips are arranged in a scattered manner. In this way, it is possible to prevent the semiconductor chips from adhering to the back surface of the upper-stage tray.
摘要翻译：为了防止半导体芯片在运输期间粘附到托盘，采用以下状态传输半导体芯片的方法。当具有多个具有用于在其主表面上容纳半导体芯片的凹入截面的容纳部分的托盘被堆叠成多级时，半导体芯片被容纳在形成在主表面上的容纳部分所形成的空间中下级托盘和形成在上级托盘的后表面上的相应的容纳部分。这里，在形成在上层托盘的后表面上的容纳部分的底表面上，以散射方式布置具有防止突起与半导体芯片接触的高度的隔离突起。以这种方式，可以防止半导体芯片粘附到上层托盘的后表面。

6. 发明授权

US07504315B2 Method of transporting semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：输送半导体器件的方法及半导体器件的制造方法
公开(公告)号：US07504315B2
公开(公告)日：2009-03-17
申请号：US11007185
申请日：2004-12-09
申请人： Yoshihisa Matsubara , Hiromichi Suzuki , Wahei Kitamura , Kosho Akiyama , Seiji Kato
发明人： Yoshihisa Matsubara , Hiromichi Suzuki , Wahei Kitamura , Kosho Akiyama , Seiji Kato
IPC分类号： H01L21/30
CPC分类号： H01L21/67333 , H01L2924/0002 , H01L2924/00
摘要： To prevent semiconductor chips from adhering to the trays during transport, a method is employed which transports semiconductor chips in the following state. When trays provided with a plurality of accommodating portions having a recessed cross section for accommodating semiconductor chips on a main surface thereof are stacked in a plurality of stages, the semiconductor chips are accommodated in spaces defined by the accommodating portions formed over the main surface of the lower-stage tray and corresponding accommodating portions formed over the back surface of the upper-stage tray. Here, on bottom surfaces of the accommodating portions formed over the back surface of the upper-stage tray, isolated projections having a height which prevents the projections from coming into contact with the semiconductor chips are arranged in a scattered manner. In this way, it is possible to prevent the semiconductor chips from adhering to the back surface of the upper-stage tray.
摘要翻译：为了防止半导体芯片在运输期间粘附到托盘，采用以下状态传输半导体芯片的方法。当具有多个具有用于在其主表面上容纳半导体芯片的凹入截面的容纳部分的托盘被堆叠成多级时，半导体芯片被容纳在形成在主表面上的容纳部分所形成的空间中下级托盘和形成在上级托盘的后表面上的相应的容纳部分。这里，在形成在上层托盘的后表面上的容纳部分的底表面上，以散射方式布置具有防止突起与半导体芯片接触的高度的隔离突起。以这种方式，可以防止半导体芯片粘附到上层托盘的后表面。

7. 发明授权

US4845543A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US4845543A
公开(公告)日：1989-07-04
申请号：US67969
申请日：1987-06-29
申请人： Susumu Okikawa , Hiroshi Mikino , Hiromichi Suzuki , Wahei Kitamura , Daiji Sakamoto
发明人： Susumu Okikawa , Hiroshi Mikino , Hiromichi Suzuki , Wahei Kitamura , Daiji Sakamoto
IPC分类号： B23K20/00 , C22C21/00 , H01L21/603 , H01L23/49
CPC分类号： H01L24/85 , B23K20/007 , C22C21/00 , H01L24/03 , H01L24/05 , H01L24/43 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05624 , H01L2224/29111 , H01L2224/29139 , H01L2224/29144 , H01L2224/2919 , H01L2224/29339 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48464 , H01L2224/48465 , H01L2224/48599 , H01L2224/48624 , H01L2224/48724 , H01L2224/73265 , H01L2224/78268 , H01L2224/78301 , H01L2224/83805 , H01L2224/85045 , H01L2224/85181 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L24/29 , H01L24/73 , H01L24/78 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/0102 , H01L2924/01024 , H01L2924/01025 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01065 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/01205 , H01L2924/0132 , H01L2924/01322 , H01L2924/10253 , H01L2924/15153 , H01L2924/15165 , H01L2924/15738 , H01L2924/1576 , H01L2924/16195 , H01L2924/181 , H01L2924/20753
摘要： A semiconductor device in which a pellet and external leads are connected by bonding wires made of aluminum containing a predetermined amount of at least one additive element, the bonding wires containing 0.05 to 3.0 weight % of at least one element selected from the group consisting of iron and palladium, or containing 0.05-3.0 weight % of at least one first element selected from the group consisting of nickel, iron and palladium and 0.05-3.0 weight % of at least one second element selected from the group consisting of magnesium, manganese and silicon, whereby the corrosion resistance of the wire is increased and the breaking strength of the wire is enhanced. The bonding wires can be connected to the semiconductor pellet by a ball bond, and it is disclosed that using a ball having a Vickers hardness of 30-50 enables good bonding of the bonding wire to, e.g., an aluminum pad on the semiconductor pellet to be achieved. A ball having such hardness can be provided by using specific aluminum alloy compositions and by a quenching of the ball. The bonding wire has the shape and height of its loop controlled by annealing the bonding wire at a specified temperature before bonding or by employing a specified composition for the material of the bonding wire. The loop shape and bondability of the bonding wire, which can be made of aluminum or an aluminum composition containing, e.g., about 1.5 weight % of magnesium, are controlled into the best states.
摘要翻译：一种半导体器件，其中通过由含有预定量的至少一种添加元素的铝制成的接合线来连接颗粒和外部引线，所述接合线含有0.05至3.0重量％的至少一种选自铁和钯，或含有0.05-3.0重量％的至少一种选自镍，铁和钯的第一元素和0.05-3.0重量％的至少一种选自镁，锰和硅的第二元素从而提高了导线的耐腐蚀性，提高了导线的断裂强度。接合线可以通过球接合连接到半导体芯片，并且公开了使用维氏硬度为30-50的球，能够将接合线与例如半导体芯片上的铝焊盘良好地接合到实现。具有这种硬度的球可以通过使用特定的铝合金组合物和球的淬火来提供。接合线的形状和高度通过在接合之前的特定温度下对接合线进行退火或通过使用用于接合线的材料的特定组成来控制。可以由铝或含有例如约1.5重量％的镁的铝组合物制成的接合线的环形和接合性被控制在最佳状态。

8. 发明申请

US20070235371A1 Method for carrying a semiconductor device 审中-公开
公开(公告)号：US20070235371A1
公开(公告)日：2007-10-11
申请号：US11808335
申请日：2007-06-08
申请人： Hiromichi Suzuki , Wahei Kitamura , Tokuji Toida , Toshimasa Shirai
发明人： Hiromichi Suzuki , Wahei Kitamura , Tokuji Toida , Toshimasa Shirai
IPC分类号： H01L21/67
CPC分类号： H01L21/67294 , G05B19/128 , G05B2219/31095 , Y02P90/10 , Y10S414/14 , Y10T29/49121 , Y10T29/4913 , Y10T29/53091 , Y10T29/53174 , Y10T29/53178
摘要： A method for carrying a semiconductor device includes: (a) providing semiconductor devices each having a main surface, a back surface, and a plurality of external terminals; (b) providing a tray having a front surface, a rear surface, an electronic tag imbedded in the tray, first concaved portions formed on the front surface, second concaved portions formed on the rear surface, the electronic tag constituted by a non-contact recognition type chip having a memory circuit in which recognizable information is stored, a depth of the first concaved portion is deeper than a depth of the second concaved portion; (c) housing the semiconductor devices into the first concaved portions respectively in such a manner that the back surface of the semiconductor device being oppose to a bottom of the first concaved portion; and (d) carrying the tray with the semiconductor devices.

9. 发明申请

US20050147488A1 Method of transporting semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：输送半导体器件的方法及半导体器件的制造方法
公开(公告)号：US20050147488A1
公开(公告)日：2005-07-07
申请号：US11007185
申请日：2004-12-09
申请人： Yoshihisa Matsubara , Hiromichi Suzuki , Wahei Kitamura , Kosho Akiyama , Seiji Kato
发明人： Yoshihisa Matsubara , Hiromichi Suzuki , Wahei Kitamura , Kosho Akiyama , Seiji Kato
IPC分类号： B65D21/02 , B65D85/86 , H01L21/673 , H01L21/68 , G06F19/00 , B66C17/08 , H01L23/48 , H01L29/40
CPC分类号： H01L21/67333 , H01L2924/0002 , H01L2924/00
摘要： To prevent semiconductor chips from adhering to the trays during transport, a method is employed which transports semiconductor chips in the following state. When trays provided with a plurality of accommodating portions having a recessed cross section for accommodating semiconductor chips on a main surface thereof are stacked in a plurality of stages, the semiconductor chips are accommodated in spaces defined by the accommodating portions formed over the main surface of the lower-stage tray and corresponding accommodating portions formed over the back surface of the upper-stage tray. Here, on bottom surfaces of the accommodating portions formed over the back surface of the upper-stage tray, isolated projections having a height which prevents the projections from coming into contact with the semiconductor chips are arranged in a scattered manner. In this way, it is possible to prevent the semiconductor chips from adhering to the back surface of the upper-stage tray.
摘要翻译：为了防止半导体芯片在运输期间粘附到托盘，采用以下状态传输半导体芯片的方法。当具有多个具有用于在其主表面上容纳半导体芯片的凹入截面的容纳部分的托盘被堆叠成多级时，半导体芯片被容纳在形成在主表面上的容纳部分所形成的空间中下级托盘和形成在上级托盘的后表面上的相应的容纳部分。这里，在形成在上层托盘的后表面上的容纳部分的底表面上，以散射方式布置具有防止突起与半导体芯片接触的高度的隔离突起。以这种方式，可以防止半导体芯片粘附到上层托盘的后表面。

10. 发明授权

US06981585B2 Surface package type semiconductor package and method of producing semiconductor memory 失效
公开(公告)号：US06981585B2
公开(公告)日：2006-01-03
申请号：US10207052
申请日：2002-07-30
申请人： Wahei Kitamura , Gen Murakami , Kunihiko Nishi
发明人： Wahei Kitamura , Gen Murakami , Kunihiko Nishi
IPC分类号： B65D73/02
CPC分类号： B32B27/08 , B32B27/18 , B32B27/304 , B32B27/32 , B32B2307/7246 , B32B2311/24 , B32B2323/04 , B32B2327/06 , B32B2439/00 , B65D79/02 , B65D81/266 , H01L21/67121 , H01L23/3107 , H01L23/3135 , H01L23/49506 , H01L23/49582 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/49171 , H01L2224/73265 , H01L2224/8592 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/20753 , H05K13/0084 , Y10S174/08 , Y10S428/922 , Y10T29/49121 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： In surface packaging of thin resin packages such as resin molded memory ICs or the like, cracks of the package occur frequently at a solder reflow step where thermal impact is applied to the package because the resin has absorbed moisture before packaging. To solve this problem, the devices are packaged moisture-tight at an assembly step of the resin molded devices where the resin is still dry, and are taken out from the bags immediately before the execution of surface packaging.

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