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1. 发明申请

US20120228504A1 MEMS SENSOR AND SENSOR ARRAY HAVING THE SAME 审中-公开
标题翻译： MEMS传感器和传感器阵列具有相同的功能
公开(公告)号：US20120228504A1
公开(公告)日：2012-09-13
申请号：US13498795
申请日：2009-09-29
申请人： Takanori Maeda , Takahiro Kawano , Kenjiro Fujimoto , Atsushi Onoe
发明人： Takanori Maeda , Takahiro Kawano , Kenjiro Fujimoto , Atsushi Onoe
IPC分类号： G01J5/02
CPC分类号： G01J5/02 , B81B3/007 , B81B2201/0278 , B81B2203/0127 , B81B2203/019 , G01J5/024
摘要： A MEMS sensor has a membrane 3 in a polygon released via a support portion 2, and the membrane 3 has a reinforcement rib portion 6 made up of a plurality of radially extending rib portions 6a and a plurality of divisional membranes 7 constructed between adjacent two rib portions 6a, 6a and formed in a polygon with the two rib portions 6a, 6a as two sides.
摘要翻译： MEMS传感器具有通过支撑部分2释放的多边形膜3，膜3具有由多个径向延伸的肋部分6a和多个分隔膜7构成的加强肋部分6，该分隔膜7在相邻的两个肋部分6a，6a并且以两个肋部6a，6a为两侧形成为多边形。

2. 发明申请

US20110260062A1 INFRARED SENSOR AND INFRARED SENSOR MANUFACTURING METHOD 审中-公开
标题翻译：红外传感器和红外传感器制造方法
公开(公告)号：US20110260062A1
公开(公告)日：2011-10-27
申请号：US13141604
申请日：2008-12-22
申请人： Kenjiro Fujimoto , Takanori Maeda , Takahiro Kawano
发明人： Kenjiro Fujimoto , Takanori Maeda , Takahiro Kawano
IPC分类号： G01J5/10 , H01L31/18
CPC分类号： H01L37/02 , G01J5/02 , G01J5/023 , G01J5/024 , G01J5/10 , G01J5/34
摘要： An infrared ray sensor and a method of fabricating the same is provided to increase detection sensitivity and to be easily fabricated with high yield rate. Provided herein is an infrared ray sensor having a frame-shaped substrate section formed in a square frame shape, a projecting base material section formed inside the frame-shaped substrate section and elongating to an incident direction of an infrared ray, and an infrared ray detection section provided on at least an upper lateral surface of the projecting base material section. The projecting base material section is made up of a plurality of rib-like element base material sections having a plurality of vertical base material sections and horizontal base material sections combined in a lattice shape.
摘要翻译：提供一种红外线传感器及其制造方法以提高检测灵敏度并且以高产率容易地制造。本发明提供一种红外线传感器，其具有形成为正方形框状的框状基板部，在框状的基板部内形成的伸长到红外线的入射方向的突出的基材部，以及红外线检测该截面设置在突出的基材部分的至少一个上侧表面上。突起基材部分由具有多个垂直基材部分和以格子形状组合的水平基材部分的多个肋状元件基材部分组成。

3. 发明申请

US20120235039A1 MEMS SENSOR 审中-公开
标题翻译： MEMS传感器
公开(公告)号：US20120235039A1
公开(公告)日：2012-09-20
申请号：US13499179
申请日：2009-09-29
申请人： Takanori Maeda , Kenjiro Fujimoto , Takahiro Kawano , Atsushi Onoe
发明人： Takanori Maeda , Kenjiro Fujimoto , Takahiro Kawano , Atsushi Onoe
IPC分类号： G01J5/00
CPC分类号： G01J5/02 , B81B3/007 , B81B2201/0278 , B81B2203/0118 , G01J5/024
摘要： A MEMS sensor has a frame portion 2 formed in a rectangular frame shape and a convexoconcave shaped membrane 3 that is constructed within the frame portion 2, the convexoconcave shape of the membrane 3 extend to two direction where a concave and a convex are orthogonal to each other, and square concave portions 3a and square convex portions 3b are disposed in a web shape within a whole in-plane area of the membrane 3.
摘要翻译： MEMS传感器具有形成为矩形框架形状的框架部分2和构造在框架部分2内的凸凹形状的膜3，膜3的凹凸形状延伸到两个方向，其中凹和凸与每个其他方形凹部3a和方形凸部3b以膜3的整个面内区域配置成网状。

4. 发明申请

US20130099121A1 INFRARED RAY DETECTION ELEMENT AND INFRARED RAY DETECTION DEVICE HAVING THE SAME 审中-公开
标题翻译：红外线检测元件和具有该红外线检测元件的红外线检测器件
公开(公告)号：US20130099121A1
公开(公告)日：2013-04-25
申请号：US13583771
申请日：2010-03-10
申请人： Takahiro Kawano , Kenjiro Fujimoto
发明人： Takahiro Kawano , Kenjiro Fujimoto
IPC分类号： G01J5/34
CPC分类号： G01J5/34 , G01J5/02 , G01J5/023 , G01J5/024 , H01L37/02
摘要： An infrared ray detection element has a plurality of pyroelectric layers that are laminated in a same direction as an incident direction of infrared rays, one or more intermediate electrode layers laminated between the plurality of pyroelectric layers; a front side electrode layer that is laminated on a front side of the pyroelectric layer positioned at a top side; and a back side electrode layer that is laminated on a back side of the pyroelectric layer positioned at a bottom side. The two pyroelectric layers adjacent in a front and back direction are performed with a polarization process such that polarization directions thereof are set to reverse directions to each other.
摘要翻译：红外线检测元件具有沿与红外线的入射方向相同的方向层叠的多个热电层，层叠在多个热电层之间的一个或多个中间电极层; 层叠在位于上侧的热电体的前侧的前侧电极层; 以及层叠在位于底侧的热电体的背面侧的背面电极层。在前后方向上相邻的两个热电层通过极化处理进行，使得其极化方向被设定为相反的方向。

5. 发明申请

US20120230364A1 SENSOR ARRAY 审中-公开
标题翻译：传感器阵列
公开(公告)号：US20120230364A1
公开(公告)日：2012-09-13
申请号：US13499170
申请日：2009-09-29
申请人： Takanori Maeda , Kenjiro Fujimoto , Takahiro Kawano , Atsushi Onoe
发明人： Takanori Maeda , Kenjiro Fujimoto , Takahiro Kawano , Atsushi Onoe
IPC分类号： G01J5/02
CPC分类号： G01J5/02 , B81B3/007 , B81B2201/0264 , B81B2201/0278 , B81B2203/0127 , B81B2207/053 , G01J5/024 , H01L27/14603 , H01L27/14669
摘要： A sensor array has a plurality of sensor elements, each of which has a rectangular frame shaped frame portion formed by connecting a plurality of frame pieces and a membrane that is constructed within the frame portion and has sensitivity as sensor, and the plurality of sensor elements are disposed in a planar shape in a state that the frame pieces in adjacent sensor elements are shared. The membrane has covexoconcave shape in which rectangular concave portions and rectangular convex portions are disposed in a web shape.
摘要翻译：传感器阵列具有多个传感器元件，每个传感器元件具有矩形框架形框架部分，该框架部分通过连接多个框架件和构成在框架部分内的膜并且具有作为传感器的灵敏度而形成，并且多个传感器元件在相邻的传感器元件中的框架片共享的状态下被布置成平面形状。膜具有凸起形状，其中矩形凹部和矩形凸部以网状形状设置。

6. 发明申请

US20130248995A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130248995A1
公开(公告)日：2013-09-26
申请号：US13607533
申请日：2012-09-07
申请人： Tatsuya NISHIWAKI , Tsuyoshi Ota , Norio Yasuhara , Masatoshi Arai , Takahiro Kawano
发明人： Tatsuya NISHIWAKI , Tsuyoshi Ota , Norio Yasuhara , Masatoshi Arai , Takahiro Kawano
IPC分类号： H01L29/78 , H01L21/82 , H01L27/088
CPC分类号： H01L29/7827 , H01L21/82 , H01L27/088 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/41775 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device includes a first semiconductor layer of a first conductivity type, a base layer of a second conductivity type placed above the first semiconductor layer, a second semiconductor layer of the first conductivity type placed above the base layer, multiple gate electrodes having upper end is positioned above the upper surface of the base layer, a lower end positioned below the bottom of the base layer, and contacting the first semiconductor layer, the second semiconductor layer, and the base layer through a gate insulating film, insulating component arranged above the gate electrode in which the upper surface is positioned below the upper surface of the second semiconductor layer, and a conductive layer covering the second semiconductor layer from the upper end to the bottom end.
摘要翻译：半导体器件包括第一导电类型的第一半导体层，位于第一半导体层上方的第二导电类型的基极层，位于基极层之上的第一导电类型的第二半导体层，具有上端的多个栅电极位于所述基底层的上表面的上方，位于所述基底层的底部下方的下端，并且通过栅极绝缘膜与所述第一半导体层，所述第二半导体层和所述基底层接触，栅电极，其上表面位于第二半导体层的上表面下方，以及导电层，其从上端到底端覆盖第二半导体层。

7. 发明授权

US07910440B2 Semiconductor device and method for making the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07910440B2
公开(公告)日：2011-03-22
申请号：US11968403
申请日：2008-01-02
申请人： Tsuyoshi Ohta , Takahiro Kawano
发明人： Tsuyoshi Ohta , Takahiro Kawano
IPC分类号： H01L21/336
CPC分类号： H01L29/66727 , H01L29/0661 , H01L29/66734 , H01L29/7811 , H01L29/7813
摘要： A semiconductor device includes: a first trench that is formed in a semiconductor substrate; a gate oxide film that is formed on a surface of the first trench; and a trench gate electrode that is formed so as to bury the first trench via the gate oxide film. The semiconductor device also includes: a second trench that is formed in the semiconductor substrate with a width wider than the width of the first trench; and a terminal-embedded insulation layer that is formed so as to bury the second trench. The semiconductor device further includes: a third trench that is formed in the semiconductor substrate with a width wider than the width of the second trench; and a trench contact electrode that is formed so as to bury the third trench.
摘要翻译：半导体器件包括：形成在半导体衬底中的第一沟槽; 形成在所述第一沟槽的表面上的栅极氧化膜; 以及沟槽栅极电极，其形成为通过栅极氧化膜掩埋第一沟槽。半导体器件还包括：形成在半导体衬底中的宽度比第一沟槽的宽度宽的第二沟槽; 以及形成为埋入第二沟槽的端子嵌入式绝缘层。半导体器件还包括：第三沟槽，其形成在半导体衬底中，宽度大于第二沟槽的宽度; 以及形成为埋入第三沟槽的沟槽接触电极。

8. 发明申请

US20090032875A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090032875A1
公开(公告)日：2009-02-05
申请号：US12185630
申请日：2008-08-04
申请人： Yusuke KAWAGUCHI , Kazuya Nakayama , Tsuyoshi Ohta , Takeshi Uchihara , Takahiro Kawano , Yuji Kato
发明人： Yusuke KAWAGUCHI , Kazuya Nakayama , Tsuyoshi Ohta , Takeshi Uchihara , Takahiro Kawano , Yuji Kato
IPC分类号： H01L29/00
CPC分类号： H01L29/7813 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/7811
摘要： There is provided a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the first conductivity type; a semiconductor region of the first conductivity type selectively provided on a front surface portion of the second semiconductor layer of the second conductivity type; a first main electrode provided in contact with a surface of the semiconductor region; a second main electrode provided on a side of the first semiconductor layer of the first conductivity type, the side being opposite to the surface on which the second semiconductor layer of the second conductivity type is provided; a gate wiring provided on the second semiconductor layer of the second conductivity type around an element region in which the semiconductor region is provided; a trench penetrating the second semiconductor layer of the second conductivity type to reach the first semiconductor layer of the first conductivity type, and also extending under the element region and the gate wiring; a gate electrode provided inside the trench in the element region with a gate insulating film interposed in between; and a gate electrode lead portion provided inside the trench under the gate wiring with the gate insulating film interposed in between, and contacting the gate wiring and the gate electrode.
摘要翻译：提供一种半导体器件，包括：第一导电类型的第一半导体层; 设置在第一导电类型的第一半导体层上的第二导电类型的第二半导体层; 选择性地设置在第二导电类型的第二半导体层的前表面部分上的第一导电类型的半导体区域; 设置成与所述半导体区域的表面接触的第一主电极; 设置在第一导电类型的第一半导体层的一侧的第二主电极，与设置有第二导电类型的第二半导体层的表面相对的一侧; 围绕设置有半导体区域的元件区域设置在第二导电类型的第二半导体层上的栅极布线; 穿过第二导电类型的第二半导体层的沟槽到达第一导电类型的第一半导体层，并且还在元件区域和栅极布线之下延伸; 设置在所述元件区域的所述沟槽内部的栅电极，其间插入有栅极绝缘膜; 以及栅极引线部分，其设置在栅极布线下方的沟槽内部，栅极绝缘膜介于其间并与栅极布线和栅电极接触。

9. 发明申请

US20080112478A1 Wireless communication apparatus having equalizer 有权
标题翻译：具有均衡器的无线通信装置
公开(公告)号：US20080112478A1
公开(公告)日：2008-05-15
申请号：US11979797
申请日：2007-11-08
申请人： Takahiro Kawano
发明人： Takahiro Kawano
IPC分类号： H03H7/30
CPC分类号： H04L25/03159 , H04L2025/03414
摘要： Receiving a transmission line estimation sequence, a wireless communication apparatus generates a transmission line characteristic estimation value for each of a plurality of sub-carriers and smoothes the transmission line characteristic estimation value of a target sub-carrier to be processed and the transmission line characteristic estimation value of its adjacent sub-carrier. The apparatus includes a determination unit for determining whether or not the adjacent sub-carrier, is a null sub-carrier and a smoothing unit for smoothing the transmission line characteristic estimation value of the target sub-carrier by excluding the transmission line characteristic estimation value of the adjacent sub-carrier determined as a null carrier by the determination unit.
摘要翻译：接收传输线估计序列，无线通信装置为多个副载波中的每一个生成传输线特性估计值，并对待处理的目标副载波的传输线特性估计值进行平滑化，并且传输线特性估计其相邻副载波的值。该装置包括用于确定相邻副载波是否为空子载波的确定单元和用于通过排除目标副载波的传输线特性估计值来平滑化的传输线特性估计值的平滑单元，所述相邻子载波由所述确定单元确定为空载波。

10. 发明授权

US06919249B2 Semiconductor device and its manufacturing method comprising a trench gate 失效
标题翻译：半导体器件及其制造方法包括沟槽栅极
公开(公告)号：US06919249B2
公开(公告)日：2005-07-19
申请号：US10778072
申请日：2004-02-17
申请人： Takahiro Kawano , Tatsuo Yoneda , Hirobumi Matsuki
发明人： Takahiro Kawano , Tatsuo Yoneda , Hirobumi Matsuki
IPC分类号： H01L21/336 , H01L29/08 , H01L29/417 , H01L29/78 , H01L21/8238
CPC分类号： H01L29/086 , H01L29/0847 , H01L29/41766 , H01L29/7802 , H01L29/7813
摘要： A semiconductor device comprises a semiconductor layer of a first conductivity type (2), a base region (3) formed proximal to the semiconductor layer, a source region (4) selectively placed over the base region, trenches (T), a gate insulating layer (7) and a gate electrode (6) provided on an inner wall of each of the trenches, and a source electrode (9) connected to the source region. The source region is higher in impurity concentration in a contact (4a) with the source electrode than in a contact with the gate insulating layer, and it is also higher in impurity concentration in the contact (4a) with the source electrode than in a contact with the base region.
摘要翻译：半导体器件包括第一导电类型（2）的半导体层，靠近半导体层形成的基极区域（3），选择性地放置在基极区域上的源极区域（4），沟槽（T），绝缘栅极层（7）和设置在每个沟槽的内壁上的栅电极（6）以及连接到源极区的源电极（9）。源极区域在与源极电极的接触（4a）中的杂质浓度高于与栅极绝缘层接触的杂质浓度，并且与源极电极的接触（4a）中的杂质浓度也高于在与基地区的联系。

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