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1. 发明申请

US20060030097A1 Methods of forming different gate structures in NMOS and PMOS regions and gate structures so formed 失效
标题翻译：在NMOS和PMOS区域中形成不同栅极结构的方法和如此形成的栅极结构
公开(公告)号：US20060030097A1
公开(公告)日：2006-02-09
申请号：US11183651
申请日：2005-07-18
申请人： Taek-Soo Jeon , Yu-Gyun Shin , Sang-Bom Kang , Hong-Bae Park , Hag-Ju Cho , Hye-Lan Lee , Beom-Jun Jin , Seong-Geon Park
发明人： Taek-Soo Jeon , Yu-Gyun Shin , Sang-Bom Kang , Hong-Bae Park , Hag-Ju Cho , Hye-Lan Lee , Beom-Jun Jin , Seong-Geon Park
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate insulating layer in the first and second regions. A metal silicide gate layer can be formed directly on the high-k gate insulating layer in the first region and avoiding forming the metal-silicide in the second region. Related gate structures are also disclosed.
摘要翻译：在集成电路器件中形成晶体管栅结构的方法可以包括在包括PMOS晶体管的第一区域的衬底上形成高k栅极绝缘层，以及包括NMOS晶体管的第二区域。可以在第一和第二区域的高k栅极绝缘层上形成多晶硅栅极层。可以在第一区域中的高k栅极绝缘层上直接形成金属硅化物栅极层，并且避免在第二区域中形成金属硅化物。还公开了相关门结构。

2. 发明授权

US07399670B2 Methods of forming different gate structures in NMOS and PMOS regions and gate structures so formed 失效
标题翻译：在NMOS和PMOS区域中形成不同栅极结构的方法和如此形成的栅极结构
公开(公告)号：US07399670B2
公开(公告)日：2008-07-15
申请号：US11183651
申请日：2005-07-18
申请人： Taek-Soo Jeon , Yu-Gyun Shin , Sang-Bom Kang , Hong-Bae Park , Hag-Ju Cho , Hye-Lan Lee , Beom-Jun Jin , Seong-Geon Park
发明人： Taek-Soo Jeon , Yu-Gyun Shin , Sang-Bom Kang , Hong-Bae Park , Hag-Ju Cho , Hye-Lan Lee , Beom-Jun Jin , Seong-Geon Park
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823842
摘要： A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate insulating layer in the first and second regions. A metal silicide gate layer can be formed directly on the high-k gate insulating layer in the first region and avoiding forming the metal-silicide in the second region. Related gate structures are also disclosed.
摘要翻译：在集成电路器件中形成晶体管栅结构的方法可以包括在包括PMOS晶体管的第一区域的衬底上形成高k栅极绝缘层，以及包括NMOS晶体管的第二区域。可以在第一和第二区域的高k栅极绝缘层上形成多晶硅栅极层。可以在第一区域中的高k栅极绝缘层上直接形成金属硅化物栅极层，并且避免在第二区域中形成金属硅化物。还公开了相关门结构。

3. 发明申请

US20080023765A1 Semiconductor Devices and Methods of Fabricating the Same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080023765A1
公开(公告)日：2008-01-31
申请号：US11756122
申请日：2007-05-31
申请人： Taek-Soo Jeon , In-Sang Kang , Sang-Bom Kang , Hong-Bae Park , Hag-Ju Cho , Hye-Lan Lee
发明人： Taek-Soo Jeon , In-Sang Kang , Sang-Bom Kang , Hong-Bae Park , Hag-Ju Cho , Hye-Lan Lee
IPC分类号： H01L27/01 , H01L21/00
CPC分类号： H01L29/78 , H01L21/28044 , H01L21/28088 , H01L21/823828 , H01L29/42372 , H01L29/4966
摘要： Provided are semiconductor devices and methods of fabricating the semiconductor devices. Embodiments of such methods may include sequentially forming a gate insulation layer and a metal layer on a semiconductor substrate and etching the metal layer to form a metallic residue on the gate insulation layer. Such methods may also include monitoring an etch by-product to detect an etch endpoint for stopping the etching and forming a polysilicon layer on the gate insulation layer including the metallic residue.
摘要翻译：提供半导体器件和制造半导体器件的方法。这些方法的实施例可以包括在半导体衬底上依次形成栅极绝缘层和金属层，并蚀刻金属层以在栅极绝缘层上形成金属残留物。这样的方法还可以包括监测蚀刻副产物以检测用于停止蚀刻的蚀刻终点并在包括金属残留物的栅极绝缘层上形成多晶硅层。

4. 发明申请

US20060151826A1 Semiconductor device having a barrier layer and method of manufacturing the same 审中-公开
标题翻译：具有阻挡层的半导体器件及其制造方法
公开(公告)号：US20060151826A1
公开(公告)日：2006-07-13
申请号：US11326286
申请日：2006-01-06
申请人： Beom-Jun Jin , Hong-Bae Park , Seong-Geon Park , Yu-Gyun Shin , Sang-Bom Kang
发明人： Beom-Jun Jin , Hong-Bae Park , Seong-Geon Park , Yu-Gyun Shin , Sang-Bom Kang
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/823425 , H01L21/823437 , H01L27/11568
摘要： A semiconductor device may include a gate structure having a gate insulation layer formed on a substrate, and a gate electrode formed on the gate insulation layer. A composite barrier layer may be formed on the gate structure.
摘要翻译：半导体器件可以包括具有形成在衬底上的栅极绝缘层的栅极结构和形成在栅极绝缘层上的栅电极。可以在栅极结构上形成复合阻挡层。

5. 发明申请

US20070166931A1 Methods of Manufacturing A Semiconductor Device for Improving the Electrical Characteristics of A Dielectric Film 审中-公开
标题翻译：制造用于改善介质膜的电气特性的半导体器件的方法
公开(公告)号：US20070166931A1
公开(公告)日：2007-07-19
申请号：US11567971
申请日：2006-12-07
申请人： Hong-Bae Park , Hag-Ju Cho , Yu-Gyun Shin , Sang-Bom Kang
发明人： Hong-Bae Park , Hag-Ju Cho , Yu-Gyun Shin , Sang-Bom Kang
IPC分类号： H01L21/336
CPC分类号： H01L21/28194 , H01L21/28185 , H01L21/3105 , H01L29/513 , H01L29/517
摘要： A method of manufacturing a semiconductor device includes depositing a high-dielectric film on a semiconductor substrate and performing an oxygen plasma treatment on the high-dielectric film deposited on the semiconductor substrate. The method further includes forming an electrode on the oxygen-plasma treated high-dielectric film.
摘要翻译：制造半导体器件的方法包括在半导体衬底上沉积高电介质膜并对沉积在半导体衬底上的高电介质膜进行氧等离子体处理。该方法还包括在氧等离子体处理的高电介质膜上形成电极。

6. 发明申请

US20060189055A1 Method of forming a composite layer, method of manufacturing a gate structure by using the method of forming the composite layer and method of manufacturing a capacitor by using the method of forming the composite layer 审中-公开
标题翻译：复合层的形成方法，通过使用复合层的形成方法制造栅极结构的方法以及使用形成复合层的方法制造电容器的方法
公开(公告)号：US20060189055A1
公开(公告)日：2006-08-24
申请号：US11356399
申请日：2006-02-16
申请人： Hong-Bae Park , Hag-Ju Cho , Yu-Gyun Shin , Sang-Bom Kang
发明人： Hong-Bae Park , Hag-Ju Cho , Yu-Gyun Shin , Sang-Bom Kang
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/0228 , H01L21/02181 , H01L21/022 , H01L21/02274 , H01L21/28194 , H01L21/28202 , H01L21/3141 , H01L21/31645 , H01L29/40114 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： Methods of forming a composite layer, a gate structure and a capacitor are disclosed. In the methods, a first dielectric layer is atomic layer deposited on a substrate by using an oxidation gas and a first precursor gas that includes hafnium precursors. A second dielectric layer is then atomic layer deposited on the first dielectric layer by using a nitriding gas and a second precursor gas that includes hafnium precursors.
摘要翻译：公开了形成复合层，栅极结构和电容器的方法。在该方法中，第一电介质层通过使用氧化气体和包括铪前体的第一前体气体在原子层上沉积在衬底上。然后通过使用氮化气体和包括铪前体的第二前体气体将第二电介质层原子层沉积在第一介电层上。

7. 发明申请

US20060019501A1 Methods of forming a thin layer including hafnium silicon oxide using atomic layer deposition and methods of forming a gate structure and a capacitor including the same 审中-公开
标题翻译：使用原子层沉积形成包括氧化铪的薄层的方法和形成栅极结构的方法和包括其的电容器的方法
公开(公告)号：US20060019501A1
公开(公告)日：2006-01-26
申请号：US11180121
申请日：2005-07-13
申请人： Beom-Jun Jin , Hong-Bae Park , Sang-Bom Kang , Yu-Gyun Shin
发明人： Beom-Jun Jin , Hong-Bae Park , Sang-Bom Kang , Yu-Gyun Shin
IPC分类号： H01L21/44 , H01L21/31 , H01L21/26
CPC分类号： H01L21/02148 , C23C16/401 , C23C16/45531 , H01L21/02208 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L21/31608 , H01L21/31645 , H01L29/517
摘要： Methods of forming a thin film include applying a first reactant to a substrate, chemisorbing a first portion of the first reactant and physisorbing a second portion of the first reactant on the substrate, applying a first oxidizer to the substrate, chemically reacting the first oxidizer with the first portion of the first reactant to form a first solid material on the substrate, applying a second reactant to the first solid material, chemisorbing a first portion of the second reactant and physisorbing a second portion of the second reactant on the first solid material, applying a second oxidizer to the first solid material; and chemically reacting the second oxidizer with the first portion of the second reactant to form a second solid material on the first solid material.
摘要翻译：形成薄膜的方法包括将第一反应物施加到基底，化学吸收第一反应物的第一部分并在基底上吸附第一反应物的第二部分，将第一氧化剂施加到基底上，使第一氧化剂与所述第一反应物的第一部分在所述基底上形成第一固体材料，向所述第一固体材料施加第二反应物，化学吸附所述第二反应物的第一部分并在所述第一固体材料上吸附所述第二反应物的第二部分，将第二氧化剂施加到所述第一固体材料; 以及使所述第二氧化剂与所述第二反应物的第一部分化学反应以在所述第一固体材料上形成第二固体材料。

8. 发明申请

US20060013946A1 Methods of forming a thin film structure, and a gate structure and a capacitor including the thin film structure 审中-公开
标题翻译：形成薄膜结构的方法以及包括薄膜结构的栅极结构和电容器
公开(公告)号：US20060013946A1
公开(公告)日：2006-01-19
申请号：US11182893
申请日：2005-07-15
申请人： Hong-Bae Park , Sang-Bom Kang , Beom-Jun Jin , Yu-Gyun Shin
发明人： Hong-Bae Park , Sang-Bom Kang , Beom-Jun Jin , Yu-Gyun Shin
IPC分类号： C23C16/00 , B05D5/12
CPC分类号： H01L21/02148 , C23C16/401 , C23C16/45531 , C23C16/45553 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L21/31616 , H01L21/31645 , H01L29/517
摘要： A thin film structure is formed that includes hafnium silicon oxide using an atomic layer deposition process. A first reactant including tetrakis ethyl methyl amino hafnium (TEMAH) is introduced onto a substrate. A first portion of the first reactant is chemisorbed to the substrate, whereas a second portion of the first reactant is physorbed to the first portion of the first reactant. A first oxidant is provided onto the substrate. A first thin film including hafnium oxide is formed on the substrate by chemically reacting the first oxidant with the first portion of the first reactant. A second reactant including amino propyl tri ethoxy silane (APTES) is introduced onto the first thin film. A first portion of the second reactant is chemisorbed to the first thin film, whereas a second portion of the second reactant is physorbed to the first portion of the second reactant. A second oxidant is provided onto the first thin film. A second thin film including silicon oxide is formed on the first thin film by chemically reacting the second oxidant with the first portion of the second reactant.
摘要翻译：使用原子层沉积工艺形成包括氧化铪的薄膜结构。将包含四乙基甲基氨基铪（TEMAH）的第一反应物引入到基材上。第一反应物的第一部分被化学吸附到基底上，而第一反应物的第二部分被物理吸附到第一反应物的第一部分。第一氧化剂被提供到基底上。通过使第一氧化剂与第一反应物的第一部分发生化学反应，在衬底上形成包括氧化铪的第一薄膜。将包含氨基丙基三乙氧基硅烷（APTES）的第二反应物引入到第一薄膜上。第二反应物的第一部分被化学吸附到第一薄膜，而第二反应物的第二部分被物理吸附到第二反应物的第一部分。在第一薄膜上提供第二氧化剂。通过使第二氧化剂与第二反应物的第一部分化学反应，在第一薄膜上形成包括氧化硅的第二薄膜。

9. 发明申请

US20070032008A1 MOS semiconductor devices having polysilicon gate electrodes and high dielectric constant gate dielectric layers and methods of manufacturing such devices 审中-公开
标题翻译：具有多晶硅栅电极和高介电常数栅介电层的MOS半导体器件及其制造方法
公开(公告)号：US20070032008A1
公开(公告)日：2007-02-08
申请号：US11494100
申请日：2006-07-27
申请人： Hye-Min Kim , Yu-Gyun Shin , In-Sang Jeon , Sang-Bom Kang , Hong-Bae Park , Beom-Jun Jin
发明人： Hye-Min Kim , Yu-Gyun Shin , In-Sang Jeon , Sang-Bom Kang , Hong-Bae Park , Beom-Jun Jin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A semiconductor device includes a substrate divided into an NMOS region and a PMOS region, a first gate pattern formed on the PMOS region, and a second gate pattern formed on the NMOS region. The first gate pattern includes a first gate oxide layer pattern, a metal oxide layer pattern, a silicon nitride layer pattern and a first polysilicon layer pattern that are sequentially stacked. The second gate pattern includes a second oxide layer pattern and a second polysilicon layer pattern. Related methods are also provided.
摘要翻译：半导体器件包括分为NMOS区和PMOS区的衬底，形成在PMOS区上的第一栅极图案，以及形成在NMOS区上的第二栅极图案。第一栅极图案包括依次层叠的第一栅极氧化物层图案，金属氧化物层图案，氮化硅层图案和第一多晶硅层图案。第二栅极图案包括第二氧化物层图案和第二多晶硅层图案。还提供了相关方法。

10. 发明申请

US20070063295A1 Gate electrode, method of forming the same, transistor having the gate electrode, method of manufacturing the same, semiconductor device having the gate electrode and method of manufacturing the same 审中-公开
标题翻译：栅电极，其形成方法，具有栅电极的晶体管，其制造方法，具有栅电极的半导体器件及其制造方法
公开(公告)号：US20070063295A1
公开(公告)日：2007-03-22
申请号：US11522343
申请日：2006-09-18
申请人： In-Sang Jeon , Yu-Gyun Shin , Sang-Bom Kang , Hong-Bae Park , Hye-Min Kim , Beom-Jun Jin
发明人： In-Sang Jeon , Yu-Gyun Shin , Sang-Bom Kang , Hong-Bae Park , Hye-Min Kim , Beom-Jun Jin
IPC分类号： H01L29/94
CPC分类号： H01L29/4983 , H01L21/28088 , H01L21/28194 , H01L21/823828 , H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/518 , H01L29/78
摘要： Example embodiments relate to a gate electrode, a method of forming the gate electrode, a transistor having the gate electrode, a method of manufacturing the transistor, a semiconductor device having the transistor and a method of manufacturing the semiconductor device. The gate electrode may include an embossing structure including a metal or a metal compound and having a first work function and a conductive layer pattern having a second work function formed on the embossing structure. A work function of the gate electrode may be adjusted between a work function of the embossing structure and a work function of the conductive layer pattern formed on the embossing structure. An NMOS transistor and a PMOS transistor having different work functions respectively may be formed on a substrate.
摘要翻译：示例性实施例涉及栅电极，形成栅电极的方法，具有栅电极的晶体管，制造晶体管的方法，具有晶体管的半导体器件和制造半导体器件的方法。栅电极可以包括包括金属或金属化合物并具有第一功函数的压花结构和在压花结构上形成的具有第二功函数的导电层图案。可以在压花结构的功函数和形成在压花结构上的导电层图案的功函数之间调整栅电极的功函数。可以在衬底上形成具有不同功函数的NMOS晶体管和PMOS晶体管。

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