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1. 发明申请

US20140343249A1 CELL KILLING FUSION PEPTIDE EXHIBITING TUMOR CELL-SPECIFIC NECROSIS INDUCTION AND TUMOR REGRESSION 审中-公开
标题翻译：细胞杀伤融合蛋白展示肿瘤细胞特异性坏死因子诱导和肿瘤回归
公开(公告)号：US20140343249A1
公开(公告)日：2014-11-20
申请号：US14361891
申请日：2011-12-15
申请人： Tae-Hyoung Kim , Ae Ran Moon , Ji Young Kim
发明人： Tae-Hyoung Kim , Ae Ran Moon , Ji Young Kim
IPC分类号： C07K7/08 , C07K16/18
CPC分类号： C07K7/08 , C07K14/4747 , C07K16/18 , C07K2319/07 , C07K2319/33
摘要： A cell-killing peptide, more specifically a cell-killing CKP fusion peptide (CTD7:CKP) is disclosed, wherein a cell-killing peptide (CKP) comprising 10 amino acids in MTD of Noxa protein causing cell death, and 7 amino acids targeting a cancer cell are fused. The cell-killing CKP fusion peptide induces strong cell necrosis at various cancer cell lines (HeLa, HCT116, MCF-7, A549, BJAB, CT26, PC3 and the like) and shows strong tumor regression effect at a mouse tumor model using experimental animals, but does not show apoptosis at normal cells. Therefore, it can be broadly used to human body for treating various diseases requiring cell death, particularly, as an anti-cancer drug.
摘要翻译：公开了细胞杀伤肽，更具体地是细胞杀伤CKP融合肽（CTD7：CKP），其中包含导致细胞死亡的Noxa蛋白的MTD中的10个氨基酸的细胞杀伤肽（CKP）和靶向的7个氨基酸癌细胞融合。细胞杀伤CKP融合肽在各种癌细胞系（HeLa，HCT116，MCF-7，A549，BJAB，CT26，PC3等）上诱导强烈的细胞坏死，并且在使用实验动物的小鼠肿瘤模型上显示出强烈的肿瘤消退效应，但在正常细胞中不显示凋亡。因此，可以广泛用于人体治疗需要细胞死亡的各种疾病，特别是作为抗癌药物。

2. 发明授权

US08877889B2 Tumor cell-killing peptides 有权
标题翻译：肿瘤细胞杀伤肽
公开(公告)号：US08877889B2
公开(公告)日：2014-11-04
申请号：US13393394
申请日：2010-08-16
申请人： Tae-Hyoung Kim
发明人： Tae-Hyoung Kim
IPC分类号： C07K7/00 , C07K14/47 , A61K38/00
CPC分类号： C07K14/4747 , A61K38/00
摘要： The present invention provides a tumor cell-killing peptide and a pharmaceutical composition for treating a cancer. The tumor cell-killing peptide of the present invention selectively homes into tumor cells so that it can induce the death of tumor cells effectively while minimizing the harming of normal cell.
摘要翻译：本发明提供了一种肿瘤细胞杀伤肽和用于治疗癌症的药物组合物。本发明的肿瘤细胞杀伤肽选择性地置入肿瘤细胞中，使得其可以有效地诱导肿瘤细胞的死亡，同时最小化正常细胞的损伤。

3. 发明授权

US06947336B2 Semiconductor device with impedance control circuit 失效
标题翻译：具有阻抗控制电路的半导体器件
公开(公告)号：US06947336B2
公开(公告)日：2005-09-20
申请号：US10410453
申请日：2003-04-08
申请人： Tae-Hyoung Kim , Uk-Rae Cho , Nam-Seog Kim
发明人： Tae-Hyoung Kim , Uk-Rae Cho , Nam-Seog Kim
IPC分类号： H03K19/0175 , G11C7/10 , G11C11/401 , G11C16/04
CPC分类号： G11C7/1057 , G11C7/1051 , G11C2207/105
摘要： A semiconductor device includes an output impedance control circuit, connected to a ZQ pad and an output buffer circuit, for controlling an impedance of the output buffer circuit according to an impedance of an external resistor connected with the ZQ pad.
摘要翻译：半导体器件包括连接到ZQ焊盘和输出缓冲电路的输出阻抗控制电路，用于根据与ZQ焊盘连接的外部电阻器的阻抗来控制输出缓冲电路的阻抗。

4. 发明授权

US06930508B2 Integrated circuit with on-chip termination 有权
标题翻译：具有片上终端的集成电路
公开(公告)号：US06930508B2
公开(公告)日：2005-08-16
申请号：US10626015
申请日：2003-07-24
申请人： Nam-Seog Kim , Uk-Rae Cho , Tae-Hyoung Kim
发明人： Nam-Seog Kim , Uk-Rae Cho , Tae-Hyoung Kim
IPC分类号： H03H11/40 , H03B1/00 , H03K19/003 , H04L25/02
CPC分类号： H04L25/0278
摘要： There is provided an integrated circuit which performs data input/output operations through a transmission line with a predetermined impedance. The integrated circuit includes a driver having a plurality of driving units, in which the driving units input/output data from/to the transmission line, and a controller for inputting an output data signal and applying a plurality of control signals to the driver, in which the control signals are generated in response to an output activation signal and impedance code signals related to states of the impedance. At least one driving unit is driven in response to the control signals, and the driver includes an on-chip termination circuit connected to an input buffer.
摘要翻译：提供了通过具有预定阻抗的传输线执行数据输入/输出操作的集成电路。集成电路包括具有多个驱动单元的驱动器，其中驱动单元从/向传输线输入/输出数据，以及用于输入输出数据信号并将多个控制信号施加到驾驶员的控制器，其响应于与阻抗状态相关的输出激活信号和阻抗代码信号而产生控制信号。响应于控制信号驱动至少一个驱动单元，并且驱动器包括连接到输入缓冲器的片上终端电路。

5. 发明授权

US08819790B2 Cooperation method and system between send mechanism and IPSec protocol in IPV6 environment 有权
标题翻译： IPV6环境下的发送机制与IPSec协议的协作方法和系统
公开(公告)号：US08819790B2
公开(公告)日：2014-08-26
申请号：US12040355
申请日：2008-02-29
申请人： Young-Ik Eom , Kwang-Sun Ko , Hyun-Su Jang , Hyun-jin Cho , Yong-Woo Jung , Hyun-Woo Choi , Gye-Hyeon Gyeong , Jung-Hwan Choi , Zhen Zhao , Tae-Hyoung Kim , Youn-Woo Kim
发明人： Young-Ik Eom , Kwang-Sun Ko , Hyun-Su Jang , Hyun-jin Cho , Yong-Woo Jung , Hyun-Woo Choi , Gye-Hyeon Gyeong , Jung-Hwan Choi , Zhen Zhao , Tae-Hyoung Kim , Youn-Woo Kim
IPC分类号： H04L9/32 , G06F21/00 , H04L29/06
CPC分类号： H04L63/164
摘要： The present invention relates to a method of embodying a cooperation system between SEND and IPSec in an IPv6 environment. The cooperation system between SEND and IPSec in accordance with the present invention includes: receiving an authentication completion report message including a first IP address of a host whose authentication is completed by the SEND; generating new authentication information corresponding to the host and storing the new authentication information in a temporary storage area, if authentication information for the host is not present in the temporary storage area, wherein the authentication information includes the first IP address; and if an authentication check request message including a second IP address is received from the IPSec, checking whether the second IP address is present in the temporary storage area, and sending the result of checking to the IPSec. The present invention allows the authentication information shared between SEND and IPSec in a mobile environment, where the network is frequently accessed, enabling IPSec secure communication at a lower cost.
摘要翻译：本发明涉及在IPv6环境中体现SEND与IPSec之间的协作系统的方法。根据本发明的SEND和IPSec之间的协作系统包括：接收认证完成报告消息，该消息包括通过SEND完成认证的主机的第一IP地址; 生成与所述主机对应的新认证信息，并将所述新认证信息存储在临时存储区域中，如果所述主机的认证信息不存在于所述临时存储区域中，则所述认证信息包括所述第一IP地址; 并且如果从IPSec接收到包含第二IP地址的认证检查请求消息，则检查该临时存储区域中是否存在第二IP地址，并向IPSec发送检查结果。本发明允许在经常访问网络的移动环境中在SEND和IPSec之间共享的认证信息以更低的成本实现IPSec安全通信。

6. 发明授权

US07586104B2 Non-heating type fluid sterilizing apparatus 失效
标题翻译：非加热型流体灭菌装置
公开(公告)号：US07586104B2
公开(公告)日：2009-09-08
申请号：US11649582
申请日：2007-01-04
申请人： Tae-Hyoung Kim
发明人： Tae-Hyoung Kim
IPC分类号： C02F1/32 , A61L2/10
CPC分类号： A61L2/0011 , A61L2/0088 , A61L2/10 , A61L2/24
摘要： A non-heating type fluid sterilizing apparatus can efficiently sterilize a fluid having high turbidity and a large quantity of solid matter or a fluid such as blood having low transmissivity of ultraviolet radiation, as well as sterilize either a single fluid in large quantity or various fluids in small quantity. The non-heating type fluid sterilizing apparatus includes a cooling tank integrally connected with a coolant inlet and a coolant outlet in order to introduce, store, and discharge a coolant; a plurality of supporting frames supporting the cooling tank; a plurality of ultraviolet lamps stacked vertically between the opposite supporting frames; a plurality of quartz tubes having the ultraviolet lamps housed therein, respectively; a fluid drainpipe installed across the cooling tank so as to be perpendicular to the ultraviolet lamps; and a spiral tube installed on an outer circumference of the fluid drainpipe, and having a fluid inlet into which a fluid flows, a tube winding, and a fluid outlet connected to the fluid drainpipe.
摘要翻译：非加热型流体灭菌装置能够高效地对具有高浊度的液体和大量的固体物质或具有低透射率的紫外线辐射的血液等的流体进行灭菌，并且对大量的单一流体或各种流体进行灭菌少量。非加热型流体灭菌装置包括与冷却剂入口和冷却剂出口一体连接的冷却罐，以便引入，储存和排出冷却剂; 支撑冷却箱的多个支撑框架; 在相对的支撑框架之间垂直堆叠的多个紫外线灯; 分别容纳有紫外灯的多个石英管; 一个安装在冷却箱上的流体排水管，以便垂直于紫外线灯; 以及螺旋管，其安装在流体排水管的外周上，并且具有流体流入的流体入口，管绕组和连接到流体排水管的流体出口。

7. 发明授权

US06952363B2 Semiconductor memory device with selectively connectable segmented bit line member and method of driving the same 有权
标题翻译：具有可选择地连接的分段位线构件的半导体存储器件及其驱动方法
公开(公告)号：US06952363B2
公开(公告)日：2005-10-04
申请号：US10785185
申请日：2004-02-25
申请人： Tae-Joong Song , Tae-Hyoung Kim
发明人： Tae-Joong Song , Tae-Hyoung Kim
IPC分类号： G11C11/41 , G11C7/00 , G11C7/12 , G11C7/18 , G11C8/12 , G11C8/16 , G11C11/00 , G11C11/413
CPC分类号： G11C7/12 , G11C7/18 , G11C8/12
摘要： A semiconductor memory device, that reduces load capacitance of write-only bit lines, may include: a first bit cell array block, in which bit cells thereof are defined by intersections of first bit lines and first word lines, the first bit lines being arranged as pairs of first signal lines and second signal lines, respectively; a second bit cell array block, in which bit cells thereof are defined by intersections of second bit lines and second word lines, the second bit lines being arranged as pairs of third signal lines and the second signal lines; respectively; a block division circuit operable to generate and output block division control signals; and a write bit line divider circuit operable to either open-circuit or connect together the first signal lines and the third signal lines, respectively, according to the block division control signals.
摘要翻译：减少只写位线的负载电容的半导体存储器件可以包括：第一位单元阵列块，其中位单元由第一位线和第一字线的交点限定，第一位线被布置分别作为第一信号线和第二信号线的对; 第二位单元阵列块，其中位单元由第二位线和第二字线的交点限定，第二位线被布置为第三信号线和第二信号线对; 分别; 块分割电路，用于产生和输出块分割控制信号; 以及写位线分频器电路，其可操作以分别根据块分割控制信号来开路或连接第一信号线和第三信号线。

8. 发明授权

US06933758B2 Synchronous mirror delay circuit with adjustable locking range 失效
标题翻译：同步镜延时电路具有可调锁定范围
公开(公告)号：US06933758B2
公开(公告)日：2005-08-23
申请号：US10308453
申请日：2002-12-03
申请人： Tae-Hyoung Kim , Yong-Jin Yoon , Nam-Seog Kim , Kwang-Jin Lee
发明人： Tae-Hyoung Kim , Yong-Jin Yoon , Nam-Seog Kim , Kwang-Jin Lee
IPC分类号： G06F1/12 , G06F1/10 , H03K5/15 , H03L7/00 , H03L7/081 , H03L7/087
CPC分类号： H03L7/0814 , H03L7/087
摘要： A synchronous mirror delay circuit comprises a delay monitor circuit for delaying a reference clock signal from a clock buffer circuit. A forward delay array sequentially delays an output clock signal of the delay monitor circuit to generate delay clock signals, and the mirror control circuit detects a delay clock signal synchronized with the reference clock signal among the delay clock signals. A backward delay array delays a clock signal delayed by the mirror control circuit, and a clock driver receives an output clock signal of the backward delay array to generate the internal clock signal. A locking range control circuit controls a delay time of each clock signal transferred to the delay monitor circuit by the amount of a delay time of each signal transferred to the clock driver when none of delay clock signals of the forward delay array is synchronized with the reference clock signal.
摘要翻译：同步镜延迟电路包括用于延迟来自时钟缓冲电路的参考时钟信号的延迟监视电路。正向延迟阵列顺序地延迟延迟监视电路的输出时钟信号以产生延迟时钟信号，并且镜像控制电路在延迟时钟信号中检测与参考时钟信号同步的延迟时钟信号。后向延迟阵列延迟由镜像控制电路延迟的时钟信号，并且时钟驱动器接收反向延迟阵列的输出时钟信号以产生内部时钟信号。当前向延迟阵列的延迟时钟信号与参考信号同步时，锁定范围控制电路控制传送到延迟监视器电路的每个时钟信号的延迟时间达到传送到时钟驱动器的每个信号的延迟时间量时钟信号。

9. 发明授权

US6075736A Semiconductor memory device with improved sense amplifier driver 有权
标题翻译：具有改善的读出放大器驱动器的半导体存储器件
公开(公告)号：US6075736A
公开(公告)日：2000-06-13
申请号：US179564
申请日：1998-10-27
申请人： Ha-Soo Kim , Jae-Goo Lee , Chang-Man Khang , Tae-Hyoung Kim
发明人： Ha-Soo Kim , Jae-Goo Lee , Chang-Man Khang , Tae-Hyoung Kim
IPC分类号： G11C11/41 , G06F9/34 , G11C7/06 , G11C11/401 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/108 , G11C7/02
CPC分类号： G11C7/06
摘要： The semiconductor memory according to the present invention employs a plurality of sense amplifier drivers which individually control the sense amplifiers, or control groups of sense amplifiers, in the semiconductor memory. More specifically, the sense amplifier drivers control whether associated sense amplifiers are connected to sense amplifier array input/output lines. In this manner fewer sense amplifiers are connected to the sense amplifier array input/output lines, reducing overall current consumption.
摘要翻译：根据本发明的半导体存储器采用多个读出放大器驱动器，其分别控制半导体存储器中的读出放大器或读出放大器的控制组。更具体地，读出放大器驱动器控制相关读出放大器是否连接到读出放大器阵列输入/输出线。以这种方式，较少的读出放大器连接到读出放大器阵列输入/输出线，从而降低总体电流消耗。

10. 发明授权

US5877990A Semiconductor memory device and method 失效
标题翻译：半导体存储器件及方法
公开(公告)号：US5877990A
公开(公告)日：1999-03-02
申请号：US953342
申请日：1997-10-17
申请人： Tae-Hyoung Kim
发明人： Tae-Hyoung Kim
IPC分类号： G11C11/407 , G11C7/10 , G11C7/00
CPC分类号： G11C7/106 , G11C7/103 , G11C7/1051 , G11C7/1069
摘要： A semiconductor memory device and method are provided that enhance data output speed of a DRAM or the like by reducing the time difference between the data output operation from a preceding word line and the data output operation from a succeeding word line. The semiconductor memory device includes a memory cell array arranged with multiple memory cells having a corresponding word line and a corresponding bit line, a row decoder for decoding a row address to select and activate a word line of the memory cell array and a sense amplifier for sensing and amplifying the data in a memory cell coupled to the activated word line when the data is applied to the corresponding bit line. The semiconductor further includes first and second latches respectively storing data using the sense amplifier taken from a memory cell coupled to a preceding activated word line and a succeeding activated word line. A switching block controls the data path between the sense amplifier and the first latch, or the sense amplifier and the second latch and a column decoder selects and applies the data stored in the first or second latch to a data bus. A data bus sense amplifier amplifies the data applied to the data bus before transmitting it to a data output buffer.
摘要翻译：提供了通过减少来自前一字线的数据输出操作与来自后续字线的数据输出操作之间的时间差来提高DRAM等的数据输出速度的半导体存储器件和方法。半导体存储器件包括一个存储单元阵列，该存储单元阵列具有多个具有对应字线和相应位线的存储单元，一行解码器，用于解码行地址以选择和激活存储单元阵列的字线;以及读出放大器，当将数据应用于对应的位线时，感测和放大耦合到激活的字线的存储器单元中的数据。半导体还包括第一和第二锁存器，其分别使用从耦合到先前激活字线和后续激活字线的存储器单元中获取的读出放大器存储数据。开关块控制读出放大器与第一锁存器或读出放大器和第二锁存器之间的数据路径，列解码器将存储在第一或第二锁存器中的数据选择并应用于数据总线。数据总线读出放大器在将数据总线发送到数据输出缓冲器之前放大应用于数据总线的数据。

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