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1. 发明授权

US06933758B2 Synchronous mirror delay circuit with adjustable locking range 失效
标题翻译：同步镜延时电路具有可调锁定范围
公开(公告)号：US06933758B2
公开(公告)日：2005-08-23
申请号：US10308453
申请日：2002-12-03
申请人： Tae-Hyoung Kim , Yong-Jin Yoon , Nam-Seog Kim , Kwang-Jin Lee
发明人： Tae-Hyoung Kim , Yong-Jin Yoon , Nam-Seog Kim , Kwang-Jin Lee
IPC分类号： G06F1/12 , G06F1/10 , H03K5/15 , H03L7/00 , H03L7/081 , H03L7/087
CPC分类号： H03L7/0814 , H03L7/087
摘要： A synchronous mirror delay circuit comprises a delay monitor circuit for delaying a reference clock signal from a clock buffer circuit. A forward delay array sequentially delays an output clock signal of the delay monitor circuit to generate delay clock signals, and the mirror control circuit detects a delay clock signal synchronized with the reference clock signal among the delay clock signals. A backward delay array delays a clock signal delayed by the mirror control circuit, and a clock driver receives an output clock signal of the backward delay array to generate the internal clock signal. A locking range control circuit controls a delay time of each clock signal transferred to the delay monitor circuit by the amount of a delay time of each signal transferred to the clock driver when none of delay clock signals of the forward delay array is synchronized with the reference clock signal.
摘要翻译：同步镜延迟电路包括用于延迟来自时钟缓冲电路的参考时钟信号的延迟监视电路。正向延迟阵列顺序地延迟延迟监视电路的输出时钟信号以产生延迟时钟信号，并且镜像控制电路在延迟时钟信号中检测与参考时钟信号同步的延迟时钟信号。后向延迟阵列延迟由镜像控制电路延迟的时钟信号，并且时钟驱动器接收反向延迟阵列的输出时钟信号以产生内部时钟信号。当前向延迟阵列的延迟时钟信号与参考信号同步时，锁定范围控制电路控制传送到延迟监视器电路的每个时钟信号的延迟时间达到传送到时钟驱动器的每个信号的延迟时间量时钟信号。

2. 发明授权

US06617894B2 Circuits and methods for generating internal clock signal of intermediate phase relative to external clock 失效
公开(公告)号：US06617894B2
公开(公告)日：2003-09-09
申请号：US10081359
申请日：2002-02-20
申请人： Yong-Jin Yoon , Uk-Rae Cho , Jung-Woo Park , Kwang-Jin Lee , Nam-Seog Kim
发明人： Yong-Jin Yoon , Uk-Rae Cho , Jung-Woo Park , Kwang-Jin Lee , Nam-Seog Kim
IPC分类号： H03L700
CPC分类号： G06F1/10 , H03K5/135
摘要： A circuit includes a clock buffer to generate an initial reference clock signal responsive to an external clock signal, a DMC to receive the initial reference clock signal, and an array of forward units to receive a signal from the DMC. The circuit also includes an array of back units that produces a back signal. The back signal is input in a clock driver to produce an internal clock signal. A delay element produces a delayed reference signal responsive to the initial reference clock signal. A plurality of MCCs receive an output of one of the forward units and the delayed reference clock signal. When one of the outputs of the forward units is synchronized with the delayed reference clock signal, one of the back units is thereby activated, which initiates generation of the back signal.

3. 发明授权

US07016257B2 Semiconductor memory device capable of generating variable clock signals according to modes of operation 失效
标题翻译：能够根据工作模式生成可变时钟信号的半导体存储器件
公开(公告)号：US07016257B2
公开(公告)日：2006-03-21
申请号：US10790262
申请日：2004-03-01
申请人： Nam-Seog Kim , Uk-Rae Cho , Yong-Jin Yoon
发明人： Nam-Seog Kim , Uk-Rae Cho , Yong-Jin Yoon
IPC分类号： G11C8/00
CPC分类号： G11C29/12015 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C29/14
摘要： A semiconductor memory device comprising: an array of memory cells; an address input circuit for receiving an external address in response to an address clock signal; a selecting circuit for selecting a memory cell in response to an address output from the address input circuit; a data output circuit for outputting the data read out from the selected memory cell in response to first and second data clock signals; and an internal clock generating circuit for generating the address clock signal and the first and second data clock signals in response to an external clock signal and a complementary clock signal thereof, wherein the address clock signal and the first and second data clock signals have twice the frequency (or half the period) of the external clock signal when in a test mode.
摘要翻译：一种半导体存储器件，包括：存储器单元阵列; 地址输入电路，用于响应于地址时钟信号接收外部地址; 选择电路，用于响应于从地址输入电路输出的地址来选择存储单元; 数据输出电路，用于响应于第一和第二数据时钟信号输出从所选存储单元读出的数据; 以及内部时钟发生电路，用于响应于外部时钟信号及其互补时钟信号产生地址时钟信号和第一和第二数据时钟信号，其中地址时钟信号和第一和第二数据时钟信号具有两倍在测试模式时外部时钟信号的频率（或一半周期）。

4. 发明申请

US20070139084A1 AMPLIFIER CIRCUIT HAVING CONSTANT OUTPUT SWING RANGE AND STABLE DELAY TIME 失效
标题翻译：具有恒定输出振荡范围和稳定延迟时间的放大器电路
公开(公告)号：US20070139084A1
公开(公告)日：2007-06-21
申请号：US11627794
申请日：2007-01-26
申请人： Nam-Seog KIM , Yong-Jin Yoon , Uk-Rae Cho
发明人： Nam-Seog KIM , Yong-Jin Yoon , Uk-Rae Cho
IPC分类号： H03K5/22
CPC分类号： H03K3/356139
摘要： Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third current to be the same as the amount of the first current although the level of the external reference signal is varied, such that the amplifier circuit and a circuit for receiving data can maintain a constant output swing range and a stable delay time irrespective of variations in the voltage levels of the external input signal or the external reference signal.
摘要翻译：提供了具有恒定的输出摆幅范围和稳定延迟时间的放大器电路，其中放大器电路包括第一偏置单元，第二偏置单元，比较单元和放大器单元，并且第一偏置单元响应内部具有预定电压电平的参考信号并且保持第一电流的量的恒定，并且第二偏置单元接收外部参考信号，响应于控制电压，并且将第二电流的量控制为与第第一电流和比较单元将第一节点的电压电平与第二节点的电压电平进行比较，并且根据比较结果控制控制电压的电压电平，并且放大器单元将电压电平具有外部参考信号电压电平的外部输入信号，放大并输出两个比较信号之间的电压差，响应控制电压，并控制尽管外部参考信号的电平变化，但是第三电流的量与第一电流的量相同，使得放大器电路和用于接收数据的电路可以保持恒定的输出摆幅范围和稳定的延迟时间，而不管外部输入信号或外部参考信号的电压电平的变化。

5. 发明申请

US20050146365A1 Apparatus for generating internal clock signal 失效
标题翻译：用于产生内部时钟信号的装置
公开(公告)号：US20050146365A1
公开(公告)日：2005-07-07
申请号：US11031129
申请日：2005-01-07
申请人： Nam-Seog Kim , Yong-Jin Yoon , Uk-Rae Cho
发明人： Nam-Seog Kim , Yong-Jin Yoon , Uk-Rae Cho
IPC分类号： G11C11/40 , G11C7/00 , G11C8/00 , G11C11/407 , H03K5/13 , H03K5/135 , H03L7/06 , H03L7/081
CPC分类号： H03L7/0812 , H03K5/133 , H03K5/135
摘要： An apparatus for generating an internal clock signal for acquisition of accurate synchronization is provided. The apparatus including: an input buffer for buffering the external clock signal to output a first reference clock signal; a delay compensation circuit for delaying the first reference clock signal; a forward delay array; a mirror control circuit comprising a plurality of phase detectors for detecting delayed clock signals synchronized with a second reference clock signal; a backward delay array; and an output buffer to generate an internal clock signal. An internal clock signal in accurate synchronization with the reference clock signal can be generated by minimizing the delay and distortion of the reference clock signal.
摘要翻译：提供一种用于产生用于获取精确同步的内部时钟信号的装置。该装置包括：输入缓冲器，用于缓冲外部时钟信号以输出第一参考时钟信号; 延迟补偿电路，用于延迟第一参考时钟信号; 前向延迟阵列镜控制电路，包括用于检测与第二参考时钟信号同步的延迟时钟信号的多个相位检测器; 后向延迟阵列以及产生内部时钟信号的输出缓冲器。可以通过最小化参考时钟信号的延迟和失真来产生与参考时钟信号精确同步的内部时钟信号。

6. 发明授权

US07400177B2 Amplifier circuit having constant output swing range and stable delay time 失效
标题翻译：放大器电路具有恒定的输出摆幅范围和稳定的延迟时间
公开(公告)号：US07400177B2
公开(公告)日：2008-07-15
申请号：US11627794
申请日：2007-01-26
申请人： Nam-Seog Kim , Yong-Jin Yoon , Uk-Rae Cho
发明人： Nam-Seog Kim , Yong-Jin Yoon , Uk-Rae Cho
IPC分类号： G11C7/00
CPC分类号： H03K3/356139
摘要： Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third current to be the same as the amount of the first current although the level of the external reference signal is varied, such that the amplifier circuit and a circuit for receiving data can maintain a constant output swing range and a stable delay time irrespective of variations in the voltage levels of the external input signal or the external reference signal.
摘要翻译：提供了具有恒定的输出摆幅范围和稳定延迟时间的放大器电路，其中放大器电路包括第一偏置单元，第二偏置单元，比较单元和放大器单元，并且第一偏置单元响应内部具有预定电压电平的参考信号并且保持第一电流的量的恒定，并且第二偏置单元接收外部参考信号，响应于控制电压，并且将第二电流的量控制为与第第一电流和比较单元将第一节点的电压电平与第二节点的电压电平进行比较，并且根据比较结果控制控制电压的电压电平，并且放大器单元将电压电平具有外部参考信号电压电平的外部输入信号，放大并输出两个比较信号之间的电压差，响应控制电压，并控制尽管外部参考信号的电平变化，但是第三电流的量与第一电流的量相同，使得放大器电路和用于接收数据的电路可以保持恒定的输出摆幅范围和稳定的延迟时间，而不管外部输入信号或外部参考信号的电压电平的变化。

7. 发明授权

US07187214B2 Amplifier circuit having constant output swing range and stable delay time 失效
标题翻译：放大器电路具有恒定的输出摆幅范围和稳定的延迟时间
公开(公告)号：US07187214B2
公开(公告)日：2007-03-06
申请号：US11071433
申请日：2005-03-03
申请人： Nam-Seog Kim , Yong-Jin Yoon , Uk-Rae Cho
发明人： Nam-Seog Kim , Yong-Jin Yoon , Uk-Rae Cho
IPC分类号： H03K5/22
CPC分类号： H03K3/356139
摘要： Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third current to be the same as the amount of the first current although the level of the external reference signal is varied, such that the amplifier circuit and a circuit for receiving data can maintain a constant output swing range and a stable delay time irrespective of variations in the voltage levels of the external input signal or the external reference signal.
摘要翻译：提供了具有恒定的输出摆幅范围和稳定延迟时间的放大器电路，其中放大器电路包括第一偏置单元，第二偏置单元，比较单元和放大器单元，并且第一偏置单元响应内部具有预定电压电平的参考信号并且保持第一电流的量的恒定，并且第二偏置单元接收外部参考信号，响应于控制电压，并且将第二电流的量控制为与第第一电流和比较单元将第一节点的电压电平与第二节点的电压电平进行比较，并且根据比较结果控制控制电压的电压电平，并且放大器单元将电压电平具有外部参考信号电压电平的外部输入信号，放大并输出两个比较信号之间的电压差，响应控制电压，并控制尽管外部参考信号的电平变化，但是第三电流的量与第一电流的量相同，使得放大器电路和用于接收数据的电路可以保持恒定的输出摆幅范围和稳定的延迟时间，而不管外部输入信号或外部参考信号的电压电平的变化。

8. 发明授权

US06992514B2 Synchronous mirror delay circuit and semiconductor integrated circuit device having the same 失效
标题翻译：同步镜延迟电路和具有该同步镜延迟电路的半导体集成电路器件
公开(公告)号：US06992514B2
公开(公告)日：2006-01-31
申请号：US10790601
申请日：2004-03-01
申请人： Nam-Seog Kim , Yong-Jin Yoon , Uk-Rae Cho
发明人： Nam-Seog Kim , Yong-Jin Yoon , Uk-Rae Cho
IPC分类号： H03L7/00
CPC分类号： H03K5/135
摘要： Disclosed is a synchronous mirror delay circuit for generating an internal clock signal synchronized with an external clock signal, comprising: a clock buffer circuit that generates a reference clock signal in response to the external clock signal; a delay monitor circuit that delays the reference clock signal; a forward delay array for delaying an output clock signal of the delay monitor circuit to generate delay clock signals; a mirror control circuit that receives the delay clock signals and the reference clock signal to detect one delay clock signal synchronized with the reference clock signal among the delay clock signals; a backward delay array that delays the delay clock signal detected by the mirror control circuit to output a synchronous clock signal; a delay circuit that delays an asynchronous clock signal output through the forward delay array; and a clock driving circuit that outputs the delayed asynchronous clock signal as the internal clock signal when the reference clock signal is not synchronized with one of the delay clock signals.
摘要翻译：公开了一种用于产生与外部时钟信号同步的内部时钟信号的同步镜延迟电路，包括：时钟缓冲电路，其响应于外部时钟信号产生参考时钟信号; 延迟监视电路，延迟参考时钟信号; 用于延迟延迟监视电路的输出时钟信号以产生延迟时钟信号的正向延迟阵列; 接收所述延迟时钟信号和所述参考时钟信号以在所述延迟时钟信号中检测与所述参考时钟信号同步的一个延迟时钟信号的镜像控制电路; 后延迟阵列，其延迟由所述镜控制电路检测到的延迟时钟信号，以输出同步时钟信号; 延迟电路，延迟通过前向延迟阵列输出的异步时钟信号; 以及时钟驱动电路，当所述参考时钟信号与所述延迟时钟信号之一不同步时，输出所述延迟异步时钟信号作为所述内部时钟信号。

9. 发明授权

US06661272B2 Digitally controllable internal clock generating circuit of semiconductor memory device and method for same 有权
公开(公告)号：US06661272B2
公开(公告)日：2003-12-09
申请号：US10041060
申请日：2002-01-07
申请人： Nam-Seog Kim , Yong-Jin Yoon
发明人： Nam-Seog Kim , Yong-Jin Yoon
IPC分类号： H03K300
CPC分类号： G11C7/222 , G11C7/22
摘要： An internal clock generating circuit of a semiconductor device includes: a delay chain having a plurality of delay units for generating multi-phase clocks by adjusting an input clock; a thermometer for outputting a thermometer code value in response to an input selection data; a multiplexer for selectively outputting one of a plurality of clocks input from the delay chain in response to the thermometer code value of the thermometer; and a pulse regenerator for outputting an adjusted internal clock by restoring a pulse form of the clock output from the multiplexer into its original state and controlling the delay thereof as much as desired.

10. 发明授权

US07154312B2 Apparatus for generating internal clock signal 失效
标题翻译：用于产生内部时钟信号的装置
公开(公告)号：US07154312B2
公开(公告)日：2006-12-26
申请号：US11031129
申请日：2005-01-07
申请人： Nam-Seog Kim , Yong-Jin Yoon , Uk-Rae Cho
发明人： Nam-Seog Kim , Yong-Jin Yoon , Uk-Rae Cho
IPC分类号： H03L7/00
CPC分类号： H03L7/0812 , H03K5/133 , H03K5/135
摘要： An apparatus for generating an internal clock signal for acquisition of accurate synchronization is provided. The apparatus including: an input buffer for buffering the external clock signal to output a first reference clock signal; a delay compensation circuit for delaying the first reference clock signal; a forward delay array; a mirror control circuit comprising a plurality of phase detectors for detecting delayed clock signals synchronized with a second reference clock signal; a backward delay array; and an output buffer to generate an internal clock signal. An internal clock signal in accurate synchronization with the reference clock signal can be generated by minimizing the delay and distortion of the reference clock signal.
摘要翻译：提供了一种用于产生用于获取精确同步的内部时钟信号的装置。该装置包括：输入缓冲器，用于缓冲外部时钟信号以输出第一参考时钟信号; 延迟补偿电路，用于延迟第一参考时钟信号; 前向延迟阵列镜控制电路，包括用于检测与第二参考时钟信号同步的延迟时钟信号的多个相位检测器; 后向延迟阵列以及产生内部时钟信号的输出缓冲器。可以通过最小化参考时钟信号的延迟和失真来产生与参考时钟信号精确同步的内部时钟信号。

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