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1. 发明授权

US06292042B1 Phase splitter 有权
标题翻译：分相器
公开(公告)号：US06292042B1
公开(公告)日：2001-09-18
申请号：US09295403
申请日：1999-04-21
申请人： Ha Soo Kim , Sung Ho Wang , Tae Hyung Kim
发明人： Ha Soo Kim , Sung Ho Wang , Tae Hyung Kim
IPC分类号： H03H1116
CPC分类号： H03K5/151
摘要： A phase splitter is disclosed for preventing a timing loss from a presentation timing mismatch of a clock signal of a phase equal to a reference signal and a clock signal of a phase inverted from the reference signal, including a semiconductor device for providing a signal of the same phase and a signal of an inverted phase with respect to a received reference signal, the semiconductor device including a first and a second transmission gates for receiving the reference signal and an inverted version of the received reference signal, and a third and a fourth transmission gates for receiving the reference sign, and the inverted version of that reference signal and for generating a signal having the same phase as the received reference signal and for providing that signal at the same time that the first and second transmission gates provide their output signal, the signals output by the first and second transmission gates having the same timing and opposite phase as the signal output by the third and fourth transmission gates with respect to the reference signal.
摘要翻译：公开了一种用于防止来自等于参考信号的相位的时钟信号的呈现定时失配的定时损失和与参考信号相反的相位的时钟信号的定时损耗，包括用于提供信号的信号的半导体器件相位相位和相对于接收的参考信号的反相信号，所述半导体器件包括用于接收参考信号的第一和第二传输门和所接收的参考信号的反相形式，以及第三和第四传输用于接收参考符号的门和该参考信号的反相版本，并用于产生具有与接收到的参考信号相同相位的信号，并且用于在第一和第二传输门提供其输出信号的同时提供该信号，由第一和第二传输门输出的信号具有与由t输出的信号相同的定时和相反相位他相对于参考信号的第三和第四传输门。

2. 发明授权

US08605534B2 Circuits, architectures, apparatuses, systems, algorithms, and methods for memory with multiple power supplies and/or multiple low power modes 有权
公开(公告)号：US08605534B2
公开(公告)日：2013-12-10
申请号：US12878703
申请日：2010-09-09
申请人： Winston Lee , Ha Soo Kim
发明人： Winston Lee , Ha Soo Kim
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C7/02 , G11C8/08
摘要： Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory. The method generally includes operating peripheral circuitry at a first voltage from a first power rail, operating a memory array at the first voltage or a second voltage, the memory array being coupled to a second power rail, coupling the first and second power rails during standard operating mode when the memory array operates at the first voltage, otherwise not coupling the first and second power rails, and reducing leakage in the memory array during a leakage reduction mode by reducing a voltage differential between a ground plane in the memory array and the second power rail.

3. 发明申请

US20110058439A1 Circuits, Architectures, Apparatuses, Systems, Algorithms, and Methods for Memory with Multiple Power Supplies and/or Multiple Low Power Modes 有权
标题翻译：具有多个电源和/或多个低功耗模式的存储器的电路，架构，设备，系统，算法和方法
公开(公告)号：US20110058439A1
公开(公告)日：2011-03-10
申请号：US12878703
申请日：2010-09-09
申请人： Winston LEE , Ha Soo KIM
发明人： Winston LEE , Ha Soo KIM
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C7/02 , G11C8/08
摘要： Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory. The method generally includes operating peripheral circuitry at a first voltage from a first power rail, operating a memory array at the first voltage or a second voltage, the memory array being coupled to a second power rail, coupling the first and second power rails during standard operating mode when the memory array operates at the first voltage, otherwise not coupling the first and second power rails, and reducing leakage in the memory array during a leakage reduction mode by reducing a voltage differential between a ground plane in the memory array and the second power rail.
摘要翻译：电路，架构，具有多个电源和/或多个低功耗模式的存储器的系统和方法。该电路通常包括以第一电压工作的外围电路，以第二电压操作的存储器阵列和经配置以在第一电压处从外围电路接收输入的平移电路，并且以第二电压向存储器阵列提供输出，所述翻译电路还被配置为防止在所述存储器的标准操作模式期间的泄漏。该方法通常包括以来自第一电源轨的第一电压操作外围电路，以第一电压或第二电压操作存储器阵列，存储器阵列耦合到第二电源轨，在标准期间耦合第一和第二电源轨当存储器阵列以第一电压工作时，否则不耦合第一和第二电源轨，并且通过减小存储器阵列中的接地平面与第二电压之间的电压差来减少泄漏减少模式期间的存储器阵列的泄漏电力轨道

4. 发明授权

US6075736A Semiconductor memory device with improved sense amplifier driver 有权
标题翻译：具有改善的读出放大器驱动器的半导体存储器件
公开(公告)号：US6075736A
公开(公告)日：2000-06-13
申请号：US179564
申请日：1998-10-27
申请人： Ha-Soo Kim , Jae-Goo Lee , Chang-Man Khang , Tae-Hyoung Kim
发明人： Ha-Soo Kim , Jae-Goo Lee , Chang-Man Khang , Tae-Hyoung Kim
IPC分类号： G11C11/41 , G06F9/34 , G11C7/06 , G11C11/401 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/108 , G11C7/02
CPC分类号： G11C7/06
摘要： The semiconductor memory according to the present invention employs a plurality of sense amplifier drivers which individually control the sense amplifiers, or control groups of sense amplifiers, in the semiconductor memory. More specifically, the sense amplifier drivers control whether associated sense amplifiers are connected to sense amplifier array input/output lines. In this manner fewer sense amplifiers are connected to the sense amplifier array input/output lines, reducing overall current consumption.
摘要翻译：根据本发明的半导体存储器采用多个读出放大器驱动器，其分别控制半导体存储器中的读出放大器或读出放大器的控制组。更具体地，读出放大器驱动器控制相关读出放大器是否连接到读出放大器阵列输入/输出线。以这种方式，较少的读出放大器连接到读出放大器阵列输入/输出线，从而降低总体电流消耗。

5. 发明授权

US09221297B2 Dual surface treated injection molding article and method of manufacturing the same 有权
标题翻译：双表面处理注塑制品及其制造方法
公开(公告)号：US09221297B2
公开(公告)日：2015-12-29
申请号：US13087494
申请日：2011-04-15
申请人： Ho-Soon Shin , Jong-Bae Park , Young-Jik Lee , Hyon-Myong Song , Ha-Soo Kim
发明人： Ho-Soon Shin , Jong-Bae Park , Young-Jik Lee , Hyon-Myong Song , Ha-Soo Kim
IPC分类号： B32B3/10 , B44F7/00 , B44F1/04 , C23C14/04
CPC分类号： B44F7/00 , B44F1/045 , C23C14/042 , Y10T428/24802 , Y10T428/24851 , Y10T428/24868 , Y10T428/24917
摘要： Disclosed are a dual surface-treated injection molding article, which is manufactured by dually surface-treating an injection molding substrate formed of a light-transmissive semi-transparent or transparent material in such a manner that a metallic appearance is expressed or any of a logo, a pattern, an ornamental design, and a picture is formed on each of inner and outer surfaces of the injection molding substrate, and a method of manufacturing the same.
摘要翻译：公开了一种双面表面处理的注射成型制品，其通过以透明的半透明或透明材料形成的注射成型基材以表面金属外观或标志的任何方式进行双面表面处理而制造在注射成型基板的内表面和外表面的每一个上形成图案，装饰设计和图片及其制造方法。

6. 发明申请

US20110253412A1 DUAL SURFACE TREATED INJECTION MOLDING ARTICLE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：双面处理注射成型品及其制造方法
公开(公告)号：US20110253412A1
公开(公告)日：2011-10-20
申请号：US13087494
申请日：2011-04-15
申请人： Ho-Soon SHIN , Jong-Bae PARK , Young-Jik LEE , Hyon-Myong SONG , Ha-Soo KIM
发明人： Ho-Soon SHIN , Jong-Bae PARK , Young-Jik LEE , Hyon-Myong SONG , Ha-Soo KIM
IPC分类号： H05K5/02 , B32B3/00 , B44C1/22
CPC分类号： B44F7/00 , B44F1/045 , C23C14/042 , Y10T428/24802 , Y10T428/24851 , Y10T428/24868 , Y10T428/24917
摘要： Disclosed are a dual surface-treated injection molding article, which is manufactured by dually surface-treating an injection molding substrate formed of a light-transmissive semi-transparent or transparent material in such a manner that a metallic appearance is expressed or any of a logo, a pattern, an ornamental design, and a picture is formed on each of inner and outer surfaces of the injection molding substrate, and a method of manufacturing the same.
摘要翻译：公开了一种双面表面处理的注射成型制品，其通过以透明的半透明或透明材料形成的注射成型基材以表面金属外观或标志的任何方式进行双面表面处理而制造在注射成型基板的内表面和外表面的每一个上形成图案，装饰设计和图片及其制造方法。

7. 发明申请

US20100247859A1 METHOD FOR FABRICATING INJECTION-MOLDED PRODUCT 审中-公开
标题翻译：用于制造注射成型产品的方法
公开(公告)号：US20100247859A1
公开(公告)日：2010-09-30
申请号：US12732453
申请日：2010-03-26
申请人： Sung-Sun PARK , Ha-Soo KIM , Hyon-Myong SONG , Seng-Ho AHN , Yong-Pil LIM , Sang-Beom KO
发明人： Sung-Sun PARK , Ha-Soo KIM , Hyon-Myong SONG , Seng-Ho AHN , Yong-Pil LIM , Sang-Beom KO
IPC分类号： B32B3/30 , B29C45/16 , B32B3/00
CPC分类号： B29C45/0053 , B29C2045/0079 , Y10T428/24355 , Y10T428/24612
摘要： Provided is a method for fabricating an injection-molded product, including a molding step for forming a semi-transparent or transparent injection-molded product with patterns formed on the surfaces thereof by injecting a material in an injection mold, a first base coating step for forming a base coating layer on the inner surface of the injection-molded product where the patterns are formed, and a clear coating step for forming a clear coating layer on an outer surface of the injection-molded product, in which the base coating layer is formed of a base coat having a color therein. Furthermore, a painting or deposition of a metallic substance is performed on the inner surface of the injection-molded material where the patterns are formed, to impart an elegant metallic gloss resulting in a stereoscopic visual effect that can be viewed or felt from the exterior of the formed injection-molded product
摘要翻译：本发明提供一种注塑成型品的制造方法，其特征在于，包括：通过在注射模具中注入材料形成具有形成在其表面上的图案的半透明或透明注塑成型品的成型工序;第一基底涂布工序在形成有图案的注塑产品的内表面上形成基底涂层;以及透明涂布步骤，用于在注射成型产品的外表面上形成透明涂层，其中基底涂层为由其中具有颜色的底涂层形成。此外，在形成图案的注射成型材料的内表面上进行金属物质的涂敷或沉积，赋予优雅的金属光泽，从而从外部观察或感觉到立体视觉效果形成的注射成型产品

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