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1. 发明授权

US07474386B2 Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device manufacturing method using the evaluation method and semiconductor device manufacturing method using a wafer evaluated by the evaluation method 有权
标题翻译：晶片平坦度评估方法，执行评估方法的晶片平整度评估装置，使用评估方法的晶片制造方法，使用评估方法的晶片质量保证方法，使用评估方法的半导体器件制造方法和使用由评估方法
公开(公告)号：US07474386B2
公开(公告)日：2009-01-06
申请号：US11710552
申请日：2007-02-26
申请人： Tadahito Fujisawa , Soichi Inoue , Makoto Kobayashi , Masashi Ichikawa , Tsuneyuki Hagiwara , Kenichi Kodama
发明人： Tadahito Fujisawa , Soichi Inoue , Makoto Kobayashi , Masashi Ichikawa , Tsuneyuki Hagiwara , Kenichi Kodama
IPC分类号： G03B27/58 , G03B27/32 , G03B27/52
CPC分类号： G01B21/30 , G01B11/306 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： There is disclosed a wafer flatness evaluation method includes measuring front and rear surface shapes of a wafer. The wafer front surface measured is divided into sites. Then, a flatness calculating method is selected according to a position of the site to be evaluated and flatness in the wafer surface is acquired.
摘要翻译：公开了一种晶片平坦度评估方法，其包括测量晶片的前后表面形状。测量的晶圆正面分为几个部位。然后，根据要评估的位置的位置选择平坦度计算方法，并获得晶片表面的平坦度。

2. 发明授权

US07365830B2 Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device manufacturing method using the evaluation method and semiconductor device manufacturing method using a wafer evaluated by the evaluation method 有权
标题翻译：晶片平坦度评估方法，执行评估方法的晶片平整度评估装置，使用评估方法的晶片制造方法，使用评估方法的晶片质量保证方法，使用评估方法的半导体器件制造方法和使用由评估方法
公开(公告)号：US07365830B2
公开(公告)日：2008-04-29
申请号：US11710410
申请日：2007-02-26
申请人： Tadahito Fujisawa , Soichi Inoue , Makoto Kobayashi , Masashi Ichikawa , Tsuneyuki Hagiwara , Kenichi Kodama
发明人： Tadahito Fujisawa , Soichi Inoue , Makoto Kobayashi , Masashi Ichikawa , Tsuneyuki Hagiwara , Kenichi Kodama
IPC分类号： G03B27/58 , G03B27/32 , G03B27/52
CPC分类号： G01B21/30 , G01B11/306 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： There is disclosed a wafer flatness evaluation method includes measuring front and rear surface shapes of a wafer. The wafer front surface measured is divided into sites. Then, a flatness calculating method is selected according to a position of the site to be evaluated and flatness in the wafer surface is acquired.
摘要翻译：公开了一种晶片平坦度评估方法，其包括测量晶片的前后表面形状。测量的晶圆正面分为几个部位。然后，根据要评估的位置的位置选择平坦度计算方法，并获得晶片表面的平坦度。

3. 发明申请

US20070177127A1 Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device manufacturing method using the evaluation method and semiconductor device manufacturing method using a wafer evaluated by the evaluation method 有权
标题翻译：晶片平坦度评估方法，执行评估方法的晶片平整度评估装置，使用评估方法的晶片制造方法，使用评估方法的晶片质量保证方法，使用评估方法的半导体器件制造方法和使用由评估方法
公开(公告)号：US20070177127A1
公开(公告)日：2007-08-02
申请号：US11710552
申请日：2007-02-26
申请人： Tadahito Fujisawa , Soichi Inoue , Makoto Kobayashi , Masashi Ichikawa , Tsuneyuki Hagiwara , Kenichi Kodama
发明人： Tadahito Fujisawa , Soichi Inoue , Makoto Kobayashi , Masashi Ichikawa , Tsuneyuki Hagiwara , Kenichi Kodama
IPC分类号： G03B27/58
CPC分类号： G01B21/30 , G01B11/306 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： There is disclosed a wafer flatness evaluation method includes measuring front and rear surface shapes of a wafer. The wafer front surface measured is divided into sites. Then, a flatness calculating method is selected according to a position of the site to be evaluated and flatness in the wafer surface is acquired.
摘要翻译：公开了一种晶片平坦度评估方法，其包括测量晶片的前后表面形状。测量的晶圆正面分为几个部位。然后，根据要评估的位置的位置选择平坦度计算方法，并获得晶片表面的平坦度。

4. 发明授权

US07230680B2 Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device manufacturing method using the evaluation method and semiconductor device manufacturing method using a wafer evaluated by the evaluation method 有权
公开(公告)号：US07230680B2
公开(公告)日：2007-06-12
申请号：US10739275
申请日：2003-12-19
申请人： Tadahito Fujisawa , Soichi Inoue , Makoto Kobayashi , Masashi Ichikawa , Tsuneyuki Hagiwara , Kenichi Kodama
发明人： Tadahito Fujisawa , Soichi Inoue , Makoto Kobayashi , Masashi Ichikawa , Tsuneyuki Hagiwara , Kenichi Kodama
IPC分类号： G03B27/58 , G03B27/42
CPC分类号： G01B21/30 , G01B11/306 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： There is disclosed a wafer flatness evaluation method includes measuring front and rear surface shapes of a wafer. The wafer front surface measured is divided into sites. Then, a flatness calculating method is selected according to a position of the site to be evaluated and flatness in the wafer surface is acquired.

5. 发明申请

US20070177126A1 Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device manufacturing method using the evaluation method and semiconductor device manufacturing method using a wafer evaluated by the evaluation method 有权
公开(公告)号：US20070177126A1
公开(公告)日：2007-08-02
申请号：US11710410
申请日：2007-02-26
申请人： Tadahito Fujisawa , Soichi Inoue , Makoto Kobayashi , Masashi Ichikawa , Tsuneyuki Hagiwara , Kenichi Kodama
发明人： Tadahito Fujisawa , Soichi Inoue , Makoto Kobayashi , Masashi Ichikawa , Tsuneyuki Hagiwara , Kenichi Kodama
IPC分类号： G03B27/58
CPC分类号： G01B21/30 , G01B11/306 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： There is disclosed a wafer flatness evaluation method includes measuring front and rear surface shapes of a wafer. The wafer front surface measured is divided into sites. Then, a flatness calculating method is selected according to a position of the site to be evaluated and flatness in the wafer surface is acquired.

6. 发明授权

US06440616B1 Mask and method for focus monitoring 失效
标题翻译：面罩和方法进行焦点监控
公开(公告)号：US06440616B1
公开(公告)日：2002-08-27
申请号：US09671501
申请日：2000-09-27
申请人： Kyoko Izuha , Tadahito Fujisawa , Soichi Inoue
发明人： Kyoko Izuha , Tadahito Fujisawa , Soichi Inoue
IPC分类号： G03F900
CPC分类号： G03F7/70641 , G03F1/26 , G03F1/44
摘要： There is disclosed a focus-monitoring mask which is adapted to be employed on an occasion of transferring a pattern on a wafer by way of photolithography, the mask comprising a first pattern region having at least one first monitor pattern which is constituted by a first opening surrounded by a first film or constituted by the first film surrounded by the first opening, and a second pattern region having at least one second monitor pattern which is constituted by a second opening surrounded by a second film or constituted by the second film surrounded by the second opening, and is capable of giving a predetermined phase difference to an exposure light passing through the second film relative to an exposure light passing through the second opening, wherein the first and second monitor patterns have a configuration in which both ends thereof are tapered from a central portion thereof.
摘要翻译：公开了一种适于在通过光刻法在晶片上转印图案的情况下采用的聚焦监视掩模，该掩模包括具有至少一个第一监视器图案的第一图案区域，该第一图案区域由第一开口由第一膜包围或由第一膜包围的第一膜构成的第二图案区域和具有至少一个第二监测图案的第二图案区域，该第二图案区域由第二开口构成，第二开口由第二膜包围或由第二膜包围，并且能够相对于通过第二开口的曝光光对通过第二膜的曝光光赋予预定的相位差，其中第一和第二监视器图案具有其两端从其中心部分。

7. 发明授权

US06317198B1 Method of examining an exposure tool 失效
标题翻译：检查曝光工具的方法
公开(公告)号：US06317198B1
公开(公告)日：2001-11-13
申请号：US09345758
申请日：1999-07-01
申请人： Kazuya Sato , Satoshi Tanaka , Tadahito Fujisawa , Soichi Inoue
发明人： Kazuya Sato , Satoshi Tanaka , Tadahito Fujisawa , Soichi Inoue
IPC分类号： G03B2732
CPC分类号： G03F7/706
摘要： In a method of examining the shape of the light source of an exposure tool, the shape of the pupil of its projection optical system, and the alignment of the shape of the light source with the shape of the pupil, the exposure tool comprising a light source, an illumination optical system for directing the light emitted from the light source to a reticle, and a projection optical system for transferring the reduced image on the reticle onto a wafer, the light emitted from the light source is projected on a reticle including a grating pattern where a transmitting area and a shading area are repeated in a finite number, the diffracted light of the first order or higher passed through the reticle is caused to illuminate the outer edge of the pupil of the projection optical system, and the pattern image on the reticle is projected on the wafer in the defocus state.
摘要翻译：在检查曝光工具的光源的形状，其投影光学系统的光瞳的形状以及光源的形状与瞳孔的形状的对准的方法中，曝光工具包括光光源，用于将从光源发射的光引导到掩模版的照明光学系统，以及用于将掩模版上的还原图像转印到晶片上的投影光学系统，从光源发射的光被投射在包括以有限数量重复发送区域和阴影区域的光栅图案，使通过标线的一级以上的衍射光照射投影光学系统的光瞳的外缘，并且图案图像在散焦状态下，在掩模版上投影在晶片上。

8. 发明授权

US07108945B2 Photomask having a focus monitor pattern 失效
公开(公告)号：US07108945B2
公开(公告)日：2006-09-19
申请号：US10396309
申请日：2003-03-26
申请人： Takumichi Sutani , Kyoko Izuha , Tadahito Fujisawa , Soichi Inoue
发明人： Takumichi Sutani , Kyoko Izuha , Tadahito Fujisawa , Soichi Inoue
IPC分类号： G01F9/00
CPC分类号： G03F7/70641 , G03F1/44
摘要： A photomask has a device pattern, which has an opening portion and a mask portion, and either a focus monitor pattern or an exposure dose monitor pattern, which has an opening portion and a mask portion and which has the same plane pattern shape as at least a partial region of a device pattern. The phase difference in transmitted exposure light between the opening portion and the mask portion of the focus monitor pattern is different from that between the opening portion and the mask portion of the device pattern. The opening portion of the exposure dose monitor pattern has a different exposure dose transmittance from that of the opening portion of the device pattern.

9. 发明授权

US5673103A Exposure apparatus and method 失效
标题翻译：曝光装置和方法
公开(公告)号：US5673103A
公开(公告)日：1997-09-30
申请号：US703530
申请日：1996-08-23
申请人： Soichi Inoue , Satoshi Tanaka , Tadahito Fujisawa
发明人： Soichi Inoue , Satoshi Tanaka , Tadahito Fujisawa
IPC分类号： G03F7/20 , G02B21/14
CPC分类号： G03F7/70058 , G03F7/70075 , G03F7/70125 , G03F7/70241 , G03F7/7025 , G03F7/70425 , G03F7/70566
摘要： An exposure apparatus for reducing/projecting a plurality of patterns of a photomask, which are elongated in at least two different directions, onto a substrate through the photomask includes a polarized light source for illuminating the photomask, a polarization control unit for changing the direction of polarization of polarized light from the polarized light source, a slit filter arranged at a position where the polarized light is focused and having a slit-like opening portion elongated in a direction perpendicular to the direction of polarization of the polarized light, the slit filter transmitting polarized light, of the polarized light passing through the photomask, which has the direction of polarization, a unit for changing the direction of the opening portion of the slit filter in synchronism with a change in direction of polarization of polarized light which is made by the polarization control unit, and a unit for illuminating the photomask with the polarized light at each position where the direction of the pattern becomes parallel to the direction of polarization of the polarized light, thereby exposing a pattern, formed on the photomask, onto the substrate at the angle of a direction of polarization perpendicular to an incident plane of light incident on the substrate.
摘要翻译：用于将通过光掩模在至少两个不同方向上延伸的光掩模的多个图案减少/投影到基板上的曝光装置包括用于照射光掩模的偏振光源，用于改变光掩模的方向的偏振控制单元偏振光从偏振光源的偏振光;狭缝滤光器，其设置在偏振光聚焦的位置处，并且具有在与偏振光的偏振方向垂直的方向上延伸的狭缝状开口部，狭缝滤光器透射通过具有偏振方向的光掩模的偏振光的偏振光与由偏振光的偏振光的偏振方向的变化同步地改变狭缝滤光片的开口部的方向的单元偏光控制单元，以及用于在每个po处以偏振光照射光掩模的单元其中图案的方向变得与偏振光的偏振方向平行，从而将形成在光掩模上的图案以垂直于入射到该光源的光的入射平面的偏振方向的角度暴露在基板上基质。

10. 发明申请

US20070259280A1 Photomask, exposure control method and method of manufacturing a semiconductor device 失效
标题翻译：光掩模，曝光控制方法和制造半导体器件的方法
公开(公告)号：US20070259280A1
公开(公告)日：2007-11-08
申请号：US11819375
申请日：2007-06-27
申请人： Tadahito Fujisawa , Soichi Inoue , Satoshi Tanaka , Masafumi Asano
发明人： Tadahito Fujisawa , Soichi Inoue , Satoshi Tanaka , Masafumi Asano
IPC分类号： G03F7/20 , G03F1/00 , G03C5/00 , G03F7/40 , G03F7/38
CPC分类号： G03F1/44
摘要： A photomask transferring a light shield film pattern formed on a transparent substrate by a projection exposure apparatus, comprising a circuit pattern for transferring a predetermined pattern to a resist film, and an exposure monitor mark, the exposure monitor mark being formed in a manner that blocks having a predetermined width p, which are not resolved by the projection exposure apparatus, are intermittently or continuously arrayed along one direction, light shield and transmission portions are arrayed along one direction in each of the blocks, the blocks are arrayed so that a dimension ratio of the light shield and transmission portions of the blocks simply changes and the phase difference of exposure light passing through adjacent light transmission portions is approximately 180°.
摘要翻译：一种光掩模，其通过投影曝光装置将形成在透明基板上的遮光膜图案转印，所述投影曝光装置包括用于将预定图案转印到抗蚀剂膜的电路图案，以及曝光监视标记，所述曝光监视标记以块具有未被投影曝光装置解析的预定宽度p沿着一个方向间歇地或连续地排列，在每个块中沿着一个方向排列有光屏蔽和透射部分，块被排列成使得尺寸比的光屏蔽和透射部分简单地改变，并且穿过相邻光传输部分的曝光光的相位差大约为180°。

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