会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明授权
    • Low power output driver
    • 低功率输出驱动器
    • US07821297B2
    • 2010-10-26
    • US11931191
    • 2007-10-31
    • Tacettin IsikLouis F. PoitrasDaniel M. Clementi
    • Tacettin IsikLouis F. PoitrasDaniel M. Clementi
    • H03K19/094
    • H04L25/0278H03K19/018521
    • A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground.
    • 低功率输出驱动器包括受压的电压源中的一个,其接收电源电压并输出比电源电压低的调节的降低的电压。 驱动器还包括接收第一逻辑信号的第一驱动器输入端,接收第二逻辑信号的第二驱动器输入,输出第一输出信号的第一驱动器输出和输出第二输出信号的第二驱动器输出。 驱动器包括在降压和第一和第二驱动器输出之间交叉连接的第一,第二,第三和第四n型金属氧化物半导体(NMOS)或恒压内部接地。 当第二输入为高电平时,第二NMOS和第三NMOS选通,第二驱动器输出升高到降低的电压,第一驱动器输出被下拉到恒定电压地。
    • 4. 发明授权
    • Low power output driver
    • 低功率输出驱动器
    • US07342420B2
    • 2008-03-11
    • US11234911
    • 2005-09-26
    • Tacettin IsikLouis F. PoitrasDaniel M. Clementi
    • Tacettin IsikLouis F. PoitrasDaniel M. Clementi
    • H03K19/094H03K19/0175
    • H04L25/0278H03K19/018521
    • A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the internal ground.
    • 低功率输出驱动器包括受压的电压源中的一个,其接收电源电压并输出比电源电压低的调节的降低的电压。 驱动器还包括接收第一逻辑信号的第一驱动器输入端,接收第二逻辑信号的第二驱动器输入,输出第一输出信号的第一驱动器输出和输出第二输出信号的第二驱动器输出。 驱动器包括在降压和第一和第二驱动器输出或地之间交叉连接的第一,第二,第三和第四n型金属氧化物半导体(NMOS)。 当第二输入为高电平时,第二NMOS和第三NMOS选通,第二驱动器输出升高到降低的电压,第一驱动器输出被下拉到内部地。
    • 6. 发明授权
    • High voltage switch utilizing low voltage MOS transistors with high voltage breakdown isolation junctions
    • 高压开关利用具有高压击穿隔离结的低压MOS晶体管
    • US08008951B2
    • 2011-08-30
    • US12555259
    • 2009-09-08
    • Tacettin Isik
    • Tacettin Isik
    • H03K3/00
    • H03K17/102
    • A high voltage switch having first and second states includes an input receiving an input voltage that is greater than a supply voltage. Each of first, second, and third MOS structures of a first conductivity type has a gate, a source, and a drain. The sources and drains of each of the MOS structures are electrically coupled in series between the input and ground. An output is electrically coupled to the input. When the switch is in the first state, the gate of the first MOS structure is pulled to ground, the gate of the second MOS structure is pulled to the supply voltage, and the gate of the third MOS structure is pulled to a voltage greater than the supply voltage and less than the input voltage. When the switch is in the second state, the gates of all of the MOS structures are pulled to the supply voltage.
    • 具有第一和第二状态的高电压开关包括接收大于电源电压的输入电压的输入端。 第一导电类型的第一,第二和第三MOS结构中的每一个具有栅极,源极和漏极。 每个MOS结构的源极和漏极在输入和地之间串联电耦合。 输出电耦合到输入。 当开关处于第一状态时,第一MOS结构的栅极被拉到地,第二MOS结构的栅极被拉到电源电压,第三MOS结构的栅极被拉到大于 电源电压小于输入电压。 当开关处于第二状态时,所有MOS结构的栅极被拉到电源电压。
    • 7. 发明申请
    • Low Power Output Driver
    • 低功率输出驱动器
    • US20090102513A1
    • 2009-04-23
    • US12342160
    • 2008-12-23
    • Tacettin IsikLouis F. PoitrasDaniel M. Clementi
    • Tacettin IsikLouis F. PoitrasDaniel M. Clementi
    • H03K19/0175
    • H04L25/0278H03K19/018521
    • A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground.
    • 低功率输出驱动器包括受压的电压源中的一个,其接收电源电压并输出比电源电压低的调节的降低的电压。 驱动器还包括接收第一逻辑信号的第一驱动器输入端,接收第二逻辑信号的第二驱动器输入,输出第一输出信号的第一驱动器输出和输出第二输出信号的第二驱动器输出。 驱动器包括在降压和第一和第二驱动器输出之间交叉连接的第一,第二,第三和第四n型金属氧化物半导体(NMOS)或恒压内部接地。 当第二输入为高电平时,第二NMOS和第三NMOS选通,第二驱动器输出升高到降低的电压,第一驱动器输出被下拉到恒定电压地。
    • 8. 发明申请
    • LOW POWER OUTPUT DRIVER
    • 低功率输出驱动器
    • US20080048724A1
    • 2008-02-28
    • US11931191
    • 2007-10-31
    • Tacettin IsikLouis PoitrasDaniel Clementi
    • Tacettin IsikLouis PoitrasDaniel Clementi
    • H03K19/094
    • H04L25/0278H03K19/018521
    • A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground.
    • 低功率输出驱动器包括受压的电压源中的一个,其接收电源电压并输出比电源电压低的调节的降低的电压。 驱动器还包括接收第一逻辑信号的第一驱动器输入端,接收第二逻辑信号的第二驱动器输入,输出第一输出信号的第一驱动器输出和输出第二输出信号的第二驱动器输出。 驱动器包括在降压和第一和第二驱动器输出之间交叉连接的第一,第二,第三和第四n型金属氧化物半导体(NMOS)或恒压内部接地。 当第二输入为高电平时,第二NMOS和第三NMOS选通,第二驱动器输出升高到降低的电压,第一驱动器输出被下拉到恒定电压地。
    • 10. 发明申请
    • High Voltage Switch Utilizing Low Voltage MOS Transistors with High Voltage Breakdown Isolation Junctions
    • 高压开关利用具有高电压故障隔离接头的低压MOS晶体管
    • US20110057714A1
    • 2011-03-10
    • US12555259
    • 2009-09-08
    • Tacettin Isik
    • Tacettin Isik
    • H03K17/687
    • H03K17/102
    • A high voltage switch having first and second states includes an input receiving an input voltage that is greater than a supply voltage. Each of first, second, and third MOS structures of a first conductivity type has a gate, a source, and a drain. The sources and drains of each of the MOS structures are electrically coupled in series between the input and ground. An output is electrically coupled to the input. When the switch is in the first state, the gate of the first MOS structure is pulled to ground, the gate of the second MOS structure is pulled to the supply voltage, and the gate of the third MOS structure is pulled to a voltage greater than the supply voltage and less than the input voltage. When the switch is in the second state, the gates of all of the MOS structures are pulled to the supply voltage.
    • 具有第一和第二状态的高电压开关包括接收大于电源电压的输入电压的输入端。 第一导电类型的第一,第二和第三MOS结构中的每一个具有栅极,源极和漏极。 每个MOS结构的源极和漏极在输入和地之间串联电耦合。 输出电耦合到输入。 当开关处于第一状态时,第一MOS结构的栅极被拉到地,第二MOS结构的栅极被拉到电源电压,第三MOS结构的栅极被拉到大于 电源电压小于输入电压。 当开关处于第二状态时,所有MOS结构的栅极被拉到电源电压。