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1. 发明授权

US5036216A Video dot clock generator 失效
标题翻译：视频点时钟发生器
公开(公告)号：US5036216A
公开(公告)日：1991-07-30
申请号：US490784
申请日：1990-03-08
申请人： Jere W. Hohmann , Bruce J. Rogers , Stephen A. Ransom , Daniel M. Clementi
发明人： Jere W. Hohmann , Bruce J. Rogers , Stephen A. Ransom , Daniel M. Clementi
IPC分类号： H03K3/354 , H03K5/00 , H03L7/089 , H03L7/099 , H03L7/187 , H03L7/193 , H03L7/199
CPC分类号： H03L7/0891 , H03K3/354 , H03L7/0995 , H03L7/187 , H03L7/193 , H03L7/199 , H03K2005/00071 , H03L2207/06
摘要： A video dot clock generator includes a phase-locked loop (PLL) which includes a voltage controlled oscillator, a frequency divider, a phase comparator and a loop filter. The voltage controlled oscillator (VCO) is programmable to provide multiple frequency ranges for a given range of control voltages applied to the oscillator. The programming affects both the frequency range and the gain of the VCO. The phase comparator includes circuitry which simulates a predetermined minimum phase error which, when compensated for, substantially eliminates jitter in the dot clock signal. The frequency divider used in the PLL and a similar frequency divided used to generate the reference signals for the phase comparator are programmable via an internal memory which also holds programmable control signals for the VCO. The memory, in turn, may be programmed by the user to achieve desired frequency and loop again characteristics for a given application.
摘要翻译：视频点时钟发生器包括锁相环（PLL），其包括压控振荡器，分频器，相位比较器和环路滤波器。压控振荡器（VCO）是可编程的，可以为施加到振荡器的给定范围的控制电压提供多个频率范围。该编程影响VCO的频率范围和增益。相位比较器包括模拟预定最小相位误差的电路，当被补偿时，基本上消除了点时钟信号中的抖动。在PLL中使用的分频器和用于产生相位比较器的参考信号的相似频率分频器可通过内部存储器进行编程，内部存储器也保存VCO的可编程控制信号。存储器又可以由用户编程以实现针对给定应用的期望的频率和循环特性。

2. 发明申请

US20090102513A1 Low Power Output Driver 有权
标题翻译：低功率输出驱动器
公开(公告)号：US20090102513A1
公开(公告)日：2009-04-23
申请号：US12342160
申请日：2008-12-23
申请人： Tacettin Isik , Louis F. Poitras , Daniel M. Clementi
发明人： Tacettin Isik , Louis F. Poitras , Daniel M. Clementi
IPC分类号： H03K19/0175
CPC分类号： H04L25/0278 , H03K19/018521
摘要： A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground.
摘要翻译：低功率输出驱动器包括受压的电压源中的一个，其接收电源电压并输出比电源电压低的调节的降低的电压。驱动器还包括接收第一逻辑信号的第一驱动器输入端，接收第二逻辑信号的第二驱动器输入，输出第一输出信号的第一驱动器输出和输出第二输出信号的第二驱动器输出。驱动器包括在降压和第一和第二驱动器输出之间交叉连接的第一，第二，第三和第四n型金属氧化物半导体（NMOS）或恒压内部接地。当第二输入为高电平时，第二NMOS和第三NMOS选通，第二驱动器输出升高到降低的电压，第一驱动器输出被下拉到恒定电压地。

3. 发明授权

US07821297B2 Low power output driver 有权
标题翻译：低功率输出驱动器
公开(公告)号：US07821297B2
公开(公告)日：2010-10-26
申请号：US11931191
申请日：2007-10-31
申请人： Tacettin Isik , Louis F. Poitras , Daniel M. Clementi
发明人： Tacettin Isik , Louis F. Poitras , Daniel M. Clementi
IPC分类号： H03K19/094
CPC分类号： H04L25/0278 , H03K19/018521
摘要： A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground.
摘要翻译：低功率输出驱动器包括受压的电压源中的一个，其接收电源电压并输出比电源电压低的调节的降低的电压。驱动器还包括接收第一逻辑信号的第一驱动器输入端，接收第二逻辑信号的第二驱动器输入，输出第一输出信号的第一驱动器输出和输出第二输出信号的第二驱动器输出。驱动器包括在降压和第一和第二驱动器输出之间交叉连接的第一，第二，第三和第四n型金属氧化物半导体（NMOS）或恒压内部接地。当第二输入为高电平时，第二NMOS和第三NMOS选通，第二驱动器输出升高到降低的电压，第一驱动器输出被下拉到恒定电压地。

4. 发明授权

US07782143B2 Phase locked loop and delay locked loop with chopper stabilized phase offset 有权
标题翻译：锁相环和具有斩波稳定相位偏移的延迟锁定环
公开(公告)号：US07782143B2
公开(公告)日：2010-08-24
申请号：US11683800
申请日：2007-03-08
申请人： Daniel M. Clementi
发明人： Daniel M. Clementi
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03L7/0812 , H03L7/0893 , H03L7/0895
摘要： A control circuit includes a phase frequency detector that receives a reference phase ΦREF (signal) as an input and a feedback phase ΦFBK (signal) as control feedback. A voltage controlled oscillator is in electrical communication with the phase frequency detector. The VCO provides an output and the feedback phase ΦFBK (signal). An auxiliary feedback loop receives error phase ΦE (signal) from each of the reference phase ΦREF (signal) and the feedback phase ΦFBK (signal). The auxiliary feedback loop provides an adjustment signal to the control circuit to correct for static phase offset.
摘要翻译：控制电路包括相位频率检测器，其接收作为输入的参考相位ΦREF（信号）和作为控制反馈的反馈相位ΦFBK（信号）。压控振荡器与相位频率检测器电连通。 VCO提供输出和反馈相ΦFBK（信号）。辅助反馈环路从参考相位ΦREF（信号）和反馈相位ΦFBK（信号）中的每一个接收误差相位ΦE（信号）。辅助反馈回路向控制电路提供调整信号，以校正静态相位偏移。

5. 发明授权

US07342420B2 Low power output driver 有权
标题翻译：低功率输出驱动器
公开(公告)号：US07342420B2
公开(公告)日：2008-03-11
申请号：US11234911
申请日：2005-09-26
申请人： Tacettin Isik , Louis F. Poitras , Daniel M. Clementi
发明人： Tacettin Isik , Louis F. Poitras , Daniel M. Clementi
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： H04L25/0278 , H03K19/018521
摘要： A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the internal ground.
摘要翻译：低功率输出驱动器包括受压的电压源中的一个，其接收电源电压并输出比电源电压低的调节的降低的电压。驱动器还包括接收第一逻辑信号的第一驱动器输入端，接收第二逻辑信号的第二驱动器输入，输出第一输出信号的第一驱动器输出和输出第二输出信号的第二驱动器输出。驱动器包括在降压和第一和第二驱动器输出或地之间交叉连接的第一，第二，第三和第四n型金属氧化物半导体（NMOS）。当第二输入为高电平时，第二NMOS和第三NMOS选通，第二驱动器输出升高到降低的电压，第一驱动器输出被下拉到内部地。

6. 发明授权

US07830177B2 Low power output driver 有权
公开(公告)号：US07830177B2
公开(公告)日：2010-11-09
申请号：US12342160
申请日：2008-12-23
申请人： Tacettin Isik , Louis F. Poitras , Daniel M. Clementi
发明人： Tacettin Isik , Louis F. Poitras , Daniel M. Clementi
IPC分类号： H03K19/094
CPC分类号： H04L25/0278 , H03K19/018521
摘要： A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground.

7. 发明申请

US20080218274A1 PHASE LOCKED LOOP AND DELAY LOCKED LOOP WITH CHOPPER STABILIZED PHASE OFFSET 有权
标题翻译：相位锁定环路和延迟锁定环路，具有切割器稳定相位偏移
公开(公告)号：US20080218274A1
公开(公告)日：2008-09-11
申请号：US11683800
申请日：2007-03-08
申请人： Daniel M. Clementi
发明人： Daniel M. Clementi
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03L7/0812 , H03L7/0893 , H03L7/0895
摘要： A control circuit includes a phase frequency detector that receives a reference phase ΦREF (signal) as an input and a feedback phase ΦFBK (signal) as control feedback. A voltage controlled oscillator is in electrical communication with the phase frequency detector. The VCO provides an output and the feedback phase ΦFBK (signal). An auxiliary feedback loop receives error phase ΦE (signal) from each of the reference phase ΦREF (signal) and the feedback phase ΦFBK (signal). The auxiliary feedback loop provides an adjustment signal to the control circuit to correct for static phase offset.
摘要翻译：控制电路包括相位频率检测器，其接收作为输入的参考相位Phi SUB REF（信号）和作为控制反馈的反馈相位Phi SUB FBK（信号）。压控振荡器与相位频率检测器电连通。 VCO提供输出和反馈相位Phi （信号）。辅助反馈回路从参考相位Phi SUB（信号）和反馈相位Phi SUB FBK（）中的每一个接收误差相位Phi （信号）。辅助反馈回路向控制电路提供调整信号，以校正静态相位偏移。

8. 发明授权

US06294936B1 Spread-spectrum modulation methods and circuit for clock generator phase-locked loop 失效
标题翻译：用于时钟发生器锁相环的扩频调制方法和电路
公开(公告)号：US06294936B1
公开(公告)日：2001-09-25
申请号：US09161969
申请日：1998-09-28
申请人： Daniel M. Clementi
发明人： Daniel M. Clementi
IPC分类号： H03D104
CPC分类号： H03C3/095 , H03K3/84 , H03K23/54 , H03L7/093 , H03L7/18
摘要： A spread-spectrum modulation method and circuit for a clock generator phase-locked loop (PLL). A dither signal is injected into a PLL in synchronization with and having the same period or fraction of the same period as the phase comparison performed within the PLL. Over such period, the phase error caused by the modulation will integrate to zero and hence avoid transmitting a disturbance to the loop. A particular embodiment utilizes an output of the reference divider and/or feedback divider within the PLL to generate the dither signal. Such a configuration avoids the need for additional hardware which otherwise would increase the chip area and/or cost of the device. The reference divider and/or feedback divider is made up preferably of a linear feedback shift register (LFSR). One or more stages of the LFSR provide an output which is used to generate the dither signal. In a preferred embodiment, the output from the LFSR exhibits a pseudo-random sequence.
摘要翻译：用于时钟发生器锁相环（PLL）的扩频调制方法和电路。抖动信号与PLL中执行的相位比较同步并且具有与相位周期相同的周期或分数的同时被注入到PLL中。在这样的时间周期内，由调制引起的相位误差将整合为零，因此避免了向环路传输干扰。特定实施例利用PLL内的参考分压器和/或反馈分压器的输出来产生抖动信号。这样的配置避免了额外的硬件的需要，否则会增加设备的芯片面积和/或成本。参考分频器和/或反馈分频器优选由线性反馈移位寄存器（LFSR）构成。 LFSR的一个或多个阶段提供用于产生抖动信号的输出。在优选实施例中，来自LFSR的输出呈现伪随机序列。

9. 发明授权

US5644270A Enchanced stability voltage controlled RC oscillator 失效
标题翻译：强化稳压电压RC振荡器
公开(公告)号：US5644270A
公开(公告)日：1997-07-01
申请号：US618413
申请日：1996-03-15
申请人： Todd K. Moyer , Daniel M. Clementi
发明人： Todd K. Moyer , Daniel M. Clementi
IPC分类号： H03K3/0231
CPC分类号： H03K3/0231
摘要： A voltage controlled oscillator having substantial frequency dependence on a parallel RC timing element including a voltage-variable resistance element, such as a MOSFET biased in the triode region. One terminal of the timing element can be connected to ground. The voltage used to tune the timing element, to lock the voltage controlled oscillator to a reference frequency can be used to control similar timing elements integrated upon the same circuit, for example a continuous-time filter in an ethernet transceiver. The oscillator frequency is substantially independent of variations in supply voltage.
摘要翻译：一种压控振荡器，其具有与并联RC定时元件相当的频率依赖性，其包括电压可变电阻元件，例如偏置在三极管区域中的MOSFET。定时元件的一个端子可以连接到地。用于调谐定时元件的电压，将压控振荡器锁定到参考频率可用于控制集成在同一电路上的类似定时元件，例如以太网收发器中的连续时间滤波器。振荡器频率基本上与电源电压的变化无关。

10. 发明授权

US08284816B1 Push-pull spread spectrum clock signal generator 有权
标题翻译：推挽扩频时钟信号发生器
公开(公告)号：US08284816B1
公开(公告)日：2012-10-09
申请号：US12476177
申请日：2009-06-01
申请人： Daniel M. Clementi
发明人： Daniel M. Clementi
IPC分类号： H04B1/00
CPC分类号： H04B15/02 , H04B2215/067
摘要： A spread spectrum clock signal generator modulates a reference clock signal based on a spread spectrum frequency profile and includes a phase-lock loop for generating a spread spectrum clock signal by aligning a phase of the modulated reference clock signal with a phase of the spread spectrum clock signal. The spread spectrum clock signal generator also includes a loop modulator for modulating the spread spectrum clock signal based on the spread spectrum frequency profile. Because the spread spectrum clock signal generator modulates both the reference clock signal and the spread spectrum clock signal based on the spread spectrum frequency profile, the spread spectrum clock signal has a non-distorted frequency profile and low phase jitter.
摘要翻译：扩展频谱时钟信号发生器基于扩频频谱分布来调制参考时钟信号，并且包括用于通过将调制参考时钟信号的相位与扩展频谱时钟的相位相对来产生扩频时钟信号的锁相环信号。扩频时钟信号发生器还包括一个环路调制器，用于根据扩展频谱分布调制扩频时钟信号。由于扩频时钟信号发生器基于扩频频谱分布调制参考时钟信号和扩频时钟信号，所以扩频时钟信号具有非失真的频率分布和低的相位抖动。

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