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    • 3. 发明申请
    • Digital Phase Lock Loop with Multi-Phase Master Clock
    • 具有多相主时钟的数字锁相环
    • US20100111241A1
    • 2010-05-06
    • US12266383
    • 2008-11-06
    • John W. KestersonCarrie SeimSelcuk SenXuecheng Jin
    • John W. KestersonCarrie SeimSelcuk SenXuecheng Jin
    • H03D3/24
    • H03L7/07H03L7/081H03L7/085H03L7/0994H03L2207/50
    • A digital phase lock loop circuit with reduced jitter at the output is disclosed. The digital phase lock loop circuit includes a phase frequency detector that determines a phase difference between a feedback signal and a reference frequency signal to generate an error signal indicative of the phase difference. A numerically controlled oscillator generates a first oscillator output signal with a frequency proportional to the error signal and a second oscillator output signal indicative of jitter of the first oscillator output signal in reference to the reference frequency signal. A phase accuracy extender determines a delay amount from the second oscillator output signal and delays the first oscillator output signal by the delay amount to generate a phase-enhanced output signal with edges aligned with one of a plurality of reference clock signals.
    • 公开了一种在输出端具有减小的抖动的数字锁相环电路。 数字锁相环电路包括相位频率检测器,其确定反馈信号和参考频率信号之间的相位差,以产生指示相位差的误差信号。 数控振荡器产生与误差信号成比例的频率的第一振荡器输出信号和指示参考频率信号的第一振荡器输出信号的抖动的第二振荡器输出信号。 相位精度延长器确定来自第二振荡器输出信号的延迟量,并将第一振荡器输出信号延迟延迟量,以产生具有与多个参考时钟信号之一对准的相位增强输出信号。
    • 4. 发明授权
    • Digital phase lock loop with multi-phase master clock
    • 具有多相主时钟的数字锁相环
    • US08184762B2
    • 2012-05-22
    • US12266383
    • 2008-11-06
    • John W. KestersonCarrie SeimSelcuk SenXuecheng Jin
    • John W. KestersonCarrie SeimSelcuk SenXuecheng Jin
    • H03D3/24H03L7/00H03L7/06
    • H03L7/07H03L7/081H03L7/085H03L7/0994H03L2207/50
    • A digital phase lock loop circuit provides an output with reduced jitter. The digital phase lock loop circuit includes a phase frequency detector that determines a phase difference between a feedback signal and a reference frequency signal to generate an error signal indicative of the phase difference. A numerically controlled oscillator generates a first oscillator output signal with a frequency proportional to the error signal and a second oscillator output signal indicative of jitter of the first oscillator output signal in reference to the reference frequency signal. A phase accuracy extender determines a delay amount from the second oscillator output signal and delays the first oscillator output signal by the delay amount to generate a phase-enhanced output signal with edges aligned with one of a plurality of reference clock signals.
    • 数字锁相环电路提供具有减少的抖动的输出。 数字锁相环电路包括相位频率检测器,其确定反馈信号和参考频率信号之间的相位差,以产生指示相位差的误差信号。 数控振荡器产生与误差信号成比例的频率的第一振荡器输出信号和指示参考频率信号的第一振荡器输出信号的抖动的第二振荡器输出信号。 相位精度延长器确定来自第二振荡器输出信号的延迟量,并将第一振荡器输出信号延迟延迟量,以产生具有与多个参考时钟信号之一对准的相位增强输出信号。
    • 5. 发明授权
    • Topology for a single ended input dual balanced mixer
    • 单端输入双平衡混频器拓扑
    • US07027792B1
    • 2006-04-11
    • US09721528
    • 2000-11-22
    • Gwilym Francis LuffSelcuk Sen
    • Gwilym Francis LuffSelcuk Sen
    • H04B1/26
    • H03D7/1425H03D7/1408H03D7/1433H03D7/1441H03D7/1458H03D7/165H03D2200/0043H03D2200/0047
    • The mixer circuit is a singled ended input to a double balanced high dynamic range mixer with only two base-emitter junctions across the supply. It provides for the use of bondwires to off chip ground as DC block and DC feed elements. The single ended input and differential output balanced mixer is well suited for the input stage of an integrated radio receiver—off chip circuitry is usually single ended, but on chip circuits are usually differential. No off chip differential RF circuits or baluns are required which reduces off chip component count and improves radio performance. The mixer circuit has lower LO drive requirements because of the DC coupled LO port. This results in better radio performance and a smaller die area because of the DC coupled IF port.
    • 混频器电路是单端输入到双平衡高动态范围混频器,在整个电源上只有两个基极 - 发射极结。 它提供使用键合线作为直流块和直流馈电元件的脱屑接地。 单端输入和差分输出平衡混频器非常适合于集成无线电接收器的输入级,芯片电路通常是单端,而片上电路通常是差分的。 不需要片外差分RF电路或平衡 - 不平衡变换器,可减少芯片组件数量并改善无线电性能。 由于直流耦合LO端口,混频器电路具有较低的LO驱动要求。 这导致更好的无线电性能和更小的管芯面积,因为直流耦合的IF端口。