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1. 发明授权

US06242356B1 Etchback method for forming microelectronic layer with enhanced surface smoothness 有权
标题翻译：用于形成具有增强的表面光滑度的微电子层的Etchback方法
公开(公告)号：US06242356B1
公开(公告)日：2001-06-05
申请号：US09465230
申请日：1999-12-17
申请人： Syun-Ming Jang , Chung-Long Chang , Shwangming Jeng , Chen-Hua Yu
发明人： Syun-Ming Jang , Chung-Long Chang , Shwangming Jeng , Chen-Hua Yu
IPC分类号： H01L21311
CPC分类号： H01L21/28123 , H01L21/28035 , H01L21/28525 , H01L21/32115
摘要： A method for forming a microelectronic layer within a microelectronic fabrication first employs a substrate. There is then formed over the substrate a target microelectronic layer. There is then formed upon the target microelectronic layer a sacrificial smoothing layer. Finally, there is then etched the sacrificial smoothing layer completely from the target microelectronic layer while partially etching the target microelectronic layer to form a partially etched target microelectronic layer with an enhanced surface smoothness in comparison with the target microelectronic layer.
摘要翻译：在微电子制造中形成微电子层的方法首先采用衬底。然后在衬底上形成目标微电子层。然后在目标微电子层上形成牺牲平滑层。最后，从目标微电子层完全蚀刻牺牲平滑层，同时与目标微电子层相比，部分蚀刻目标微电子层以形成具有增强的表面光滑度的部分蚀刻的目标微电子层。

2. 发明授权

US06207483B1 Method for smoothing polysilicon gate structures in CMOS devices 有权
标题翻译： CMOS器件中多晶硅栅极结构平滑化的方法
公开(公告)号：US06207483B1
公开(公告)日：2001-03-27
申请号：US09527183
申请日：2000-03-17
申请人： Chu-Yun Fu , Chung-Long Chang , Syun-Ming Jang , Shwangming Jeng
发明人： Chu-Yun Fu , Chung-Long Chang , Syun-Ming Jang , Shwangming Jeng
IPC分类号： H01L218238
CPC分类号： H01L21/823828 , H01L21/28035 , H01L21/32115
摘要： There is provided a method for smoothing the surface of undoped polysilicon regions of a CMOS structure, primarily gate regions. A direct HPD-CVD argon sputter is used improve the surface roughness by a factor of more than 50%. The argon plasma sputter may be used either alone or in conjunction with a thin capping layer of oxide, nitride or oxynitride. The devices manufactured using the process exhibit excellent electrical characteristics and improved reliability compared to devices made using conventional manufacturing processes.
摘要翻译：提供了一种用于平滑CMOS结构的未掺杂多晶硅区域的表面的方法，主要是栅极区域。使用直接HPD-CVD氩溅射将表面粗糙度提高了50％以上。氩等离子体溅射可以单独使用或与氧化物，氮化物或氮氧化物的薄覆盖层结合使用。与使用常规制造工艺制造的器件相比，使用该工艺制造的器件表现出优异的电气特性和改进的可靠性。

3. 发明授权

US06559040B1 Process for polishing the top surface of a polysilicon gate 有权
标题翻译：抛光多晶硅栅极顶表面的工艺
公开(公告)号：US06559040B1
公开(公告)日：2003-05-06
申请号：US09421517
申请日：1999-10-20
申请人： Chen-Hua Yu , Chung-Long Chang , Syun-Ming Jang
发明人： Chen-Hua Yu , Chung-Long Chang , Syun-Ming Jang
IPC分类号： H01L21302
CPC分类号： H01L21/3212 , H01L21/28035
摘要： The process of polishing the top surface of a polysilicon gate electrode often results in significant loss of material before adequate smoothness is achieved. This problem is overcome in the present invention by laying down a thin layer of a dielectric on the surface of the polysilicon prior to the application of CMP. This provides a sacrificial layer that facilitates the polishing operation and results in a polysilicon surface that is both very smooth and achievable with minimum loss of polysilicon.
摘要翻译：抛光多晶硅栅电极的顶表面的过程通常在达到足够的平滑度之前导致材料的显着损失。在本发明中通过在施加CMP之前在多晶硅的表面上放置介电层的薄层来克服该问题。这提供了促进抛光操作的牺牲层，并且导致多晶硅表面非常平滑并且可以以最小的多晶硅损失实现。

4. 发明授权

US06444371B1 Prevention of die loss to chemical mechanical polishing 有权
标题翻译：防止模具损失进行化学机械抛光
公开(公告)号：US06444371B1
公开(公告)日：2002-09-03
申请号：US09377541
申请日：1999-08-19
申请人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
发明人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
IPC分类号： G03F900
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2223/54466 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modern high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.
摘要翻译：描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。本发明适用于用于形成现代高密度，多级集成电路的所有方法，并且不受所形成的层数或使用的材料的影响。在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

5. 发明授权

US5972798A Prevention of die loss to chemical mechanical polishing 失效
标题翻译：防止模具损失进行化学机械抛光
公开(公告)号：US5972798A
公开(公告)日：1999-10-26
申请号：US86775
申请日：1998-05-29
申请人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
发明人： Syun-Ming Jang , Jui-Yu Chang , Chen-Hua Yu , Chung-Long Chang , Tsu Shih , Jeng-Horng Chen
IPC分类号： H01L23/544 , H01L21/00
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2223/54466 , H01L2924/0002 , Y10S438/942
摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modem high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.
摘要翻译：描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。本发明适用于用于形成调制解调器高密度多电平集成电路的所有方法，而不受所形成的层数或使用的材料的影响。在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

6. 发明授权

US06049137A Readable alignment mark structure formed using enhanced chemical mechanical polishing 失效
标题翻译：使用增强的化学机械抛光形成可读取的对准标记结构
公开(公告)号：US06049137A
公开(公告)日：2000-04-11
申请号：US106331
申请日：1998-06-29
申请人： Syun-Ming Jang , Ying-Ho Chen , Chung-Long Chang , Chen-Hua Yu
发明人： Syun-Ming Jang , Ying-Ho Chen , Chung-Long Chang , Chen-Hua Yu
IPC分类号： H01L23/544 , H01L21/302 , H01L21/461
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S148/102 , Y10S438/975
摘要： A structure of a readable alignment mark and method of manufacturing the readable alignment mark in an alignment mark area on a semiconductor substrate. A semiconductor substrate 10 comprising a product area 12 and an alignment mark area 30 is provided. The alignment mark area 30 has an outer area 40 and an inner area 50. The outer area surrounds 40 the inner area 50. A plurality of alignment mark trenches 24 is formed in the substrate 10 within the inner area 50. A pad oxide layer 20 and a silicon nitride layer 44 are formed sequentially in at least the alignment mark area 12. An isolation trench 43 is formed in the substrate 10 in at least the outer area 40. An insulating layer 46 is formed at least over the alignment mark area 30. The insulating layer 46 is chemical-mechanical polished thereby removing a first thickness of the insulating layer from the inner alignment mark area 50 and leaving a residual insulating layer 46A in the alignment mark trenches 48. Etches are used to remove the residual insulating layer 46A, silicon nitride layer 44, and pad oxide layer 42 in the alignment mark area 30 thereby exposing the alignment marks 48 and making the alignment marks readable.
摘要翻译：可读取的对准标记的结构和在半导体衬底上的对准标记区域中制造可读取的对准标记的方法。提供了包括产品区域12和对准标记区域30的半导体衬底10。对准标记区域30具有外部区域40和内部区域50.外部区域40围绕内部区域50.多个对准标记沟槽24形成在内部区域50内的衬底10中。衬垫氧化物层20 并且在至少对准标记区域12中顺序地形成氮化硅层44.隔离沟槽43至少在外部区域40中形成在基板10中。绝缘层46至少形成在对准标记区域30的上方绝缘层46进行化学机械抛光，从而从内部对准标记区域50除去绝缘层的第一厚度，并且在对准标记沟槽48中留下残留绝缘层46A。使用蚀刻来去除残留绝缘层46A ，氮化硅层44和衬垫氧化物层42，从而露出对准标记48并使对准标记可读。

7. 发明授权

US5786260A Method of fabricating a readable alignment mark structure using enhanced chemical mechanical polishing 失效
标题翻译：使用增强的化学机械抛光制造可读取的对准标记结构的方法
公开(公告)号：US5786260A
公开(公告)日：1998-07-28
申请号：US767015
申请日：1996-12-16
申请人： Syun-Ming Jang , Ying-Ho Chen , Chung-Long Chang , Chen-Hua Yu
发明人： Syun-Ming Jang , Ying-Ho Chen , Chung-Long Chang , Chen-Hua Yu
IPC分类号： H01L23/544 , H01L23/58
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S148/102 , Y10S438/975
摘要： A structure of a readable alignment mark and method of manufacturing the readable alignment mark in an alignment mark area on a semiconductor substrate. A semiconductor substrate 10 comprising a product area 12 and an alignment mark area 30 is provided. The alignment mark area 30 has an outer area 40 and an inner area 50. The outer area surrounds 40 the inner area 50. A plurality of alignment mark trenches 24 is formed in the substrate 10 within the inner area 50. A pad oxide layer 20 and a silicon nitride layer 44 are formed sequentially in at least the alignment mark area 12. An isolation trench 43 is formed in the substrate 10 in at least the outer area 40. An insulating layer 46 is formed at least over the alignment mark area 30. The insulating layer 46 is chemical-mechanical polished thereby removing a first thickness of the insulating layer from the inner alignment mark area 50 and leaving a residual insulating layer 46A in the alignment mark trenches 48. Etches are used to remove the residual insulating layer 46A, silicon nitride layer 44, and pad oxide layer 42 in the alignment mark area 30 thereby exposing the alignment marks 48 and making the alignment marks readable.
摘要翻译：可读取的对准标记的结构和在半导体衬底上的对准标记区域中制造可读取的对准标记的方法。提供了包括产品区域12和对准标记区域30的半导体衬底10。对准标记区域30具有外部区域40和内部区域50.外部区域40围绕内部区域50.多个对准标记沟槽24形成在内部区域50内的衬底10中。衬垫氧化物层20 并且在至少对准标记区域12中顺序地形成氮化硅层44.隔离沟槽43至少在外部区域40中形成在基板10中。绝缘层46至少形成在对准标记区域30的上方绝缘层46进行化学机械抛光，从而从内部对准标记区域50除去绝缘层的第一厚度，并且在对准标记沟槽48中留下残留绝缘层46A。使用蚀刻来去除残留绝缘层46A ，氮化硅层44和衬垫氧化物层42，从而露出对准标记48并使对准标记可读。

8. 发明授权

US5773360A Reduction of surface contamination in post-CMP cleaning 失效
标题翻译：减少后CMP清洁中的表面污染
公开(公告)号：US5773360A
公开(公告)日：1998-06-30
申请号：US734067
申请日：1996-10-18
申请人： Chung-Long Chang , Chen-Hua Yu , Syun-Ming Jang
发明人： Chung-Long Chang , Chen-Hua Yu , Syun-Ming Jang
IPC分类号： H01L21/3105 , H01L21/461
CPC分类号： H01L21/31053 , Y10S438/906 , Y10S438/959
摘要： Chemical-mechanical polishing is followed with a scrubbing procedure for the removal of any particulate contaminants. Scrubbing is succeeded by a plasma etching step, using a parallel electrode plasma etcher, a downstream plasma etcher, or similar apparatus. Plasma etching is performed for about 30 seconds using CF.sub.4 as the etching gas, so that about 300 Angstroms of the post CMP surface is removed. This results in the almost total elimination of residual mobile ions from the polished surface without the introduction of microgrooves and similar blemishes as is often the case when HF is used for this purpose.
摘要翻译：随后进行化学机械抛光，用于除去任何颗粒污染物的洗涤程序。通过等离子体蚀刻步骤，使用平行电极等离子体蚀刻器，下游等离子体蚀刻器或类似装置来完成擦洗。使用CF 4作为蚀刻气体进行等离子体蚀刻约30秒，从而去除后CMP表面的约300埃。这导致几乎完全消除了抛光表面的残余移动离子，而不会引入微槽和类似的瑕疵，如通常用于此目的的HF的情况。

9. 发明授权

US06391792B1 Multi-step chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layer 有权
标题翻译：用于形成图案化平面化孔径填充层的多步化学机械抛光（CMP）平面化方法
公开(公告)号：US06391792B1
公开(公告)日：2002-05-21
申请号：US09573981
申请日：2000-05-18
申请人： Syun-Ming Jang , Juing-Yi Cheng , Chung-Long Chang
发明人： Syun-Ming Jang , Juing-Yi Cheng , Chung-Long Chang
IPC分类号： H01L21302
CPC分类号： H01L21/31053 , H01L21/76229
摘要： Within a method for forming an aperture fill layer within a aperture, there is first provided a topographic substrate having an aperture formed therein. There is then formed over the topographic substrate and filling the aperture a blanket aperture fill layer. There is then planarized, while employing a first chemical mechanical polish (CMP) planarizing method, the blanket aperture fill layer to form a blanket planarized aperture fill layer while not reaching the topographic substrate. Finally, there is then planarized, while employing a second planarizing method, the blanket planarized aperture fill layer to form within the aperture a patterned planarized aperture fill layer. The two step planarizing method may be employed for forming with enhanced planarity and attenuated topographic substrate erosion a patterned planarized aperture fill layer, such as a patterned planarized trench isolation region, within a topographic substrate, such as a topographic semiconductor substrate.
摘要翻译：在用于在孔内形成孔填充层的方法中，首先提供其中形成有孔的形貌基底。然后形成在地形衬底上并且将孔填充到覆盖孔填充层。然后平面化，同时采用第一化学机械抛光（CMP）平面化方法，橡皮布孔填充层，以形成覆盖平面化的孔填充层，同时不能到达地形衬底。最后，在采用第二平面化方法的同时平面化平坦化的平面化孔径填充层，以在孔内形成图案化的平坦化孔填充层。可以采用两步平面化方法来形成具有增强的平面度和衰减的地形衬底侵蚀的图案化的平坦化孔填充层，例如图形化的平面化沟槽隔离区域，在地形衬底（例如地形半导体衬底）内。

10. 发明授权

US6153512A Process to improve adhesion of HSQ to underlying materials 有权
标题翻译：提高HSQ与下层材料粘附性的工艺
公开(公告)号：US6153512A
公开(公告)日：2000-11-28
申请号：US414922
申请日：1999-10-12
申请人： Chung-Long Chang , Syun-Ming Jang
发明人： Chung-Long Chang , Syun-Ming Jang
IPC分类号： H01L21/3105 , H01L21/312 , H01L21/316 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/02134 , H01L21/02131 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02282 , H01L21/02315 , H01L21/31058 , H01L21/3124 , H01L21/31629 , H01L21/76801 , H01L21/76826 , H01L21/76834
摘要： A process for forming an intermetal dielectric, (IMD), layer, comprised of an overlying silicon oxide layer, and an underlying low k dielectric layer, such as hydrogen silsesquioxane, (HSQ), has been developed. The process features the use of a series of plasma treatments, performed in a nitrogen containing ambient, used to improve the adhesion of the IMD layer, to underlying materials. A first plasma treatment is performed on a thin insulator layer, prior to application of the HSQ layer. The plasma treatment roughens the top surface of the thin insulator layer, resulting in improved adhesion of the HSQ layer to the thin insulator layer. A second plasma treatment is performed to the HSQ layer, prior to deposition of the overlying, thick silicon oxide layer, allowing improve adhesion of the thick silicon oxide layer, to the underlying HSQ layer, to be achieved.
摘要翻译：已经开发了用于形成由上覆硅氧化物层构成的金属间电介质（IMD）层，和诸如氢倍半硅氧烷（HSQ）等下面的低k电介质层的工艺。该方法的特征在于使用一系列等离子体处理，其在含氮环境中进行，用于改善IMD层的附着力到下面的材料。在施加HSQ层之前，在薄绝缘体层上进行第一等离子体处理。等离子体处理使薄绝缘体层的顶表面变粗糙，从而改善了HSQ层与薄绝缘体层的粘合性。在沉积上覆的厚的氧化硅层之前，对HSQ层进行第二等离子体处理，以使得能够实现厚的氧化硅层与底层的HSQ层的粘附。

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