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1. 发明申请

US20120068258A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120068258A1
公开(公告)日：2012-03-22
申请号：US13052908
申请日：2011-03-21
申请人： Syotaro ONO , Wataru Saito , Shunji Taniuchi , Miho Watanabe , Hiroaki Yamashita
发明人： Syotaro ONO , Wataru Saito , Shunji Taniuchi , Miho Watanabe , Hiroaki Yamashita
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/7811 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/84 , H01L29/0619 , H01L29/402 , H01L29/42372 , H01L29/66712 , H01L2224/37013 , H01L2224/40245 , H01L2224/40479 , H01L2224/40499 , H01L2224/4103 , H01L2224/84203 , H01L2924/00014 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00 , H01L2224/37099
摘要： According to one embodiment, a semiconductor device includes a first main electrode, a control electrode, an extraction electrode, a second insulating film, a plurality of contact electrodes, and a control terminal. The first main electrode is electrically connected to a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type selectively provided on a surface of the first semiconductor region. The control electrode is provided on the first semiconductor region via a first insulating film. The extraction electrode is electrically connected to the control electrode. The second insulating film is provided on the first main electrode and the extraction electrode. The plurality of contact electrodes are provided in an inside of a plurality of first contact holes formed in the second insulating film and are electrically connected to the extraction electrode. The control terminal covers portions of the first main electrode provided on the first semiconductor region, on the second semiconductor region, and on the control electrode, respectively, and the extraction electrode, is electrically connected to the plurality of contact electrodes, and is electrically insulated from the first main electrode by the second insulating film.
摘要翻译：根据一个实施例，半导体器件包括第一主电极，控制电极，引出电极，第二绝缘膜，多个接触电极和控制端子。第一主电极电连接到第一导电类型的第一半导体区域和选择性地设置在第一半导体区域的表面上的第二导电类型的第二半导体区域。控制电极经由第一绝缘膜设置在第一半导体区域上。引出电极与控制电极电连接。第二绝缘膜设置在第一主电极和引出电极上。多个接触电极设置在形成在第二绝缘膜中的多个第一接触孔的内部，并与引出电极电连接。控制端子分别覆盖设置在第一半导体区域上，第二半导体区域上和控制电极上的第一主电极的部分，并且引出电极电连接到多个接触电极，并且是电绝缘的从第一主电极通过第二绝缘膜。

2. 发明申请

US20120074461A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120074461A1
公开(公告)日：2012-03-29
申请号：US13235302
申请日：2011-09-16
申请人： Syotaro ONO , Wataru Saito , Shunji Taniuchi , Miho Watanabe , Hiroaki Yamashita
发明人： Syotaro ONO , Wataru Saito , Shunji Taniuchi , Miho Watanabe , Hiroaki Yamashita
IPC分类号： H01L29/78 , H01L21/336 , H01L21/331 , H01L29/739
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/42376 , H01L29/4238
摘要： According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.
摘要翻译：根据实施例，半导体器件包括设置在第一半导体层上并包括第一柱和第二柱的第二半导体层。第一控制电极设置在第二半导体层的沟槽中，第二控制电极设置在第二半导体层上并连接到第一控制电极。除了第二控制电极下方的部分之外，在第二半导体层的表面上设置第一半导体区域。第二半导体区域设置在第一半导体区域的表面上，第二半导体区域与第二控制电极下方的部分分开，第三半导体区域设置在第一半导体区域上。第一主电极与第一半导体层电连接，第二主电极与第二和第三半导体区域电连接。

3. 发明申请

US20110227154A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110227154A1
公开(公告)日：2011-09-22
申请号：US13052032
申请日：2011-03-18
申请人： Syotaro ONO , Wataru Saito , Munehisa Yabuzaki , Shunji Taniuchi , Miho Watanabe
发明人： Syotaro ONO , Wataru Saito , Munehisa Yabuzaki , Shunji Taniuchi , Miho Watanabe
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/66712
摘要： A semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type formed on the first semiconductor layer; a first buried layer of the first conductivity type selectively formed in the second semiconductor layer and having a first peak impurity concentration at a first depth; a second buried layer of a second conductivity type selectively formed in the second semiconductor layer and having a second peak impurity concentration at a second depth; a base layer of the second conductivity type selectively formed in the second semiconductor layer and overlapping with an upper portion of the second buried layer; a source layer of the first conductivity type selectively formed in the base layer; and a gate electrode formed on the base layer and on the second semiconductor layer above the first buried layer with a gate insulating film being interposed therebetween.
摘要翻译：一种半导体器件，包括：第一导电类型的第一半导体层; 形成在第一半导体层上的第一导电类型的第二半导体层; 第一导电类型的第一掩埋层选择性地形成在第二半导体层中，并且在第一深度处具有第一峰值杂质浓度; 第二导电类型的第二掩埋层选择性地形成在第二半导体层中，并且在第二深度具有第二峰值杂质浓度; 第二导电类型的基极层选择性地形成在第二半导体层中并与第二掩埋层的上部重叠; 选择性地形成在所述基底层中的所述第一导电类型的源极层; 以及形成在所述第一掩埋层上的所述基极层和所述第二半导体层上的栅电极，其间插入有栅极绝缘膜。

4. 发明申请

US20130082261A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20130082261A1
公开(公告)日：2013-04-04
申请号：US13612200
申请日：2012-09-12
申请人： Wataru SAITO , Syotaro ONO , Toshiyuki NAKA , Shunji TANIUCHI , Hiroaki YAMASHITA
发明人： Wataru SAITO , Syotaro ONO , Toshiyuki NAKA , Shunji TANIUCHI , Hiroaki YAMASHITA
IPC分类号： H01L27/088
CPC分类号： H01L27/0629 , H01L27/0727 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/42372 , H01L29/7803 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7808 , H01L29/7813 , H01L29/7827 , H01L29/868 , H01L29/872
摘要： A semiconductor device comprising: a Metal Oxide Semiconductor Field Effect Transistor including: a semiconductor substrate including a first semiconductor layer of a first conductivity type; second semiconductor layers of a second conductivity type extending in a depth direction from one surface of the semiconductor substrate, and having space each other; a first diode including a fifth semiconductor layer of the second conductivity type contacting the second semiconductor layer in one surface side of the semiconductor substrate, the first semiconductor layer and the second semiconductor layers; and an anode of the second diode connected to an anode of the first diode.
摘要翻译：一种半导体器件，包括：金属氧化物半导体场效应晶体管，包括：半导体衬底，包括第一导电类型的第一半导体层; 第二导电类型的第二半导体层，在深度方向上从半导体衬底的一个表面延伸并且彼此具有空间; 第一二极管，包括在半导体衬底的一个表面侧中与第二半导体层接触的第二导电类型的第五半导体层，第一半导体层和第二半导体层; 并且所述第二二极管的阳极连接到所述第一二极管的阳极。

5. 发明申请

US20130248988A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130248988A1
公开(公告)日：2013-09-26
申请号：US13607697
申请日：2012-09-08
申请人： Syotaro ONO , Wataru Saito , Toshiyuki Naka , Shunji Taniuchi , Hiroaki Yamashita
发明人： Syotaro ONO , Wataru Saito , Toshiyuki Naka , Shunji Taniuchi , Hiroaki Yamashita
IPC分类号： H01L29/78 , H01L21/02
CPC分类号： H01L29/7827 , H01L21/02697 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/42376 , H01L29/4238 , H01L29/7802 , H01L29/7813
摘要： A semiconductor device includes a semiconductor substrate and a plurality of gate electrodes including a part extended in a first direction in a plane parallel with the semiconductor substrate. The semiconductor substrate has a second semiconductor layer including a plurality of first conductive type pillars and second conductive type second pillars that are disposed on the first semiconductor layer, extending in the first direction in the plane parallel with the semiconductor substrate and in a third direction intersecting with a second direction orthogonal to the first direction, and arranged adjacent to each other in an alternate manner.
摘要翻译：半导体器件包括半导体衬底和多个栅电极，其包括在与半导体衬底平行的平面中沿第一方向延伸的部分。所述半导体衬底具有包括多个第一导电型柱和第二导电型第二柱的第二半导体层，所述第二导电型柱和第二导电型第二柱设置在所述第一半导体层上，在与所述半导体衬底平行的平面中沿所述第一方向延伸，并且在第三方向上相交具有与第一方向正交的第二方向，并且以交替的方式彼此相邻布置。

6. 发明申请

US20100308399A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20100308399A1
公开(公告)日：2010-12-09
申请号：US12728823
申请日：2010-03-22
申请人： Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
发明人： Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0619 , H01L29/0626 , H01L29/0634 , H01L29/0657 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/7808 , H01L29/7811 , H01L29/7828
摘要： A power semiconductor device includes: a first semiconductor layer of the first conduction type; second semiconductor layers of the first conduction type and third semiconductor layers of the second conduction type alternately provided transversely on the first semiconductor layer; fourth semiconductor layers of the second conduction type provided on the surfaces of the third semiconductor layers; fifth semiconductor layers of the first conduction type provided selectively on the surfaces of the fourth semiconductor layer; sixth semiconductor layers of the second conduction type and seventh semiconductor layers of the first conduction type alternately provided transversely on the second and the third semiconductor layers; a first main electrode electrically connected to the first semiconductor layer; an insulation film provided on the fourth semiconductor layers, the sixth semiconductor layers and the seventh semiconductor layers; a control electrode provided on the fourth semiconductor layers, the sixth semiconductor layers and the seventh semiconductor layers via the insulation film; and a second main electrode joined to the surfaces of the fourth semiconductor layers and the fifth semiconductor layers, the sixth semiconductor layers being connected to the fourth semiconductor layers and to at least one of the third semiconductor layers, which is provided between two of the fourth semiconductor layers, and an impurity concentration of the third semiconductor layers provided below the sixth semiconductor layers being higher than an impurity concentration of the third semiconductor layers provided under the fourth semiconductor layers.
摘要翻译：功率半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层和第二导电类型的第三半导体层交替地设置在第一半导体层上; 设置在第三半导体层的表面上的第二导电类型的第四半导体层; 选择性地在第四半导体层的表面上提供第一导电类型的第五半导体层; 第二导电类型的第六半导体层和第一导电类型的第七半导体层交替地设置在第二和第三半导体层上; 电连接到第一半导体层的第一主电极; 设置在第四半导体层，第六半导体层和第七半导体层上的绝缘膜; 设置在第四半导体层上的控制电极，第六半导体层和第七半导体层经由绝缘膜; 以及与所述第四半导体层和所述第五半导体层的表面接合的第二主电极，所述第六半导体层与所述第四半导体层连接，并且至少一个所述第三半导体层设置在所述第四半导体层并且设置在第六半导体层下方的第三半导体层的杂质浓度高于设置在第四半导体层下方的第三半导体层的杂质浓度。

7. 发明申请

US20100264489A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100264489A1
公开(公告)日：2010-10-21
申请号：US12719475
申请日：2010-03-08
申请人： Hiroshi OHTA , Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
发明人： Hiroshi OHTA , Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
IPC分类号： H01L27/06 , H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/7395 , H01L29/7813
摘要： A transistor contains a first semiconductor layer of a first conductivity type and a drift layer having a pillar structure in which a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type are alternately disposed in a direction parallel to a surface of the first semiconductor layer. The fourth semiconductor layer of the first conductivity type and the fifth semiconductor layer of the second conductivity type are alternately disposed and parallel to the drift layer. The fifth semiconductor layer has a larger amount of impurities than the fourth semiconductor layer. The sixth semiconductor layer of the first conductivity type and the seventh semiconductor layer of the second conductivity type are alternately disposed and parallel to the fourth and the fifth semiconductor layers. The seventh semiconductor layer has a smaller amount of impurities than the sixth semiconductor layer.
摘要翻译：晶体管包含第一导电类型的第一半导体层和具有柱结构的漂移层，其中第一导电类型的第二半导体层和第二导电类型的第三半导体层在平行于第一半导体层的表面。第一导电类型的第四半导体层和第二导电类型的第五半导体层交替地设置并平行于漂移层。第五半导体层的杂质量比第四半导体层大。第一导电类型的第六半导体层和第二导电类型的第七半导体层交替地设置并平行于第四和第五半导体层。第七半导体层的杂质量比第六半导体层少。

8. 发明申请

US20100038712A1 POWER SEMICONDUCTOR DEVICE 失效
标题翻译：功率半导体器件
公开(公告)号：US20100038712A1
公开(公告)日：2010-02-18
申请号：US12540192
申请日：2009-08-12
申请人： Miho WATANABE , Masaru IZUMISAWA , Yasuto SUMI , Hiroshi OHTA , Wataru SEKINE , Wataru SAITO , Syotaro ONO , Nana HATANO
发明人： Miho WATANABE , Masaru IZUMISAWA , Yasuto SUMI , Hiroshi OHTA , Wataru SEKINE , Wataru SAITO , Syotaro ONO , Nana HATANO
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/1095 , H01L29/7802
摘要： A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part. The device includes a first semiconductor layer, and second and third semiconductor layers formed on the first semiconductor layer, and alternately arranged along a direction parallel to a surface of the first semiconductor layer, wherein the device part is provided with a first region and a second region, each of which includes at least one of the second semiconductor layers and at least one of the third semiconductor layers, and with regard to a difference value ΔN (=NA−NB) obtained by subtracting an impurity amount NB per unit length of each of the third semiconductor layers from an impurity amount NA per unit length of each of the second semiconductor layers, a difference value ΔNC1 which is the difference value ΔN in the first region of the device part, a difference value ΔNC2 which is the difference value ΔN in the second region of the device part, and a difference value ΔNT which is the difference value ΔN in the terminal part satisfy a relationship of ΔNC1>ΔNT>ΔNC2.
摘要翻译：根据本发明实施例的半导体器件包括器件部分和端子部分。该器件包括第一半导体层，以及形成在第一半导体层上的第二和第三半导体层，并且沿着与第一半导体层的表面平行的方向交替布置，其中器件部分设置有第一区域和第二半导体层区域，其中每一个包括第二半导体层和至少一个第三半导体层中的至少一个，并且关于通过从每单位长度减去杂质量NB获得的差值Dgr; N（= NA-NB）从每个第二半导体层的每单位长度的杂质量NA中的每个第三半导体层的差分值＆Dgr; NC1，其是器件部分的第一区域中的差值＆Dgr; N，差值＆Dgr ;作为装置部分的第二区域中的差值Dgr; N的NC2，作为终端部分中的差值Dgr; N的差值＆Dgr; NT满足关系的＆Dgr; NC1>＆Dgr; NT>＆Dgr; NC2。

9. 发明申请

US20110018055A1 POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 失效
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US20110018055A1
公开(公告)日：2011-01-27
申请号：US12840201
申请日：2010-07-20
申请人： Hiroshi OHTA , Yasuto SUMI , Kiyoshi KIMURA , Wataru SEKINE , Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
发明人： Hiroshi OHTA , Yasuto SUMI , Kiyoshi KIMURA , Wataru SEKINE , Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66712 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/7811
摘要： According to one embodiment, a power semiconductor device includes a first semiconductor layer, and first, second and third semiconductor regions. The first semiconductor layer has a first conductivity type. The first semiconductor regions have a second conductivity type, and are formed with periodicity in a lateral direction in a second semiconductor layer of the first conductivity type. The second semiconductor layer is provided on a major surface of the first semiconductor layer in a device portion with a main current path formed in a vertical direction generally perpendicular to the major surface and in a terminal portion provided around the device portion. The second semiconductor region has the first conductivity type and is a portion of the second semiconductor layer sandwiched between adjacent ones of the first semiconductor regions. The third semiconductor regions have the second conductivity type and are provided below the first semiconductor regions in the terminal portion.
摘要翻译：根据一个实施例，功率半导体器件包括第一半导体层以及第一，第二和第三半导体区域。第一半导体层具有第一导电类型。第一半导体区域具有第二导电类型，并且在第一导电类型的第二半导体层中在横向方向上形成周期性。第二半导体层设置在器件部分的第一半导体层的主表面上，其主电流通道形成在大体上垂直于主表面的垂直方向上，以及设置在器件部分周围的端子部分中。第二半导体区域具有第一导电类型，并且是夹在相邻的第一半导体区域中的第二半导体层的一部分。第三半导体区域具有第二导电类型并且设置在端子部分中的第一半导体区域的下方。

10. 发明申请

US20100096692A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100096692A1
公开(公告)日：2010-04-22
申请号：US12537219
申请日：2009-08-06
申请人： Wataru SAITO , Syotaro ONO , Nana HATANO , Hiroshi OHTA , Miho WATANABE
发明人： Wataru SAITO , Syotaro ONO , Nana HATANO , Hiroshi OHTA , Miho WATANABE
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/7806
摘要： A semiconductor device of the invention includes: a super junction structure of an n-type pillar layer and a p-type pillar layer; a base layer provided on the p-type pillar layer; a source layer selectively provided on a surface of the base layer; a gate insulating film provided on a portion being in contact with the base layer, a portion being in contact with the source layer and a portion being in contact with the n-type pillar layer on a portion of a junction between the n-type pillar layer and the p-type pillar layer; a control electrode provided opposed to the base layer, the source layer and the n-type pillar layer through the gate insulating film; and a source electrode electrically connected to the base layer, the source layer and the n-type layer. The source electrode is contact with the surface of the n-type pillar layer located between the control electrodes to form a Schottky junction.
摘要翻译：本发明的半导体器件包括：n型柱层和p型柱层的超结结构; 设置在p型支柱层上的基底层; 源层选择性地设置在基层的表面上; 设置在与所述基底层接触的部分上的栅极绝缘膜，与所述源极层接触的部分和在所述n型支柱的接合部的一部分上与所述n型支柱层接触的部分层和p型支柱层; 控制电极，其通过所述栅极绝缘膜与所述基极层，所述源极层和所述n型支柱层相对设置; 以及与基极层，源极层和n型层电连接的源电极。源电极与位于控制电极之间的n型支柱层的表面接触以形成肖特基结。

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