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1. 发明授权

US06331446B1 Process for underfilling a controlled collapse chip connection (C4) integrated circuit package with an underfill material that is heated to a partial gel state 有权
标题翻译：用于将加热到部分凝胶状态的底部填充材料用于底部填充受控崩溃芯片连接（C4）集成电路封装的工艺
公开(公告)号：US06331446B1
公开(公告)日：2001-12-18
申请号：US09261648
申请日：1999-03-03
申请人： Duane Cook , Venkatesan Murali , Suresh Ramalingam , Nagesh Vodrahalli
发明人： Duane Cook , Venkatesan Murali , Suresh Ramalingam , Nagesh Vodrahalli
IPC分类号： H01L2144
CPC分类号： H01L24/31 , H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83951 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01082 , H01L2924/14 , H01L2924/00 , H01L2924/3512 , H01L2224/0401
摘要： A partial gel step in the underfilling of an integrated circuit that is mounted to a substrate. The process involves dispensing a first underfill material and then heating the underfill material to a partial gel state. The partial gel step may reduce void formation and improve adhesion performance during moisture loading.
摘要翻译：在安装到基板上的集成电路的底部填充中的部分凝胶步骤。该方法包括分配第一底部填充材料，然后将底部填充材料加热至部分凝胶状态。部分凝胶步骤可以减少空隙形成并改善湿气加载期间的粘附性能。

2. 发明授权

US07141448B2 Controlled collapse chip connection (C4) integrated circuit package which has two dissimilar underfill materials 有权
公开(公告)号：US07141448B2
公开(公告)日：2006-11-28
申请号：US09874666
申请日：2001-06-05
申请人： Suresh Ramalingam , Venkatesan Murali , Duane Cook
发明人： Suresh Ramalingam , Venkatesan Murali , Duane Cook
IPC分类号： H01L21/00 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L21/563 , H01L24/31 , H01L2224/16225 , H01L2224/73203 , H01L2224/83951 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01082 , H01L2924/14 , H01L2924/15787 , H01L2924/3512 , H01L2924/00 , H01L2224/0401
摘要： An integrated circuit package which may include the dispense of a second encapsulant material (or fillet) different from the first underfill material on an integrated circuit package which may include an integrated circuit that is mounted to a substrate. The package may further have a first underfill material and a second underfill material that are attached to the integrated circuit and the substrate. The second encapsulant material may be tailored to inhibit cracking of the epoxy itself that propagates into the substrate during thermo-mechanical loading.

3. 发明授权

US06778727B2 Optic switch 失效
公开(公告)号：US06778727B2
公开(公告)日：2004-08-17
申请号：US10714414
申请日：2003-11-14
申请人： Suresh Ramalingam , Venkatesan Murali
发明人： Suresh Ramalingam , Venkatesan Murali
IPC分类号： G02B626
CPC分类号： G02F1/3132 , G02F1/0147 , G02F1/3137
摘要： An apparatus comprising a body having dimensions suitable for light transmission therethrough, the body comprising a core extending therethrough, a first portion of the core comprising an index of refraction different than a second portion of the core and a cladding disposed about the core. An optical electronic integrated circuit (OEIC) substrate comprising a plurality of waveguides and a light source emitter coupled to at least one of the plurality of waveguides. A method comprising providing optical signals to an optical electronic integrated circuit (OEIC) through a plurality of waveguides are arranged in a circuit of different paths; and selecting an optical path by the index of refraction of a portion of the core.

4. 发明授权

US07066657B2 Optical subassembly 有权
标题翻译：光学组件
公开(公告)号：US07066657B2
公开(公告)日：2006-06-27
申请号：US09752881
申请日：2000-12-28
申请人： Venkatesan Murali , Douglas E. Crafts , Suresh Ramalingam , Brett M. Zaborsky , Siegfried B. Fleischer
发明人： Venkatesan Murali , Douglas E. Crafts , Suresh Ramalingam , Brett M. Zaborsky , Siegfried B. Fleischer
IPC分类号： G02B6/42 , G02B6/30
CPC分类号： G02B6/4246 , G02B6/4214 , G02B6/4292
摘要： An apparatus including a base having a first opening of a dimension suitable to pass a light emission therethrough, a first side wall coupled to the base and having a second opening of a dimension suitable to pass a light emission therethrough, a second side wall coupled to the base and having a reflective component thereon, and the base, the first side wall, and the second side wall define an interior chamber with the reflective component disposed in the interior chamber; and a fiber connector extending from an exterior of the first side wall adjacent the second opening. A method including powering a laser disposed in a substrate coupling a fiber optic cable to an optical subassembly; and aligning the optical assembly over the transceiver board to capture the emitted light from the laser in the fiber optic cable.
摘要翻译：一种装置，包括具有第一开口的基座，该第一开口的尺寸适于通过其中的光发射;第一侧壁，其耦合到所述基座并且具有适于使光发射通过的尺寸的第二开口;第二侧壁，所述底座并且在其上具有反射部件，并且所述基座，所述第一侧壁和所述第二侧壁限定内部腔室，所述反射部件设置在所述内部腔室中; 以及从邻近第二开口的第一侧壁的外部延伸的光纤连接器。一种方法，包括为将光纤电缆耦合到光学子组件的基板中的激光器供电; 并且将光学组件对准在收发器板上以捕获来自光纤电缆中的激光器的发射光。

5. 发明申请

US20050117853A1 OPTICAL SUBASSEMBLY 有权
标题翻译：光学分层
公开(公告)号：US20050117853A1
公开(公告)日：2005-06-02
申请号：US09752881
申请日：2000-12-28
申请人： Venkatesan Murali , Douglas Crafts , Suresh Ramalingam , Brett Zaborsky , Siegfried Fleischer
发明人： Venkatesan Murali , Douglas Crafts , Suresh Ramalingam , Brett Zaborsky , Siegfried Fleischer
IPC分类号： G02B6/42 , G02B6/36
CPC分类号： G02B6/4246 , G02B6/4214 , G02B6/4292
摘要： An apparatus including a base having a first opening of a dimension suitable to pass a light emission therethrough, a first side wall coupled to the base and having a second opening of a dimension suitable to pass a light emission therethrough, a second side wall coupled to the base and having a reflective component thereon, and the base, the first side wall, and the second side wall define an interior chamber with the reflective component disposed in the interior chamber; and a fiber connector extending from an exterior of the first side wall adjacent the second opening. A method including powering a laser disposed in a substrate coupling a fiber optic cable to an optical subassembly; and aligning the optical assembly over the transceiver board to capture the emitted light from the laser in the fiber optic cable.
摘要翻译：一种装置，包括具有第一开口的基座，该第一开口的尺寸适于通过其中的光发射;第一侧壁，其耦合到所述基座并且具有适于使光发射通过的尺寸的第二开口;第二侧壁，所述底座并且在其上具有反射部件，并且所述基座，所述第一侧壁和所述第二侧壁限定内部腔室，所述反射部件设置在所述内部腔室中; 以及从邻近第二开口的第一侧壁的外部延伸的光纤连接器。一种方法，包括为将光纤电缆耦合到光学子组件的基板中的激光器供电; 并且将光学组件对准在收发器板上以捕获来自光纤电缆中的激光器的发射光。

6. 发明授权

US06687427B2 Optic switch 有权
公开(公告)号：US06687427B2
公开(公告)日：2004-02-03
申请号：US09752901
申请日：2000-12-29
申请人： Suresh Ramalingam , Venkatesan Murali
发明人： Suresh Ramalingam , Venkatesan Murali
IPC分类号： G02B626
CPC分类号： G02F1/3132 , G02F1/0147 , G02F1/3137
摘要： An apparatus comprising a body having dimensions suitable for light transmission therethrough, the body comprising a core extending therethrough, a first portion of the core comprising an index of refraction different than a second portion of the core and a cladding disposed about the core. An optical electronic integrated circuit (OEIC) substrate comprising a plurality of waveguides and a light source emitter coupled to at least one of the plurality of waveguides. A method comprising providing optical signals to an optical electronic integrated circuit (OEIC) through a plurality of waveguides are arranged in a circuit of different paths; and selecting an optical path by the index of refraction of a portion of the core.

7. 发明授权

US08886481B1 Reducing variation in multi-die integrated circuits 有权
标题翻译：减少多芯片集成电路的变化
公开(公告)号：US08886481B1
公开(公告)日：2014-11-11
申请号：US12835184
申请日：2010-07-13
申请人： Arifur Rahman , Michael J. Hart , Venkatesan Murali
发明人： Arifur Rahman , Michael J. Hart , Venkatesan Murali
IPC分类号： G06F19/00
CPC分类号： H01L22/20 , H01L22/14 , H01L2224/16225 , H01L2924/15311
摘要： A method of reducing variation in multi-die integrated circuits can include, for each of a plurality of dies, determining at least one performance metric and selecting at least two dies for inclusion within a multi-die integrated circuit according to the at least one performance metric. Systems and devices for executing the steps of the method are also described.
摘要翻译：减少多管芯集成电路中的变化的方法可以包括对于多个管芯中的每一个，确定至少一个性能度量并且根据至少一个性能选择至少两个管芯以包括在多管芯集成电路内度量。还描述了用于执行该方法的步骤的系统和设备。

8. 发明申请

US20140030836A1 Silicon Carbide Lamina 失效
标题翻译：碳化硅薄片
公开(公告)号：US20140030836A1
公开(公告)日：2014-01-30
申请号：US13558843
申请日：2012-07-26
申请人： Venkatesan Murali , Steve Babayan , Christopher J. Petti
发明人： Venkatesan Murali , Steve Babayan , Christopher J. Petti
IPC分类号： H01L33/02 , H01L21/762
CPC分类号： H01L33/0079 , H01L21/76254 , H01L29/2003 , H01L29/66462 , H01L29/7786 , H01L33/007
摘要： A method of fabricating an electronic device includes providing a silicon carbide or diamond-like carbon donor body and implanting ions into a first surface of the donor body to define a cleave plane. After implanting, an epitaxial layer is formed on the first surface, and a temporary carrier is coupled to the epitaxial layer. A lamina is cleaved from the donor body at the cleave plane, and the temporary carrier is removed from the lamina. In some embodiments a light emitting diode or a high electron mobility transistor is fabricated from the lamina and epitaxial layer.
摘要翻译：一种制造电子器件的方法包括提供碳化硅或类金刚石碳供体，并将离子注入施主体的第一表面以限定解理面。在注入之后，在第一表面上形成外延层，并且临时载体耦合到外延层。在切割平面处从供体体中切割薄层，并将临时载体从薄片上移除。在一些实施例中，从层板和外延层制造发光二极管或高电子迁移率晶体管。

9. 发明授权

US08518724B2 Method to form a device by constructing a support element on a thin semiconductor lamina 失效
标题翻译：通过在薄半导体层上构造支撑元件来形成器件的方法
公开(公告)号：US08518724B2
公开(公告)日：2013-08-27
申请号：US13450414
申请日：2012-04-18
申请人： Christopher J. Petti , Mohamed M. Hilali , Theodore Smick , Venkatesan Murali , Kathy J. Jackson , Zhiyong Li , Gopalakrishna Prabhu
发明人： Christopher J. Petti , Mohamed M. Hilali , Theodore Smick , Venkatesan Murali , Kathy J. Jackson , Zhiyong Li , Gopalakrishna Prabhu
IPC分类号： H01L21/00 , H01L31/00
CPC分类号： H01L31/1892 , H01L31/0747 , H01L31/1864 , Y02E10/50
摘要： A semiconductor assembly is described in which a support element is constructed on a surface of a semiconductor lamina. Following formation of the thin lamina, which may have a thickness about 50 microns or less, the support element is formed, for example by plating, or by application of a precursor and curing in situ, resulting in a support element which may be, for example, metal, ceramic, polymer, etc. This is in contrast to pre-formed support element which is affixed to the lamina following its formation, or to a donor wafer from which the lamina is subsequently cleaved.Fabricating the support element in situ may avoid the use of adhesives to attach the lamina to a permanent support element. In some embodiments, this process flow allows the lamina to be annealed at high temperature, then to have an amorphous silicon layer formed on each face of the lamina following that anneal.
摘要翻译：描述了半导体组件，其中在半导体层的表面上构造支撑元件。形成厚度约为50微米或更小的薄层之后，例如通过镀覆或通过施加前体和原位固化来形成支撑元件，得到支撑元件，其可以用于例如，金属，陶瓷，聚合物等。这与预先形成的支撑元件形成对比，该预制形成的支撑元件在其形成之后固定到层板上，或者与施加器晶片相接触，该晶片随后被切割。原位制造支撑元件可以避免使用粘合剂将薄片附着到永久支撑元件上。在一些实施例中，该工艺流程允许薄层在高温下退火，然后在该退火之后具有在层的每个表面上形成的非晶硅层。

10. 发明授权

US06219910B1 Method for cutting integrated circuit dies from a wafer which contains a plurality of solder bumps 有权
标题翻译：用于从包含多个焊料凸块的晶片切割集成电路管芯的方法
公开(公告)号：US06219910B1
公开(公告)日：2001-04-24
申请号：US09263118
申请日：1999-03-05
申请人： Venkatesan Murali
发明人： Venkatesan Murali
IPC分类号： H05K334
CPC分类号： H01L24/11 , H01L2224/05568 , H01L2224/05573 , H01L2224/13099 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , Y10T29/49144 , Y10T29/53178 , H01L2224/05599
摘要： A method for cutting an integrated circuit die from a wafer. The method may include the step of forming a solder bump on an integrated circuit wafer. The solder bump is then oxidized. The oxidization process may form an outer oxidized layer on the solder bump. An integrated circuit die is cut from the wafer after the oxidization step. The cutting process may include spraying a fluid onto the wafer. The oxidized solder may form a protective layer which reduces the amount of particles and lead hydroxide formed during the cutting process. The integrated circuit die may be mounted to a package substrate by reflowing the solder bump onto a pad of the substrate. The outer oxidized layer may be removed with a flux that is used to reflow the solder bump onto the substrate.
摘要翻译：一种用于从晶片切割集成电路管芯的方法。该方法可以包括在集成电路晶片上形成焊料凸块的步骤。焊料凸点然后被氧化。氧化过程可以在焊料凸块上形成外部氧化层。在氧化步骤之后从晶片切割集成电路管芯。切割过程可以包括将流体喷涂到晶片上。氧化的焊料可以形成保护层，其减少在切割过程中形成的颗粒和氢氧化铅的量。集成电路管芯可以通过将焊料凸块回流到衬底的焊盘上而被安装到封装衬底。外部氧化层可以用用于将焊料凸块回流到衬底上的焊剂去除。

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