专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07494599B2 Method for fabricating fine pattern in semiconductor device 失效
标题翻译：在半导体器件中制造精细图案的方法
公开(公告)号：US07494599B2
公开(公告)日：2009-02-24
申请号：US11742288
申请日：2007-04-30
申请人： Sung-Kwon Lee , Seung-Chan Moon , Won-Kyu Kim
发明人： Sung-Kwon Lee , Seung-Chan Moon , Won-Kyu Kim
IPC分类号： B44C1/22
CPC分类号： H01L21/0332 , Y10T428/2826
摘要： A method for forming a fine pattern in a semiconductor device includes forming a first polymer layer over an etch target layer, the first polymer layer including a carbon-rich polymer layer, forming a second polymer layer over the first polymer layer, the second polymer layer including a silicon-rich polymer layer, patterning the second polymer layer, oxidizing surfaces of the patterned second polymer layer, etching the first polymer layer using the patterned second polymer layer comprising the oxidized surfaces, and etching the etch target layer using the patterned second polymer layer comprising the oxidized surfaces and the etched first polymer layer.
摘要翻译：在半导体器件中形成精细图案的方法包括在蚀刻目标层上形成第一聚合物层，第一聚合物层包括富碳聚合物层，在第一聚合物层上形成第二聚合物层，第二聚合物层包括富含硅的聚合物层，图案化第二聚合物层，氧化图案化的第二聚合物层的表面，使用包含氧化表面的图案化的第二聚合物层蚀刻第一聚合物层，以及使用图案化的第二聚合物层，其包含氧化表面和蚀刻的第一聚合物层。

2. 发明授权

US07442648B2 Method for fabricating semiconductor device using tungsten as sacrificial hard mask 有权
标题翻译：使用钨作为牺牲硬掩模制造半导体器件的方法
公开(公告)号：US07442648B2
公开(公告)日：2008-10-28
申请号：US11149325
申请日：2005-06-10
申请人： Kwang-Ok Kim , Yun-Seok Cho , Seung-Chan Moon , Jin-Ki Jung , Sung-Kwon Lee , Jun-Hyeub Sun , Dong-Duk Lee , Jin-Woong Kim , Gyu-Han Yoon
发明人： Kwang-Ok Kim , Yun-Seok Cho , Seung-Chan Moon , Jin-Ki Jung , Sung-Kwon Lee , Jun-Hyeub Sun , Dong-Duk Lee , Jin-Woong Kim , Gyu-Han Yoon
IPC分类号： H01L21/302
CPC分类号： H01L21/76802 , H01L21/0332 , H01L21/28123 , H01L21/31116 , H01L21/31144 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L27/10894
摘要： The present invention relates to a method for fabricating a semiconductor device using tungsten as a sacrificial hard mask material. The method includes the steps of: forming a layer on an etch target layer; forming a photoresist pattern on the layer; etching the layer by using the photoresist pattern as an etch mask along with use of a plasma containing CHF3 gas to form a sacrificial hard mask; and etching the etch target layer by using at least the sacrificial hard mask as an etch mask, thereby obtaining a predetermined pattern.
摘要翻译：本发明涉及使用钨作为牺牲硬掩模材料制造半导体器件的方法。该方法包括以下步骤：在蚀刻目标层上形成层; 在该层上形成光致抗蚀剂图案; 通过使用光致抗蚀剂图案作为蚀刻掩模以及使用含有CHF 3 N 3气体的等离子体来蚀刻该层以形成牺牲性硬掩模; 并且通过使用至少牺牲硬掩模作为蚀刻掩模来蚀刻蚀刻目标层，由此获得预定图案。

3. 发明申请

US20060079093A1 Method for fabricating semiconductor device using tungsten as sacrificial hard mask 有权
标题翻译：使用钨作为牺牲硬掩模制造半导体器件的方法
公开(公告)号：US20060079093A1
公开(公告)日：2006-04-13
申请号：US11149325
申请日：2005-06-10
申请人： Kwang-Ok Kim , Yun-Seok Cho , Seung-Chan Moon , Jin-Ki Jung , Sung-Kwon Lee , Jun-Hyeub Sun , Dong-Duk Lee , Jin-Woong Kim , Gyu-Han Yoon
发明人： Kwang-Ok Kim , Yun-Seok Cho , Seung-Chan Moon , Jin-Ki Jung , Sung-Kwon Lee , Jun-Hyeub Sun , Dong-Duk Lee , Jin-Woong Kim , Gyu-Han Yoon
IPC分类号： H01L21/461
CPC分类号： H01L21/76802 , H01L21/0332 , H01L21/28123 , H01L21/31116 , H01L21/31144 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L27/10894
摘要： The present invention relates to a method for fabricating a semiconductor device using tungsten as a sacrificial hard mask material. The method includes the steps of: forming a layer on an etch target layer; forming a photoresist pattern on the layer; etching the layer by using the photoresist pattern as an etch mask along with use of a plasma containing CHF3 gas to form a sacrificial hard mask; and etching the etch target layer by using at least the sacrificial hard mask as an etch mask, thereby obtaining a predetermined pattern.
摘要翻译：本发明涉及使用钨作为牺牲硬掩模材料制造半导体器件的方法。该方法包括以下步骤：在蚀刻目标层上形成层; 在该层上形成光致抗蚀剂图案; 通过使用光致抗蚀剂图案作为蚀刻掩模以及使用含有CHF 3 N 3气体的等离子体来蚀刻该层以形成牺牲硬掩模; 并且通过使用至少牺牲硬掩模作为蚀刻掩模来蚀刻蚀刻目标层，由此获得预定图案。

4. 发明授权

US07589026B2 Method for fabricating a fine pattern in a semiconductor device 失效
标题翻译：在半导体器件中制造精细图案的方法
公开(公告)号：US07589026B2
公开(公告)日：2009-09-15
申请号：US11743669
申请日：2007-05-03
申请人： Sung-Kwon Lee , Jae-Young Lee
发明人： Sung-Kwon Lee , Jae-Young Lee
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31144 , H01L21/0332 , H01L21/31122 , H01L21/31138
摘要： A method for fabricating a fine pattern in a semiconductor device includes forming a first polymer layer and a second polymer layer over an etch target layer. The second polymer layer is patterned at a first substrate temperature. The first polymer layer is etched at a second substrate temperature using an etch gas that does not include oxygen (O2). The first polymer layer is etched using the patterned second polymer layer as an etch mask. The etch target layer is then etched using the etched first polymer layer and the etched second polymer layer as an etch mask.
摘要翻译：在半导体器件中制造精细图案的方法包括在蚀刻目标层上形成第一聚合物层和第二聚合物层。第二聚合物层在第一衬底温度下被图案化。使用不包括氧（O 2）的蚀刻气体在第二衬底温度下蚀刻第一聚合物层。使用图案化的第二聚合物层作为蚀刻掩模蚀刻第一聚合物层。然后使用蚀刻的第一聚合物层和蚀刻的第二聚合物层作为蚀刻掩模蚀刻蚀刻目标层。

5. 发明授权

US07534553B2 Method for fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07534553B2
公开(公告)日：2009-05-19
申请号：US11264427
申请日：2005-10-31
申请人： Sung-Kwon Lee , Gyu-Dong Park
发明人： Sung-Kwon Lee , Gyu-Dong Park
IPC分类号： G03F7/26
CPC分类号： H01L21/02118 , G03F7/09 , H01L21/022 , H01L21/02337 , H01L21/312
摘要： A method for fabricating a semiconductor device is provided. The method includes: preparing a substrate defined as active regions and inactive regions and provided with a plurality of conductive patterns; forming a buffer layer over the plurality of conductive patterns; forming an organic material having fluidity better than that of a photoresist layer on the buffer layer; flowing the organic material between the conductive patterns through a thermal treatment process, thereby filling a portion of each gap between the conductive patterns; forming the photoresist layer over the organic material and the buffer layer; forming a plurality of photoresist patterns opening the active regions through a photo-exposure process and a developing process; and performing an ion-implantation process using the plurality of photoresist patterns, thereby forming a plurality of junction regions in the active regions of the substrate.
摘要翻译：提供一种制造半导体器件的方法。该方法包括：制备定义为有源区和非活性区的衬底，并设置有多个导电图案; 在所述多个导电图案上形成缓冲层; 形成流动性优于缓冲层上的光致抗蚀剂层的有机材料; 通过热处理工艺使有机材料在导电图案之间流动，由此填充导电图案之间的每个间隙的一部分; 在有机材料和缓冲层上形成光致抗蚀剂层; 形成通过曝光过程和显影过程打开活性区域的多个光致抗蚀剂图案; 以及使用所述多个光致抗蚀剂图案进行离子注入工艺，从而在所述衬底的有源区域中形成多个结区域。

6. 发明申请

US20080293212A1 METHOD FOR FORMING STORAGE NODE OF CAPACITOR IN SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中形成电容器存储节点的方法
公开(公告)号：US20080293212A1
公开(公告)日：2008-11-27
申请号：US12168823
申请日：2008-07-07
申请人： Jun-Hyeub Sun , Sung-Kwon Lee , Sung-Yoon Cho
发明人： Jun-Hyeub Sun , Sung-Kwon Lee , Sung-Yoon Cho
IPC分类号： H01L21/02
CPC分类号： H01L21/76897 , H01L27/10855 , H01L28/90
摘要： A method for forming a capacitor in a semiconductor device comprises forming an inter-layer layer on a semi-finished substrate; etching the inter-layer insulation layer to form a plurality of first contact holes; forming a first insulation layer on sidewalls of the first contact holes; forming a plurality of storage-node contact plugs filled into the first contact holes; forming a second insulation layer with a different etch rate from the first insulation layer over the storage-node contact plugs; forming a third insulation layer on the second insulation layer; sequentially etching the third insulation layer and the second insulation layer to form a plurality of second contact holes exposing the storage-node contact plugs; and forming the storage node on each of the second contact holes.
摘要翻译：一种在半导体器件中形成电容器的方法包括在半成品衬底上形成层间层; 蚀刻层间绝缘层以形成多个第一接触孔; 在所述第一接触孔的侧壁上形成第一绝缘层; 形成填充到所述第一接触孔中的多个存储节点接触插塞; 在所述存储节点接触插塞上形成具有与所述第一绝缘层不同的蚀刻速率的第二绝缘层; 在所述第二绝缘层上形成第三绝缘层; 依次蚀刻第三绝缘层和第二绝缘层，以形成暴露存储节点接触插塞的多个第二接触孔; 以及在所述第二接触孔中的每一个上形成所述存储节点。

7. 发明授权

US07405091B2 Method for testing contact open in semicoductor device 失效
标题翻译：在半导体器件中测试接触开路的方法
公开(公告)号：US07405091B2
公开(公告)日：2008-07-29
申请号：US11020599
申请日：2004-12-21
申请人： Sung-Kwon Lee , Tae-Woo Jung , Min-Suk Lee
发明人： Sung-Kwon Lee , Tae-Woo Jung , Min-Suk Lee
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： The present invention is a method for testing a contact open capable of effectively testing a contact open defect in an In-line as securing a mass productivity. The method includes the steps of: performing a photolithography process for forming a contact; forming a contact hole by performing a contact etching process after sampling at least one wafer; depositing a conductive layer on the wafer provided with the contact hole; isolating the conductive layer within the contact hole; performing a test for testing a contact open interface to check whether a remaining layer is existed in an interface between the conductive layer and a lower structure of the conductive layer; and performing a process for etching the contact of a main lot based on a test result.
摘要翻译：本发明是一种用于测试接触开口的方法，其能够有效地测试在线的接触开口缺陷以确保批量生产率。该方法包括以下步骤：执行用于形成接触的光刻工艺; 在对至少一个晶片取样之后进行接触蚀刻工艺形成接触孔; 在设置有接触孔的晶片上沉积导电层; 隔离接触孔内的导电层; 执行用于测试接触开放界面的测试以检查导电层和导电层的下部结构之间的界面中是否存在剩余层; 并且基于测试结果执行蚀刻主批次的接触的处理。

8. 发明授权

US07365000B2 Method for fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07365000B2
公开(公告)日：2008-04-29
申请号：US10876783
申请日：2004-06-28
申请人： Sung-Kwon Lee , Min-Suk Lee
发明人： Sung-Kwon Lee , Min-Suk Lee
IPC分类号： H01L21/4763 , H01L21/76
CPC分类号： H01L21/02063 , H01L21/02046 , H01L21/02052 , H01L21/02164 , H01L21/022 , H01L21/02211 , H01L21/02222 , H01L21/02274 , H01L21/02282 , H01L21/02337 , H01L21/31116 , H01L21/3125 , H01L21/316 , H01L21/31612 , H01L21/76837 , H01L21/76897 , H01L21/823475
摘要： Disclosed is a method for fabricating a semiconductor device capable of preventing an inter-layer insulation layer from being damaged during a wet cleaning process due to a density difference created by reliance on a thickness of a SOG layer subjected to a curing process and of overcoming defects caused by an improper contact opening in a certain region and a punch taken place by micro voids of an APL layer. Particularly, the method includes the steps of: forming a plurality of conductive structure on a substrate; forming a spin-on-glass layer; curing the spin-on-glass layer; forming an advanced-planarization-layer on the spin-on-glass layer; and forming a plurality of contact holes by selectively etching the advanced-planarization-layer and the spin-on-glass layer, thereby exposing portions of the substrate.
摘要翻译：公开了一种制造半导体器件的方法，该半导体器件能够防止层间绝缘层在湿式清洁过程中由于依赖于经历固化过程的SOG层的厚度和克服缺陷而产生的密度差而被损坏这是由于某个区域的接触开口不正确以及由APL层的微小空隙发生的冲击造成的。特别地，该方法包括以下步骤：在衬底上形成多个导电结构; 形成旋涂玻璃层; 固化旋涂玻璃层; 在旋涂玻璃层上形成先进的平面化层; 以及通过选择性地蚀刻高级平坦化层和旋涂玻璃层而形成多个接触孔，从而暴露基板的部分。

9. 发明申请

US20080081446A1 Method for fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20080081446A1
公开(公告)日：2008-04-03
申请号：US11904401
申请日：2007-09-27
申请人： Sung-Kwon Lee , Min-Suk Lee
发明人： Sung-Kwon Lee , Min-Suk Lee
IPC分类号： H01L21/3205
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/31144
摘要： A method for fabricating a semiconductor device includes forming a first pattern over a substrate, forming an oxide-based layer over the first pattern, forming a hard mask layer over the oxide-based layer, etching the hard mask layer at a first substrate temperature, and etching the oxide-based layer to form a second pattern, wherein the oxide-based layer is etched at a second substrate temperature which is greater than the first substrate temperature using a gas including fluorine (F) and carbon (C) as a main etch gas.
摘要翻译：一种制造半导体器件的方法包括在衬底上形成第一图案，在第一图案上形成氧化物基层，在氧化物基层上形成硬掩模层，在第一衬底温度下蚀刻硬掩模层，并且蚀刻所述氧化物基层以形成第二图案，其中所述氧化物基层在使用包含氟（F）和碳（C））为主要气体的第二基板温度下蚀刻，所述第二基板温度大于所述第一基板温度蚀刻气体。

10. 发明授权

US07314792B2 Method for fabricating transistor of semiconductor device 有权
标题翻译：制造半导体器件晶体管的方法
公开(公告)号：US07314792B2
公开(公告)日：2008-01-01
申请号：US11321591
申请日：2005-12-30
申请人： Myung-Ok Kim , Tae-Woo Jung , Sung-Kwon Lee , Sea-Ug Jang
发明人： Myung-Ok Kim , Tae-Woo Jung , Sung-Kwon Lee , Sea-Ug Jang
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/331 , H01L21/76
CPC分类号： H01L21/31116 , H01L29/66621
摘要： A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to form a plurality of recess structures each of which has a flat bottom portion with a critical dimension (CD) larger than that of a top portion; and sequentially forming a gate oxide layer and a metal layer on the recess structures; and patterning the gate oxide layer and the metal layer to form a plurality of gate structures.
摘要翻译：提供一种制造半导体器件的晶体管的方法。该方法包括：在包括底部结构的衬底中形成器件隔离层，从而限定有源区; 将活性区域蚀刻到预定深度以形成多个凹部结构，每个凹部结构具有平坦的底部，其临界尺寸（CD）大于顶部部分的临界尺寸; 并且在所述凹部结构上依次形成栅极氧化物层和金属层; 以及图案化栅极氧化物层和金属层以形成多个栅极结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式