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1. 发明授权

US06703314B2 Method for fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06703314B2
公开(公告)日：2004-03-09
申请号：US10308139
申请日：2002-12-03
申请人： Sung-Kwon Lee , Sang-Ik Kim , Chang-Youn Hwang , Weon-Joon Suh , Min-Suk Lee
发明人： Sung-Kwon Lee , Sang-Ik Kim , Chang-Youn Hwang , Weon-Joon Suh , Min-Suk Lee
IPC分类号： H01L21302
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/7682
摘要： Provided is a method for forming a self aligned contact (SAC) of a semiconductor device that can minimize the loss of gate electrodes and hard mask. The method includes the steps of: providing a semiconductor substrate on which a plurality of conductive patterns are formed; forming a first insulation layer along the profile of the conductive patterns on the substrate; forming a second insulation layer on the substrate and simultaneously forming voids between the conductive patterns; forming a third insulation layer on the first insulation layer; and forming contact holes that expose the surface of the substrate between the conductive patterns by etching the third insulation layer and the second insulation layer covering the voids.
摘要翻译：提供一种用于形成可以最小化栅电极和硬掩模的损耗的半导体器件的自对准接触（SAC）的方法。该方法包括以下步骤：提供其上形成有多个导电图案的半导体衬底; 沿着衬底上的导电图案的轮廓形成第一绝缘层; 在所述基板上形成第二绝缘层，同时在所述导电图案之间形成空隙; 在所述第一绝缘层上形成第三绝缘层; 以及形成通过蚀刻所述第三绝缘层和覆盖所述空隙的所述第二绝缘层而在所述导电图案之间暴露所述基板的表面的接触孔。

2. 发明授权

US06867145B2 Method for fabricating semiconductor device using photoresist pattern formed with argon fluoride laser 失效
标题翻译：使用由氟化氢激光形成的光致抗蚀剂图案制造半导体器件的方法
公开(公告)号：US06867145B2
公开(公告)日：2005-03-15
申请号：US10320718
申请日：2002-12-17
申请人： Sung-Kwon Lee , Sang-Ik Kim , Chang-Youn Hwang
发明人： Sung-Kwon Lee , Sang-Ik Kim , Chang-Youn Hwang
IPC分类号： H01L21/311 , H01L21/60 , H01L21/302
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76831
摘要： The present invention provides a method for fabricating a semiconductor device with use of an ArF light source capable of minimizing deformations of a photoresist pattern for ArF during an etching process. Also, when forming the pattern, C5F8 gas is used at a main etching step to compensate etch tolerance of the photoresist for ArF. By controlling process recipe properly, it is possible to minimize pattern deformations as simultaneously as to form a micronized pattern. To compensate the etch tolerance of the photoresist for ArF weaker than that of a photoresist for KrF, the main etching step is divided into three sub-steps, thereby providing a method for minimizing the pattern deformations when duplicating the pattern.
摘要翻译：本发明提供一种使用能在蚀刻过程中使ArF的光刻胶图案的变形最小化的ArF光源来制造半导体器件的方法。此外，当形成图案时，在主蚀刻步骤中使用C5F8气体来补偿用于ArF的光致抗蚀剂的蚀刻耐受性。通过适当地控制工艺配方，可以同时形成微粉化图案来最小化图案变形。为了补偿光致抗蚀剂对于用于KrF的光致抗蚀剂的蚀刻耐受性弱，主蚀刻步骤被分为三个子步骤，从而提供了当复制图案时最小化图案变形的方法。

3. 发明授权

US06569778B2 Method for forming fine pattern in semiconductor device 有权
公开(公告)号：US06569778B2
公开(公告)日：2003-05-27
申请号：US10166133
申请日：2002-06-10
申请人： Sung-Kwon Lee , Chang-Youn Hwang
发明人： Sung-Kwon Lee , Chang-Youn Hwang
IPC分类号： H01L21461
CPC分类号： H01L21/76897 , H01L21/0276 , H01L21/31116 , H01L21/76804
摘要： A fine pattern forming method of a semiconductor device sequentially deposits an etch-target layer to be formed as the fine pattern, an anti-reflective layer and a photoresist film on a prepared semiconductor substrate and forms a photoresist pattern by performing photolithography for the photoresist film with an ArF exposure source. Then, two etching processes are performed to form the fine pattern. In one etching process, there are etched the anti-reflective layer and a portion of a non-pattern area of the etch-target layer at a first substrate temperature with fluorine-based gas and argon gas by using the photoresist pattern as an etching mask. In the other etching process, there is etched a remaining portion of the non-pattern area of the etch-target layer at a second substrate temperature higher than the first substrate temperature with fluorine-based gas and argon gas.

4. 发明授权

US07745331B2 Method for fabricating contact plug in semiconductor device 有权
标题翻译：半导体器件接触插头的制造方法
公开(公告)号：US07745331B2
公开(公告)日：2010-06-29
申请号：US11646062
申请日：2006-12-27
申请人： Chang-Youn Hwang
发明人： Chang-Youn Hwang
IPC分类号： H01L21/44
CPC分类号： H01L21/76804 , H01L21/76831
摘要： An insulation layer including a landing plug is formed over a substrate. An amorphous carbon hard mask is formed over a certain portion of the insulation layer. The insulation layer is etched using the amorphous carbon hard mask to form a storage node contact hole exposing the landing plug. A conductive material is formed in the storage node contact hole to form a storage node contact plug. Other embodiments are also described.
摘要翻译：在基板上形成包括着陆塞的绝缘层。在绝缘层的某一部分上形成无定形碳硬掩模。使用无定形碳硬掩模蚀刻绝缘层，以形成暴露着陆塞的存储节点接触孔。在存储节点接触孔中形成导电材料以形成存储节点接触插塞。还描述了其它实施例。

5. 发明申请

US20070123040A1 Method for forming storage node contact plug in semiconductor device 有权
标题翻译：在半导体器件中形成存储节点接触插头的方法
公开(公告)号：US20070123040A1
公开(公告)日：2007-05-31
申请号：US11418720
申请日：2006-05-05
申请人： Chang-Youn Hwang , Hyung-Hwan Kim , Ik-Soo Choi , Hae-Jung Lee
发明人： Chang-Youn Hwang , Hyung-Hwan Kim , Ik-Soo Choi , Hae-Jung Lee
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/76804 , H01L21/76831 , H01L27/10855
摘要： A method for forming a storage node contact plug in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer over a substrate having a conductive plug; etching a portion of the inter-layer insulation layer using at least line type storage node contact masks as an etch mask to form a first contact hole with sloping sidewalls; etching another portion of the inter-layer insulation layer underneath the first contact hole to form a second contact hole exposing the conductive plug, the second contact hole having substantially vertical sidewalls; and filling the first and second storage node contact holes to form a storage node contact plug.
摘要翻译：提供一种在半导体器件中形成存储节点接触插头的方法。该方法包括：在具有导电插塞的基板上形成层间绝缘层; 使用至少线型存储节点接触掩模作为蚀刻掩模蚀刻层间绝缘层的一部分，以形成具有倾斜侧壁的第一接触孔; 蚀刻在第一接触孔下面的层间绝缘层的另一部分，以形成露出导电插塞的第二接触孔，第二接触孔具有基本垂直的侧壁; 以及填充所述第一和第二存储节点接触孔以形成存储节点接触插头。

6. 发明申请

US20050153535A1 Method for forming contact in semiconductor device 失效
标题翻译：在半导体器件中形成接触的方法
公开(公告)号：US20050153535A1
公开(公告)日：2005-07-14
申请号：US10882698
申请日：2004-06-29
申请人： Chang-Youn Hwang , Bong-Ho Choi , Jung-Geun Kim
发明人： Chang-Youn Hwang , Bong-Ho Choi , Jung-Geun Kim
IPC分类号： H01L21/28 , H01L21/306 , H01L21/311 , H01L21/3213 , H01L21/44 , H01L21/4763 , H01L21/60 , H01L21/768
CPC分类号： H01L21/76897 , H01L21/02052 , H01L21/31116 , H01L21/31144 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L21/76801 , H01L21/76802 , H01L21/76831
摘要： Disclosed is a method for forming a contact in a semiconductor device. The method includes the steps of: forming a bit line on a substrate; forming an oxide layer made of high density plasma (HDP) oxide on a substrate structure including the bit line and the substrate; forming a hard mask on the oxide layer; and performing an etching process for forming a storage node contact, wherein the etching process is performed after the bit line, the oxide layer and the hard mask are formed with a predetermined thickness and a predetermined tensile stress such that a total compressive stress value of the bit line, the oxide layer and the hard mask layer is less than a critical value of a lifting phenomenon.
摘要翻译：公开了一种在半导体器件中形成接触的方法。该方法包括以下步骤：在衬底上形成位线; 在包括所述位线和所述衬底的衬底结构上形成由高密度等离子体（HDP）氧化物制成的氧化物层; 在氧化物层上形成硬掩模; 以及进行用于形成存储节点接触的蚀刻工艺，其中在所述位线，所述氧化物层和所述硬掩模形成预定厚度和预定拉伸应力之后执行所述蚀刻工艺，使得所述蚀刻工艺的总压缩应力值位线，氧化物层和硬掩模层小于提升现象的临界值。

7. 发明申请

US20080003798A1 Method for fabricating contact plug in semiconductor device 有权
标题翻译：半导体器件接触插头的制造方法
公开(公告)号：US20080003798A1
公开(公告)日：2008-01-03
申请号：US11646062
申请日：2006-12-27
申请人： Chang-Youn Hwang
发明人： Chang-Youn Hwang
IPC分类号： H01L21/44
CPC分类号： H01L21/76804 , H01L21/76831
摘要： An insulation layer including a landing plug is formed over a substrate. An amorphous carbon hard mask is formed over a certain portion of the insulation layer. The insulation layer is etched using the amorphous carbon hard mask to form a storage node contact hole exposing the landing plug. A conductive material is formed in the storage node contact hole to form a storage node contact plug. Other embodiments are also described.
摘要翻译：在基板上形成包括着陆塞的绝缘层。在绝缘层的某一部分上形成无定形碳硬掩模。使用无定形碳硬掩模蚀刻绝缘层，以形成暴露着陆塞的存储节点接触孔。在存储节点接触孔中形成导电材料以形成存储节点接触插塞。还描述了其它实施例。

8. 发明申请

US20060292498A1 Method for forming contact hole in semiconductor device 审中-公开
标题翻译：在半导体器件中形成接触孔的方法
公开(公告)号：US20060292498A1
公开(公告)日：2006-12-28
申请号：US11319369
申请日：2005-12-29
申请人： Chang-Youn Hwang , Dong-Duk Lee , Ik-Soo Choi , Hong-Gu Lee
发明人： Chang-Youn Hwang , Dong-Duk Lee , Ik-Soo Choi , Hong-Gu Lee
IPC分类号： G03F7/26
CPC分类号： H01L21/76831 , H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76802 , H01L21/76829
摘要： A method for forming a contact hole in a semiconductor device includes preparing a substrate including a bottom structure; forming an insulation layer such that the insulation layer covers the bottom structure; forming a silicon-rich oxynitride layer on the insulation layer; forming a photoresist pattern on the silicon-rich oxynitride layer; etching the silicon-rich oxynitride layer using the photoresist pattern as an etch mask, thereby obtaining hard masks; and etching the insulation layer using the photoresist pattern and the hard masks as an etch mask to form a contact hole exposing a portion of the bottom structure.
摘要翻译：一种在半导体器件中形成接触孔的方法包括：制备包括底部结构的衬底; 形成绝缘层，使得绝缘层覆盖底部结构; 在所述绝缘层上形成富硅氧氮化物层; 在富硅氧氮化物层上形成光致抗蚀剂图案; 使用光致抗蚀剂图案作为蚀刻掩模蚀刻富硅氧氮化物层，由此获得硬掩模; 以及使用光致抗蚀剂图案和硬掩模作为蚀刻掩模来蚀刻绝缘层，以形成暴露底部结构的一部分的接触孔。

9. 发明授权

US07226829B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07226829B2
公开(公告)日：2007-06-05
申请号：US10749533
申请日：2003-12-30
申请人： Chang-Youn Hwang , Dong-Sauk Kim , Jin-Ki Jung
发明人： Chang-Youn Hwang , Dong-Sauk Kim , Jin-Ki Jung
IPC分类号： H01L21/8238
CPC分类号： H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： The present invention is related to a method for forming a storage node of a semiconductor device. The method includes the steps of: (a) forming a plurality of bit line patterns, each including a wire and a hard mask sequentially stacked on a surface of a substrate structure; (b) sequentially forming a first barrier layer and a first inter-layer insulation layer along a profile containing bit line patterns until filling spaces between the bit line patterns; (c) etching the first inter-layer insulation layer until a partial portion of the first inter-layer insulation layer remains on each space between the bit line patterns; (d) forming a second barrier layer on the first inter-layer insulation layer and the first barrier layer; and (e) etching the first and the second barrier layers and the remaining first inter-layer insulation layer to expose a surface of the substrate structure disposed between the bit line patterns.
摘要翻译：本发明涉及一种用于形成半导体器件的存储节点的方法。该方法包括以下步骤：（a）形成多个位线图案，每个位线图案包括依次层叠在基板结构的表面上的导线和硬掩模; （b）沿着包含位线图形的轮廓依次形成第一阻挡层和第一层间绝缘层，直到填充位线图形之间的空间; （c）蚀刻第一层间绝缘层，直到第一层间绝缘层的部分部分保留在位线图案之间的每个空间上; （d）在第一层间绝缘层和第一阻挡层上形成第二阻挡层; 和（e）蚀刻第一和第二阻挡层和剩余的第一层间绝缘层以暴露位于位线图案之间的衬底结构的表面。

10. 发明授权

US07427564B2 Method for forming storage node contact plug in semiconductor device 有权
标题翻译：在半导体器件中形成存储节点接触插头的方法
公开(公告)号：US07427564B2
公开(公告)日：2008-09-23
申请号：US11418720
申请日：2006-05-05
申请人： Chang-Youn Hwang , Hyung-Hwan Kim , Ik-Soo Choi , Hae-Jung Lee
发明人： Chang-Youn Hwang , Hyung-Hwan Kim , Ik-Soo Choi , Hae-Jung Lee
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/76804 , H01L21/76831 , H01L27/10855
摘要： A method for forming a storage node contact plug in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer over a substrate having a conductive plug; etching a portion of the inter-layer insulation layer using at least line type storage node contact masks as an etch mask to form a first contact hole with sloping sidewalls; etching another portion of the inter-layer insulation layer underneath the first contact hole to form a second contact hole exposing the conductive plug, the second contact hole having substantially vertical sidewalls; and filling the first and second storage node contact holes to form a storage node contact plug.
摘要翻译：提供一种在半导体器件中形成存储节点接触插头的方法。该方法包括：在具有导电插塞的基板上形成层间绝缘层; 使用至少线型存储节点接触掩模作为蚀刻掩模蚀刻层间绝缘层的一部分，以形成具有倾斜侧壁的第一接触孔; 蚀刻在第一接触孔下面的层间绝缘层的另一部分，以形成露出导电插塞的第二接触孔，第二接触孔具有基本垂直的侧壁; 以及填充所述第一和第二存储节点接触孔以形成存储节点接触插头。

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