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1. 发明申请

US20060292498A1 Method for forming contact hole in semiconductor device 审中-公开
标题翻译：在半导体器件中形成接触孔的方法
公开(公告)号：US20060292498A1
公开(公告)日：2006-12-28
申请号：US11319369
申请日：2005-12-29
申请人： Chang-Youn Hwang , Dong-Duk Lee , Ik-Soo Choi , Hong-Gu Lee
发明人： Chang-Youn Hwang , Dong-Duk Lee , Ik-Soo Choi , Hong-Gu Lee
IPC分类号： G03F7/26
CPC分类号： H01L21/76831 , H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76802 , H01L21/76829
摘要： A method for forming a contact hole in a semiconductor device includes preparing a substrate including a bottom structure; forming an insulation layer such that the insulation layer covers the bottom structure; forming a silicon-rich oxynitride layer on the insulation layer; forming a photoresist pattern on the silicon-rich oxynitride layer; etching the silicon-rich oxynitride layer using the photoresist pattern as an etch mask, thereby obtaining hard masks; and etching the insulation layer using the photoresist pattern and the hard masks as an etch mask to form a contact hole exposing a portion of the bottom structure.
摘要翻译：一种在半导体器件中形成接触孔的方法包括：制备包括底部结构的衬底; 形成绝缘层，使得绝缘层覆盖底部结构; 在所述绝缘层上形成富硅氧氮化物层; 在富硅氧氮化物层上形成光致抗蚀剂图案; 使用光致抗蚀剂图案作为蚀刻掩模蚀刻富硅氧氮化物层，由此获得硬掩模; 以及使用光致抗蚀剂图案和硬掩模作为蚀刻掩模来蚀刻绝缘层，以形成暴露底部结构的一部分的接触孔。

2. 发明申请

US20060141696A1 Method for forming landing plug contact in semiconductor device 有权
标题翻译：在半导体器件中形成着陆插头接触的方法
公开(公告)号：US20060141696A1
公开(公告)日：2006-06-29
申请号：US11176714
申请日：2005-07-06
申请人： Ik-Soo Choi , Chang-Youn Hwang , Hong-Gu Lee
发明人： Ik-Soo Choi , Chang-Youn Hwang , Hong-Gu Lee
IPC分类号： H01L21/8244 , H01L21/3205 , H01L21/44 , H01L21/461
CPC分类号： H01L21/76897 , H01L21/7684 , H01L27/10888
摘要： A method for forming a landing contact plug in a semiconductor device is provided. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer over the gate structures; planarizing the inter-layer insulation layer until the gate hard mask is exposed; forming an etch barrier layer on the inter-layer insulation layer; etching a predetermined portion of the inter-layer insulation layer by using the etch barrier layer as an etch barrier to form a plurality of contact holes; forming a conductive layer until the conductive layer fills the contact holes; removing surface roughness created during the formation of the conductive layer by a first etch-back process; and planarizing the conductive layer by a second etch-back process until the gate hard mask is exposed.
摘要翻译：提供一种在半导体器件中形成着陆接触塞的方法。该方法包括以下步骤：在衬底上形成多个栅极结构，每个栅极结构包括栅极硬掩模; 在所述栅极结构上形成层间绝缘层; 平坦化层间绝缘层，直到栅极硬掩模露出; 在层间绝缘层上形成蚀刻阻挡层; 通过使用蚀刻阻挡层作为蚀刻阻挡层来蚀刻层间绝缘层的预定部分以形成多个接触孔; 形成导电层直到导电层填充接触孔; 通过第一回蚀工艺去除在形成导电层期间产生的表面粗糙度; 以及通过第二次回蚀工艺对导电层进行平坦化，直至露出栅极硬掩模。

3. 发明授权

US07419896B2 Method for forming landing plug contact in semiconductor device 有权
标题翻译：在半导体器件中形成着陆插头接触的方法
公开(公告)号：US07419896B2
公开(公告)日：2008-09-02
申请号：US11176714
申请日：2005-07-06
申请人： Ik-Soo Choi , Chang-Youn Hwang , Hong-Gu Lee
发明人： Ik-Soo Choi , Chang-Youn Hwang , Hong-Gu Lee
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/76897 , H01L21/7684 , H01L27/10888
摘要： A method for forming a landing contact plug in a semiconductor device is provided. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer over the gate structures; planarizing the inter-layer insulation layer until the gate hard mask is exposed; forming an etch barrier layer on the inter-layer insulation layer; etching a predetermined portion of the inter-layer insulation layer by using the etch barrier layer as an etch barrier to form a plurality of contact holes; forming a conductive layer until the conductive layer fills the contact holes; removing surface roughness created during the formation of the conductive layer by a first etch-back process; and planarizing the conductive layer by a second etch-back process until the gate hard mask is exposed.
摘要翻译：提供一种在半导体器件中形成着陆接触塞的方法。该方法包括以下步骤：在衬底上形成多个栅极结构，每个栅极结构包括栅极硬掩模; 在所述栅极结构上形成层间绝缘层; 平坦化层间绝缘层，直到栅极硬掩模露出; 在层间绝缘层上形成蚀刻阻挡层; 通过使用蚀刻阻挡层作为蚀刻阻挡层来蚀刻层间绝缘层的预定部分以形成多个接触孔; 形成导电层直到导电层填充接触孔; 通过第一回蚀工艺去除在形成导电层期间产生的表面粗糙度; 以及通过第二次回蚀工艺对导电层进行平坦化，直至露出栅极硬掩模。

4. 发明申请

US20070123040A1 Method for forming storage node contact plug in semiconductor device 有权
标题翻译：在半导体器件中形成存储节点接触插头的方法
公开(公告)号：US20070123040A1
公开(公告)日：2007-05-31
申请号：US11418720
申请日：2006-05-05
申请人： Chang-Youn Hwang , Hyung-Hwan Kim , Ik-Soo Choi , Hae-Jung Lee
发明人： Chang-Youn Hwang , Hyung-Hwan Kim , Ik-Soo Choi , Hae-Jung Lee
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/76804 , H01L21/76831 , H01L27/10855
摘要： A method for forming a storage node contact plug in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer over a substrate having a conductive plug; etching a portion of the inter-layer insulation layer using at least line type storage node contact masks as an etch mask to form a first contact hole with sloping sidewalls; etching another portion of the inter-layer insulation layer underneath the first contact hole to form a second contact hole exposing the conductive plug, the second contact hole having substantially vertical sidewalls; and filling the first and second storage node contact holes to form a storage node contact plug.
摘要翻译：提供一种在半导体器件中形成存储节点接触插头的方法。该方法包括：在具有导电插塞的基板上形成层间绝缘层; 使用至少线型存储节点接触掩模作为蚀刻掩模蚀刻层间绝缘层的一部分，以形成具有倾斜侧壁的第一接触孔; 蚀刻在第一接触孔下面的层间绝缘层的另一部分，以形成露出导电插塞的第二接触孔，第二接触孔具有基本垂直的侧壁; 以及填充所述第一和第二存储节点接触孔以形成存储节点接触插头。

5. 发明授权

US07427564B2 Method for forming storage node contact plug in semiconductor device 有权
标题翻译：在半导体器件中形成存储节点接触插头的方法
公开(公告)号：US07427564B2
公开(公告)日：2008-09-23
申请号：US11418720
申请日：2006-05-05
申请人： Chang-Youn Hwang , Hyung-Hwan Kim , Ik-Soo Choi , Hae-Jung Lee
发明人： Chang-Youn Hwang , Hyung-Hwan Kim , Ik-Soo Choi , Hae-Jung Lee
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/76804 , H01L21/76831 , H01L27/10855
摘要： A method for forming a storage node contact plug in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer over a substrate having a conductive plug; etching a portion of the inter-layer insulation layer using at least line type storage node contact masks as an etch mask to form a first contact hole with sloping sidewalls; etching another portion of the inter-layer insulation layer underneath the first contact hole to form a second contact hole exposing the conductive plug, the second contact hole having substantially vertical sidewalls; and filling the first and second storage node contact holes to form a storage node contact plug.
摘要翻译：提供一种在半导体器件中形成存储节点接触插头的方法。该方法包括：在具有导电插塞的基板上形成层间绝缘层; 使用至少线型存储节点接触掩模作为蚀刻掩模蚀刻层间绝缘层的一部分，以形成具有倾斜侧壁的第一接触孔; 蚀刻在第一接触孔下面的层间绝缘层的另一部分，以形成露出导电插塞的第二接触孔，第二接触孔具有基本垂直的侧壁; 以及填充所述第一和第二存储节点接触孔以形成存储节点接触插头。

6. 发明授权

US07709367B2 Method for fabricating storage node contact in semiconductor device 失效
标题翻译：在半导体器件中制造存储节点接触的方法
公开(公告)号：US07709367B2
公开(公告)日：2010-05-04
申请号：US11761577
申请日：2007-06-12
申请人： Hae-Jung Lee , Ik-Soo Choi , Chang-Youn Hwang , Mi-Hyune You
发明人： Hae-Jung Lee , Ik-Soo Choi , Chang-Youn Hwang , Mi-Hyune You
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/76804 , H01L27/105 , H01L27/1052 , H01L27/10855 , Y10S257/906 , Y10S257/912
摘要： A method for fabricating a storage node contact in a semiconductor device includes forming a landing plug over a substrate, forming a first insulation layer over the landing plug, forming a bit line pattern over the first insulation layer, forming a second insulation layer over the bit line pattern, forming a mask pattern for forming a storage node contact over the second insulation layer, etching the second and first insulation layers until the landing plug is exposed to form a storage node contact hole including a portion having a rounded profile, filling a conductive material in the storage node contact hole to form a contact plug, and forming a storage node over the contact plug.
摘要翻译：一种用于在半导体器件中制造存储节点接触的方法包括在衬底上形成着陆塞，在着陆塞上形成第一绝缘层，在第一绝缘层上形成位线图形，在该位上形成第二绝缘层形成用于在所述第二绝缘层上形成存储节点接触的掩模图案，蚀刻所述第二绝缘层和所述第一绝缘层，直到所述着陆塞被暴露以形成包括具有圆形轮廓的部分的存储节点接触孔，填充导电存储节点接触孔中的材料形成接触塞，并在接触插塞上形成存储节点。

7. 发明申请

US20080003811A1 METHOD FOR FABRICATING STORAGE NODE CONTACT IN SEMICONDUCTOR DEVICE 失效
标题翻译：在半导体器件中制造储存节点接触的方法
公开(公告)号：US20080003811A1
公开(公告)日：2008-01-03
申请号：US11761577
申请日：2007-06-12
申请人： Hae-Jung Lee , Ik-Soo Choi , Chang-Youn Hwang , Mi-Hyune You
发明人： Hae-Jung Lee , Ik-Soo Choi , Chang-Youn Hwang , Mi-Hyune You
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/76804 , H01L27/105 , H01L27/1052 , H01L27/10855 , Y10S257/906 , Y10S257/912
摘要： A method for fabricating a storage node contact in a semiconductor device includes forming a landing plug over a substrate, forming a first insulation layer over the landing plug, forming a bit line pattern over the first insulation layer, forming a second insulation layer over the bit line pattern, forming a mask pattern for forming a storage node contact over the second insulation layer, etching the second and first insulation layers until the landing plug is exposed to form a storage node contact hole including a portion having a rounded profile, filling a conductive material in the storage node contact hole to form a contact plug, and forming a storage node over the contact plug.
摘要翻译：一种用于在半导体器件中制造存储节点接触的方法包括在衬底上形成着陆塞，在着陆塞上形成第一绝缘层，在第一绝缘层上形成位线图形，在该位上形成第二绝缘层形成用于在所述第二绝缘层上形成存储节点接触的掩模图案，蚀刻所述第二绝缘层和所述第一绝缘层，直到所述着陆塞被暴露以形成包括具有圆形轮廓的部分的存储节点接触孔，填充导电存储节点接触孔中的材料形成接触塞，并在接触插塞上形成存储节点。

8. 发明授权

US07745331B2 Method for fabricating contact plug in semiconductor device 有权
标题翻译：半导体器件接触插头的制造方法
公开(公告)号：US07745331B2
公开(公告)日：2010-06-29
申请号：US11646062
申请日：2006-12-27
申请人： Chang-Youn Hwang
发明人： Chang-Youn Hwang
IPC分类号： H01L21/44
CPC分类号： H01L21/76804 , H01L21/76831
摘要： An insulation layer including a landing plug is formed over a substrate. An amorphous carbon hard mask is formed over a certain portion of the insulation layer. The insulation layer is etched using the amorphous carbon hard mask to form a storage node contact hole exposing the landing plug. A conductive material is formed in the storage node contact hole to form a storage node contact plug. Other embodiments are also described.
摘要翻译：在基板上形成包括着陆塞的绝缘层。在绝缘层的某一部分上形成无定形碳硬掩模。使用无定形碳硬掩模蚀刻绝缘层，以形成暴露着陆塞的存储节点接触孔。在存储节点接触孔中形成导电材料以形成存储节点接触插塞。还描述了其它实施例。

9. 发明申请

US20050153535A1 Method for forming contact in semiconductor device 失效
标题翻译：在半导体器件中形成接触的方法
公开(公告)号：US20050153535A1
公开(公告)日：2005-07-14
申请号：US10882698
申请日：2004-06-29
申请人： Chang-Youn Hwang , Bong-Ho Choi , Jung-Geun Kim
发明人： Chang-Youn Hwang , Bong-Ho Choi , Jung-Geun Kim
IPC分类号： H01L21/28 , H01L21/306 , H01L21/311 , H01L21/3213 , H01L21/44 , H01L21/4763 , H01L21/60 , H01L21/768
CPC分类号： H01L21/76897 , H01L21/02052 , H01L21/31116 , H01L21/31144 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L21/76801 , H01L21/76802 , H01L21/76831
摘要： Disclosed is a method for forming a contact in a semiconductor device. The method includes the steps of: forming a bit line on a substrate; forming an oxide layer made of high density plasma (HDP) oxide on a substrate structure including the bit line and the substrate; forming a hard mask on the oxide layer; and performing an etching process for forming a storage node contact, wherein the etching process is performed after the bit line, the oxide layer and the hard mask are formed with a predetermined thickness and a predetermined tensile stress such that a total compressive stress value of the bit line, the oxide layer and the hard mask layer is less than a critical value of a lifting phenomenon.
摘要翻译：公开了一种在半导体器件中形成接触的方法。该方法包括以下步骤：在衬底上形成位线; 在包括所述位线和所述衬底的衬底结构上形成由高密度等离子体（HDP）氧化物制成的氧化物层; 在氧化物层上形成硬掩模; 以及进行用于形成存储节点接触的蚀刻工艺，其中在所述位线，所述氧化物层和所述硬掩模形成预定厚度和预定拉伸应力之后执行所述蚀刻工艺，使得所述蚀刻工艺的总压缩应力值位线，氧化物层和硬掩模层小于提升现象的临界值。

10. 发明授权

US06703314B2 Method for fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06703314B2
公开(公告)日：2004-03-09
申请号：US10308139
申请日：2002-12-03
申请人： Sung-Kwon Lee , Sang-Ik Kim , Chang-Youn Hwang , Weon-Joon Suh , Min-Suk Lee
发明人： Sung-Kwon Lee , Sang-Ik Kim , Chang-Youn Hwang , Weon-Joon Suh , Min-Suk Lee
IPC分类号： H01L21302
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/7682
摘要： Provided is a method for forming a self aligned contact (SAC) of a semiconductor device that can minimize the loss of gate electrodes and hard mask. The method includes the steps of: providing a semiconductor substrate on which a plurality of conductive patterns are formed; forming a first insulation layer along the profile of the conductive patterns on the substrate; forming a second insulation layer on the substrate and simultaneously forming voids between the conductive patterns; forming a third insulation layer on the first insulation layer; and forming contact holes that expose the surface of the substrate between the conductive patterns by etching the third insulation layer and the second insulation layer covering the voids.
摘要翻译：提供一种用于形成可以最小化栅电极和硬掩模的损耗的半导体器件的自对准接触（SAC）的方法。该方法包括以下步骤：提供其上形成有多个导电图案的半导体衬底; 沿着衬底上的导电图案的轮廓形成第一绝缘层; 在所述基板上形成第二绝缘层，同时在所述导电图案之间形成空隙; 在所述第一绝缘层上形成第三绝缘层; 以及形成通过蚀刻所述第三绝缘层和覆盖所述空隙的所述第二绝缘层而在所述导电图案之间暴露所述基板的表面的接触孔。

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