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1. 发明申请

US20090154212A1 Memory module 有权
标题翻译：内存模块
公开(公告)号：US20090154212A1
公开(公告)日：2009-06-18
申请号：US12292700
申请日：2008-11-24
申请人： Sung-Joo Park , Kyoung-Sun Kim , Young-Ho Lee , Jea-Eun Lee
发明人： Sung-Joo Park , Kyoung-Sun Kim , Young-Ho Lee , Jea-Eun Lee
IPC分类号： G11C5/02 , G11C5/06 , G11C7/00
CPC分类号： G11C7/20 , G11C5/04 , G11C5/066 , G11C7/1078 , G11C7/1084 , G11C7/1093 , G11C2207/105
摘要： A memory module, includes a memory module board and a plurality of memory devices on the memory module board. The memory module board includes one or more first input terminals configured to receive first signals to individually control the memory devices, and one or more second input terminals configured to receive second signals to commonly control the memory devices. Each of the memory devices includes a plurality of first signal input units configured to receive the first signals through one or more first input pins, a plurality of second signal input units configured to receive the second signals through one or more second input pins, and a plurality of dummy units, the dummy units being respectively connected to the first signal input units in parallel, and being configured to receive the first signals through one or more third input pins and to compensate for a signal line load.
摘要翻译：存储器模块包括存储器模块板和存储器模块板上的多个存储器件。存储器模块板包括被配置为接收第一信号以单独控制存储器件的一个或多个第一输入端子，以及被配置为接收第二信号以共同控制存储器件的一个或多个第二输入端子。每个存储器件包括多个第一信号输入单元，其被配置为通过一个或多个第一输入引脚接收第一信号;多个第二信号输入单元，被配置为通过一个或多个第二输入引脚接收第二信号;以及多个虚拟单元，虚拟单元分别并联连接到第一信号输入单元，并且被配置为通过一个或多个第三输入引脚接收第一信号并补偿信号线负载。

2. 发明授权

US07859879B2 Memory module 有权
标题翻译：内存模块
公开(公告)号：US07859879B2
公开(公告)日：2010-12-28
申请号：US12292700
申请日：2008-11-24
申请人： Sung-Joo Park , Kyoung-Sun Kim , Young-Ho Lee , Jea-Eun Lee
发明人： Sung-Joo Park , Kyoung-Sun Kim , Young-Ho Lee , Jea-Eun Lee
IPC分类号： G11C5/00
CPC分类号： G11C7/20 , G11C5/04 , G11C5/066 , G11C7/1078 , G11C7/1084 , G11C7/1093 , G11C2207/105
摘要： A memory module, includes a memory module board and a plurality of memory devices on the memory module board. The memory module board includes one or more first input terminals configured to receive first signals to individually control the memory devices, and one or more second input terminals configured to receive second signals to commonly control the memory devices. Each of the memory devices includes a plurality of first signal input units configured to receive the first signals through one or more first input pins, a plurality of second signal input units configured to receive the second signals through one or more second input pins, and a plurality of dummy units, the dummy units being respectively connected to the first signal input units in parallel, and being configured to receive the first signals through one or more third input pins and to compensate for a signal line load.
摘要翻译：存储器模块包括存储器模块板和存储器模块板上的多个存储器件。存储器模块板包括被配置为接收第一信号以单独控制存储器件的一个或多个第一输入端子，以及被配置为接收第二信号以共同控制存储器件的一个或多个第二输入端子。每个存储器件包括多个第一信号输入单元，其被配置为通过一个或多个第一输入引脚接收第一信号;多个第二信号输入单元，被配置为通过一个或多个第二输入引脚接收第二信号;以及多个虚拟单元，虚拟单元分别并联连接到第一信号输入单元，并且被配置为通过一个或多个第三输入引脚接收第一信号并补偿信号线负载。

3. 发明申请

US20120014156A1 DATA RECEIVER, SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：数据接收器，半导体器件和包括其的存储器件
公开(公告)号：US20120014156A1
公开(公告)日：2012-01-19
申请号：US13110161
申请日：2011-05-18
申请人： Sung-Joo PARK , Jea-Eun Lee , Jung-Joon Lee , Yang-Ki Kim , Kyoung-Sun Kim
发明人： Sung-Joo PARK , Jea-Eun Lee , Jung-Joon Lee , Yang-Ki Kim , Kyoung-Sun Kim
IPC分类号： G11C5/02 , G11C7/10 , H03L5/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C8/06
摘要： A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal.
摘要翻译：数据接收机包括第一缓冲电路和第二缓冲电路。第一缓冲电路基于多个控制信号改变数据路径的电阻和参考电压路径的电阻，并且调整输入数据信号的电压电平和参考电压的电平以产生内部数据信号以及基于数据路径的变化的电阻和参考电压路径的变化的电阻的内部参考电压。第二缓冲电路将内部数据信号与内部参考电压进行比较以产生数据信号。

4. 发明授权

US07540743B2 Memory module, memory module socket and mainboard using same 有权
标题翻译：内存模块，内存模块插座和主板使用相同
公开(公告)号：US07540743B2
公开(公告)日：2009-06-02
申请号：US11836286
申请日：2007-08-09
申请人： Sung-Joo Park , Kyoung-Sun Kim , Jung-Joon Lee , Jea-Eun Lee
发明人： Sung-Joo Park , Kyoung-Sun Kim , Jung-Joon Lee , Jea-Eun Lee
IPC分类号： H01R12/00
CPC分类号： H01R12/83 , H01R13/62988 , H01R13/631 , H05K1/0295 , H05K1/117 , H05K2201/09954 , H05K2201/10159
摘要： A memory module socket disposed on a principal surface of a mainboard, and adapted to mechanically receive and electrically connect a memory module with a mainboard, the memory module socket including a first unit socket having a plurality of first socket pins adapted to electrically connect a first connector disposed on an edge of the memory module, and a second unit socket having a plurality of second socket pins adapted to electrically connect to a second connector disposed on the memory module orthogonal to the first connector, wherein the memory module as installed in the memory module socket is parallel to the principal surface of the mainboard.
摘要翻译：存储模块插座，设置在主板的主表面上，并且适于机械地接收和电连接存储器模块与主板，所述存储器模块插座包括第一单元插座，所述第一单元插座具有多个第一插座引脚，所述第一插座引脚适于电连接第一连接器，其设置在存储器模块的边缘上，以及第二单元插座，其具有多个第二插座引脚，其适于电连接到设置在与第一连接器正交的存储器模块上的第二连接器，其中存储器模块安装在存储器模块插座平行于主板的主表面。

5. 发明申请

US20080023702A1 Integrated circuit module and method of forming the same 有权
标题翻译：集成电路模块及其形成方法
公开(公告)号：US20080023702A1
公开(公告)日：2008-01-31
申请号：US11878697
申请日：2007-07-26
申请人： Sung-Joo Park , Kyoung-Sun Kim , Jung-Joon Lee , Jea-Eun Lee
发明人： Sung-Joo Park , Kyoung-Sun Kim , Jung-Joon Lee , Jea-Eun Lee
IPC分类号： H01L23/48 , H01L21/00
CPC分类号： H05K1/141 , H01L23/5385 , H01L24/16 , H01L24/81 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/14 , H05K1/0268 , H05K3/3436 , H05K2201/10378 , H05K2201/10734 , H05K2203/0455 , Y02P70/613 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method of forming an integrated circuit module may include interposing an auxiliary PCB between at least one semiconductor chip and a main PCB, the auxiliary PCB having at least one circuit pattern for electrical connection to one of the semiconductor chip and at least one circuit pattern formed on the main PCB.
摘要翻译：形成集成电路模块的方法可以包括在至少一个半导体芯片和主PCB之间插入辅助PCB，辅助PCB具有至少一个用于电连接到半导体芯片中的一个的电路图案和形成的至少一个电路图案在主PCB上。

6. 发明授权

US08559241B2 Data receiver, semiconductor device and memory device including the same 有权
标题翻译：数据接收器，半导体器件和包括其的存储器件
公开(公告)号：US08559241B2
公开(公告)日：2013-10-15
申请号：US13110161
申请日：2011-05-18
申请人： Sung-Joo Park , Jea-Eun Lee , Jung-Joon Lee , Yang-Ki Kim , Kyoung-Sun Kim
发明人： Sung-Joo Park , Jea-Eun Lee , Jung-Joon Lee , Yang-Ki Kim , Kyoung-Sun Kim
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1084 , G11C8/06
摘要： A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal.
摘要翻译：数据接收机包括第一缓冲电路和第二缓冲电路。第一缓冲电路基于多个控制信号改变数据路径的电阻和参考电压路径的电阻，并且调整输入数据信号的电压电平和参考电压的电平以产生内部数据信号以及基于数据路径的变化的电阻和参考电压路径的变化的电阻的内部参考电压。第二缓冲电路将内部数据信号与内部参考电压进行比较以产生数据信号。

7. 发明授权

US07799605B2 Integrated circuit module and method of forming the same 有权
标题翻译：集成电路模块及其形成方法
公开(公告)号：US07799605B2
公开(公告)日：2010-09-21
申请号：US11878697
申请日：2007-07-26
申请人： Sung-Joo Park , Kyoung-Sun Kim , Jung-Joon Lee , Jea-Eun Lee
发明人： Sung-Joo Park , Kyoung-Sun Kim , Jung-Joon Lee , Jea-Eun Lee
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H05K1/141 , H01L23/5385 , H01L24/16 , H01L24/81 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/14 , H05K1/0268 , H05K3/3436 , H05K2201/10378 , H05K2201/10734 , H05K2203/0455 , Y02P70/613 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method of forming an integrated circuit module may include interposing an auxiliary PCB between at least one semiconductor chip and a main PCB, the auxiliary PCB having at least one circuit pattern for electrical connection to one of the semiconductor chip and at least one circuit pattern formed on the main PCB.
摘要翻译：形成集成电路模块的方法可以包括在至少一个半导体芯片和主PCB之间插入辅助PCB，辅助PCB具有至少一个用于电连接到半导体芯片中的一个的电路图案和形成的至少一个电路图案在主PCB上。

8. 发明申请

US20090129041A1 Stacked semiconductor module, method of fabricating the same, and electronic system using the same 有权
标题翻译：叠层半导体模块及其制造方法以及使用其的电子系统
公开(公告)号：US20090129041A1
公开(公告)日：2009-05-21
申请号：US12232990
申请日：2008-09-26
申请人： Jung-Chan Cho , Yang-Je Lee , Hyun-Seok Choi , Yong-Hyun Kim , Jung-Hyeon Kim , Hyo-Jae Bang , Do-Hyung Kim , Kyoung-Sun Kim , Young-Ho Lee , Jae-Sang Baik , Yong-Jin Kim
发明人： Jung-Chan Cho , Yang-Je Lee , Hyun-Seok Choi , Yong-Hyun Kim , Jung-Hyeon Kim , Hyo-Jae Bang , Do-Hyung Kim , Kyoung-Sun Kim , Young-Ho Lee , Jae-Sang Baik , Yong-Jin Kim
IPC分类号： H05K1/14 , H05K1/00 , H05K7/10
CPC分类号： H05K1/147 , H05K1/117 , H05K1/189 , H05K3/323 , H05K3/361 , H05K3/4691 , H05K2201/042 , H05K2201/056 , H05K2201/09445 , H05K2201/0949 , H05K2201/10159 , H05K2203/1572
摘要： A stacked semiconductor module, a method of fabricating the same, and an electronic system using the module are provided. A first semiconductor module having a plurality of semiconductor devices mounted on a rigid printed circuit board (PCB) and a second semiconductor module having a plurality of other semiconductor devices mounted on a flexible PCB are provided. On the rigid PCB a number L of first tabs may be disposed on a first surface, and a number K of second tabs may be disposed on a second surface of the rigid PCB. The flexible PCB may have a number M of third tabs on a third surface, and a number N of fourth tabs on a fourth surface of the flexible PCB. The second tabs may be combined with the third tabs using a conductive adhesive. The third tabs may be electrically connected to corresponding ones of the second tabs.
摘要翻译：提供堆叠半导体模块，其制造方法和使用该模块的电子系统。提供了具有安装在刚性印刷电路板（PCB）上的多个半导体器件和具有安装在柔性PCB上的多个其它半导体器件的第二半导体模块的第一半导体模块。在刚性PCB上，可以在第一表面上设置数L个第一突出部，并且可以在刚性PCB的第二表面上设置数个K个第二突片。柔性PCB可以在第三表面上具有数量M的第三突出部，并且在柔性PCB的第四表面上可以具有数目N的第四突出部。第二突片可以使用导电粘合剂与第三突片组合。第三突片可以电连接到相应的第二突片。

9. 发明授权

US07715200B2 Stacked semiconductor module, method of fabricating the same, and electronic system using the same 有权
标题翻译：叠层半导体模块及其制造方法以及使用其的电子系统
公开(公告)号：US07715200B2
公开(公告)日：2010-05-11
申请号：US12232990
申请日：2008-09-26
申请人： Jung-Chan Cho , Yang-Je Lee , Hyun-Seok Choi , Yong-Hyun Kim , Jung-Hyeon Kim , Hyo-Jae Bang , Do-Hyung Kim , Kyoung-Sun Kim , Young-Ho Lee , Jae-Sang Baik , Yong-Jin Kim
发明人： Jung-Chan Cho , Yang-Je Lee , Hyun-Seok Choi , Yong-Hyun Kim , Jung-Hyeon Kim , Hyo-Jae Bang , Do-Hyung Kim , Kyoung-Sun Kim , Young-Ho Lee , Jae-Sang Baik , Yong-Jin Kim
IPC分类号： H05K1/00
CPC分类号： H05K1/147 , H05K1/117 , H05K1/189 , H05K3/323 , H05K3/361 , H05K3/4691 , H05K2201/042 , H05K2201/056 , H05K2201/09445 , H05K2201/0949 , H05K2201/10159 , H05K2203/1572
摘要： A stacked semiconductor module, a method of fabricating the same, and an electronic system using the module are provided. A first semiconductor module having a plurality of semiconductor devices mounted on a rigid printed circuit board (PCB) and a second semiconductor module having a plurality of other semiconductor devices mounted on a flexible PCB are provided. On the rigid PCB a number L of first tabs may be disposed on a first surface, and a number K of second tabs may be disposed on a second surface of the rigid PCB. The flexible PCB may have a number M of third tabs on a third surface, and a number N of fourth tabs on a fourth surface of the flexible PCB. The second tabs may be combined with the third tabs using a conductive adhesive. The third tabs may be electrically connected to corresponding ones of the second tabs.
摘要翻译：提供堆叠半导体模块，其制造方法和使用该模块的电子系统。提供了具有安装在刚性印刷电路板（PCB）上的多个半导体器件和具有安装在柔性PCB上的多个其它半导体器件的第二半导体模块的第一半导体模块。在刚性PCB上，可以在第一表面上设置数L个第一突出部，并且可以在刚性PCB的第二表面上设置数个K个第二突片。柔性PCB可以在第三表面上具有数量M的第三突出部，并且在柔性PCB的第四表面上可以具有数目N的第四突出部。第二突片可以使用导电粘合剂与第三突片组合。第三突片可以电连接到相应的第二突片。

10. 发明申请

US20070164448A1 Semiconductor chip package with attached electronic devices, and integrated circuit module having the same 审中-公开
标题翻译：带有电子器件的半导体芯片封装，以及具有相同电路的集成电路模块
公开(公告)号：US20070164448A1
公开(公告)日：2007-07-19
申请号：US11505361
申请日：2006-08-17
申请人： Kyoung-Sun Kim , Ki-Hyun Ko , Byoung-Ha Oh
发明人： Kyoung-Sun Kim , Ki-Hyun Ko , Byoung-Ha Oh
IPC分类号： H01L23/48
CPC分类号： H01L23/66 , H01L23/13 , H01L23/49816 , H01L23/562 , H01L24/48 , H01L2224/16 , H01L2224/4824 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19106 , H05K1/0231 , H05K3/303 , H05K2201/10378 , H05K2201/1053 , H05K2201/10568 , H05K2201/10734 , H05K2201/2036 , Y02P70/613 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided are a semiconductor chip package with attached electronic devices, and an integrated circuit module having the same. The semiconductor chip packages may include a supporting substrate, input/output bonding pads arranged on a first plane of the supporting substrate, and device bonding pads arranged on the edges of the first plane or portions of the first plane adjacent to the edges. Accordingly, the mount area of a printed circuit board may be reduced, efficient routing may be possible, and the occurrence of package cracks may be reduced and/or prevented.
摘要翻译：提供了具有附接的电子设备的半导体芯片封装以及具有该电子器件的集成电路模块。半导体芯片封装可以包括支撑衬底，布置在支撑衬底的第一平面上的输入/输出接合焊盘以及布置在第一平面的边缘上的第一平面的边缘或邻近边缘的第一平面的部分的器件接合焊盘。因此，可以减少印刷电路板的安装面积，可以有效地布线，并且可以减少和/或防止包装裂缝的发生。

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