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1. 发明授权

US07540743B2 Memory module, memory module socket and mainboard using same 有权
标题翻译：内存模块，内存模块插座和主板使用相同
公开(公告)号：US07540743B2
公开(公告)日：2009-06-02
申请号：US11836286
申请日：2007-08-09
申请人： Sung-Joo Park , Kyoung-Sun Kim , Jung-Joon Lee , Jea-Eun Lee
发明人： Sung-Joo Park , Kyoung-Sun Kim , Jung-Joon Lee , Jea-Eun Lee
IPC分类号： H01R12/00
CPC分类号： H01R12/83 , H01R13/62988 , H01R13/631 , H05K1/0295 , H05K1/117 , H05K2201/09954 , H05K2201/10159
摘要： A memory module socket disposed on a principal surface of a mainboard, and adapted to mechanically receive and electrically connect a memory module with a mainboard, the memory module socket including a first unit socket having a plurality of first socket pins adapted to electrically connect a first connector disposed on an edge of the memory module, and a second unit socket having a plurality of second socket pins adapted to electrically connect to a second connector disposed on the memory module orthogonal to the first connector, wherein the memory module as installed in the memory module socket is parallel to the principal surface of the mainboard.
摘要翻译：存储模块插座，设置在主板的主表面上，并且适于机械地接收和电连接存储器模块与主板，所述存储器模块插座包括第一单元插座，所述第一单元插座具有多个第一插座引脚，所述第一插座引脚适于电连接第一连接器，其设置在存储器模块的边缘上，以及第二单元插座，其具有多个第二插座引脚，其适于电连接到设置在与第一连接器正交的存储器模块上的第二连接器，其中存储器模块安装在存储器模块插座平行于主板的主表面。

2. 发明申请

US20080023702A1 Integrated circuit module and method of forming the same 有权
标题翻译：集成电路模块及其形成方法
公开(公告)号：US20080023702A1
公开(公告)日：2008-01-31
申请号：US11878697
申请日：2007-07-26
申请人： Sung-Joo Park , Kyoung-Sun Kim , Jung-Joon Lee , Jea-Eun Lee
发明人： Sung-Joo Park , Kyoung-Sun Kim , Jung-Joon Lee , Jea-Eun Lee
IPC分类号： H01L23/48 , H01L21/00
CPC分类号： H05K1/141 , H01L23/5385 , H01L24/16 , H01L24/81 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/14 , H05K1/0268 , H05K3/3436 , H05K2201/10378 , H05K2201/10734 , H05K2203/0455 , Y02P70/613 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method of forming an integrated circuit module may include interposing an auxiliary PCB between at least one semiconductor chip and a main PCB, the auxiliary PCB having at least one circuit pattern for electrical connection to one of the semiconductor chip and at least one circuit pattern formed on the main PCB.
摘要翻译：形成集成电路模块的方法可以包括在至少一个半导体芯片和主PCB之间插入辅助PCB，辅助PCB具有至少一个用于电连接到半导体芯片中的一个的电路图案和形成的至少一个电路图案在主PCB上。

3. 发明授权

US08559241B2 Data receiver, semiconductor device and memory device including the same 有权
标题翻译：数据接收器，半导体器件和包括其的存储器件
公开(公告)号：US08559241B2
公开(公告)日：2013-10-15
申请号：US13110161
申请日：2011-05-18
申请人： Sung-Joo Park , Jea-Eun Lee , Jung-Joon Lee , Yang-Ki Kim , Kyoung-Sun Kim
发明人： Sung-Joo Park , Jea-Eun Lee , Jung-Joon Lee , Yang-Ki Kim , Kyoung-Sun Kim
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1084 , G11C8/06
摘要： A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal.
摘要翻译：数据接收机包括第一缓冲电路和第二缓冲电路。第一缓冲电路基于多个控制信号改变数据路径的电阻和参考电压路径的电阻，并且调整输入数据信号的电压电平和参考电压的电平以产生内部数据信号以及基于数据路径的变化的电阻和参考电压路径的变化的电阻的内部参考电压。第二缓冲电路将内部数据信号与内部参考电压进行比较以产生数据信号。

4. 发明授权

US07799605B2 Integrated circuit module and method of forming the same 有权
标题翻译：集成电路模块及其形成方法
公开(公告)号：US07799605B2
公开(公告)日：2010-09-21
申请号：US11878697
申请日：2007-07-26
申请人： Sung-Joo Park , Kyoung-Sun Kim , Jung-Joon Lee , Jea-Eun Lee
发明人： Sung-Joo Park , Kyoung-Sun Kim , Jung-Joon Lee , Jea-Eun Lee
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H05K1/141 , H01L23/5385 , H01L24/16 , H01L24/81 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/14 , H05K1/0268 , H05K3/3436 , H05K2201/10378 , H05K2201/10734 , H05K2203/0455 , Y02P70/613 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method of forming an integrated circuit module may include interposing an auxiliary PCB between at least one semiconductor chip and a main PCB, the auxiliary PCB having at least one circuit pattern for electrical connection to one of the semiconductor chip and at least one circuit pattern formed on the main PCB.
摘要翻译：形成集成电路模块的方法可以包括在至少一个半导体芯片和主PCB之间插入辅助PCB，辅助PCB具有至少一个用于电连接到半导体芯片中的一个的电路图案和形成的至少一个电路图案在主PCB上。

5. 发明申请

US20120014156A1 DATA RECEIVER, SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：数据接收器，半导体器件和包括其的存储器件
公开(公告)号：US20120014156A1
公开(公告)日：2012-01-19
申请号：US13110161
申请日：2011-05-18
申请人： Sung-Joo PARK , Jea-Eun Lee , Jung-Joon Lee , Yang-Ki Kim , Kyoung-Sun Kim
发明人： Sung-Joo PARK , Jea-Eun Lee , Jung-Joon Lee , Yang-Ki Kim , Kyoung-Sun Kim
IPC分类号： G11C5/02 , G11C7/10 , H03L5/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C8/06
摘要： A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal.
摘要翻译：数据接收机包括第一缓冲电路和第二缓冲电路。第一缓冲电路基于多个控制信号改变数据路径的电阻和参考电压路径的电阻，并且调整输入数据信号的电压电平和参考电压的电平以产生内部数据信号以及基于数据路径的变化的电阻和参考电压路径的变化的电阻的内部参考电压。第二缓冲电路将内部数据信号与内部参考电压进行比较以产生数据信号。

6. 发明申请

US20050002241A1 Memory system with improved signal integrity 审中-公开
标题翻译：具有改善信号完整性的存储系统
公开(公告)号：US20050002241A1
公开(公告)日：2005-01-06
申请号：US10837610
申请日：2004-05-04
申请人： Sung-Joo Park , Byung-Se So , Jung-Joon Lee , Jae-Jun Lee , Chil-Nam Yoon
发明人： Sung-Joo Park , Byung-Se So , Jung-Joon Lee , Jae-Jun Lee , Chil-Nam Yoon
IPC分类号： G06F12/00 , G06F13/40 , G11C5/00 , G11C5/06
CPC分类号： G06F13/4086
摘要： A memory system includes a memory controller, a memory bus connected to the memory controller, and a plurality of memory modules connected along the memory bus, where each of the memory modules includes a plurality of memory devices. The system also includes a dummy stub or a dummy module connected to the memory bus between the memory controller and the memory module closest to the memory controller among the plurality of memory modules. The dummy stub or dummy module improves a signal integrity of at least the memory module closest to the memory controller.
摘要翻译：存储器系统包括存储器控制器，连接到存储器控制器的存储器总线以及沿着存储器总线连接的多个存储器模块，其中每个存储器模块包括多个存储器件。该系统还包括连接到存储器总线之间的存储器控制器和位于多个存储器模块中最靠近存储器控制器的存储器模块之间的虚拟存根或虚拟模块。虚拟短线或虚拟模块改善了至少与存储器控制器最接近的存储器模块的信号完整性。

7. 发明授权

US06836138B1 Module having test architecture for facilitating the testing of ball grid array packages, and test method using the same 失效
标题翻译：具有用于促进球栅阵列封装测试的测试架构的模块，以及使用其的测试方法
公开(公告)号：US06836138B1
公开(公告)日：2004-12-28
申请号：US10795507
申请日：2004-03-09
申请人： Sung-Joo Park , Byung-Se So , Jung-Joon Lee
发明人： Sung-Joo Park , Byung-Se So , Jung-Joon Lee
IPC分类号： G01R3126
CPC分类号： H05K1/0268 , G01R1/0483 , G01R31/31905 , G11C29/48 , G11C2029/5602 , H01L2224/48091 , H01L2224/859 , H01L2924/15311 , H01L2924/3011 , H05K1/111 , H05K2201/10734 , H01L2924/00014
摘要： A ball grid array (BGA) package test module includes BGA packages, a module board, and test architecture for use in testing the BGA packages while they are mounted to the module board. The test architecture of the BGA package test module includes package test signal lines connected to solder balls of the BGA packages as extending along a bottom surface of the BGA packages, board test signal lines extending along the module board, and electrical junctions that interconnect the package and board test signal lines. Signals from the BGA packages can be picked up by the probe of a testing apparatus via the board test signal lines. The present invention is advantageous in that it minimizes the effect of stubbing by the test signal lines when the memory module is operating.
摘要翻译：球栅阵列（BGA）封装测试模块包括BGA封装，模块板和测试架构，用于在安装到模块板时测试BGA封装。 BGA封装测试模块的测试架构包括连接到BGA封装的焊球的封装测试信号线，沿BGA封装的底表面延伸，沿着模块板延伸的板测试信号线，以及将封装相互连接的电连接和板测试信号线。来自BGA封装的信号可以由测试装置的探头通过板测试信号线拾取。本发明的优点在于，当存储器模块运行时，其最小化由测试信号线引起的短截线的影响。

8. 发明授权

US07276786B2 Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip packages are mounted 失效
标题翻译：具有镜像结构和双列直插存储器模块的堆叠板上芯片封装，其上安装有堆叠板上芯片封装
公开(公告)号：US07276786B2
公开(公告)日：2007-10-02
申请号：US11177736
申请日：2005-07-08
申请人： Jeong-Hyeon Cho , Jung-Joon Lee , Do-Hyung Kim , Byung-Se So
发明人： Jeong-Hyeon Cho , Jung-Joon Lee , Do-Hyung Kim , Byung-Se So
IPC分类号： H01L23/42 , H01L23/58 , H01L29/40
CPC分类号： H01L25/105 , H01L23/3128 , H01L25/16 , H01L2224/06136 , H01L2224/48091 , H01L2224/4824 , H01L2225/1023 , H01L2225/107 , H01L2225/1094 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/00014
摘要： Embodiments of the invention include a stacked board-on-chip (BOC) package having a mirroring structure and a dual inline memory module (DIMM) on which the stacked BOC package is mounted. A bottom surface of a first semiconductor chip faces a bottom surface of a second semiconductor chip. An interposer electrically connects first and second packages, respectively comprising the first and second semiconductor chips, to each other. The DIMM is obtained by electrically connecting BOC packages to each other on upper and lower substrates of a printed circuit board. Since a height of the stacked BOC packages is greater than a height of a conventional stacked BOC package, the DIMM has a minimum stub length and an optimal topology. Hence, the DIMM can have a signal with excellent fidelity by reducing a load upon a signal line, and installation or wiring of components within the DIMM 300 requires less effort.
摘要翻译：本发明的实施例包括具有镜像结构的堆叠板上芯片（BOC）封装和其上安装有堆叠的BOC封装的双列直插存储器模块（DIMM）。第一半导体芯片的底面朝向第二半导体芯片的底面。插入器将分别包括第一和第二半导体芯片的第一和第二封装彼此电连接。通过在印刷电路板的上下基板上将BOC封装彼此电连接来获得DIMM。由于堆叠的BOC封装的高度大于常规堆叠BOC封装的高度，所以DIMM具有最小的短截线长度和最佳拓扑。因此，通过减少信号线上的负载，DIMM可以具有出色的保真度的信号，并且DIMM 300内的组件的安装或接线需要较少的努力。

9. 发明申请

US20060184755A1 Semiconductor memory device and memory system using same 失效
标题翻译：半导体存储器件和使用其的存储器系统
公开(公告)号：US20060184755A1
公开(公告)日：2006-08-17
申请号：US11352009
申请日：2006-02-11
申请人： Jung-Joon Lee
发明人： Jung-Joon Lee
IPC分类号： G06F13/00
CPC分类号： G11C7/20 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： There is provided a semiconductor memory device and a memory system using the same. The semiconductor memory device includes an input data delay time adjustor for varying an input delay time, selecting one bit of a n-bit input data, delaying the selected one bit by the input delay time and outputting the delayed bit, in response to a control signal during an input data delay test operation; and an output data delay time adjustor for varying an output delay time, selecting one bit of a m-bit output data, delaying the selected one bit by the output delay time and outputting the delayed bit, in response to the control signal during an output data delay test operation, wherein the input data delay time adjustor is arranged for n-bit input data, and wherein the output data delay time adjustor is arranged for m-bit output data.
摘要翻译：提供了一种半导体存储器件和使用该半导体存储器件的存储器系统。半导体存储器件包括用于改变输入延迟时间的输入数据延迟时间调节器，选择n位输入数据的一位，响应于控制将所选择的一位延迟输入延迟时间并输出延迟位在输入数据延迟测试操作期间信号; 以及输出数据延迟时间调整器，用于改变输出延迟时间，选择m位输出数据的一位，响应于输出期间的控制信号，将所选择的一位延迟输出延迟时间并输出延迟位数据延迟测试操作，其中输入数据延迟时间调节器被配置用于n位输入数据，并且其中输出数据延迟时间调整器被布置用于m位输出数据。

10. 发明申请

US20060055017A1 Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip package are mounted 失效
标题翻译：堆叠的片上芯片封装，具有镜像结构和双列直插存储器模块，其上安装有堆叠的片上芯片封装
公开(公告)号：US20060055017A1
公开(公告)日：2006-03-16
申请号：US11177736
申请日：2005-07-08
申请人： Jeong-Hyeon Cho , Jung-Joon Lee , Do-Hyung Kim , Byung-Se So
发明人： Jeong-Hyeon Cho , Jung-Joon Lee , Do-Hyung Kim , Byung-Se So
IPC分类号： H01L23/02
CPC分类号： H01L25/105 , H01L23/3128 , H01L25/16 , H01L2224/06136 , H01L2224/48091 , H01L2224/4824 , H01L2225/1023 , H01L2225/107 , H01L2225/1094 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/00014
摘要： Embodiments of the invention include a stacked board-on-chip (BOC) package having a mirroring structure and a dual inline memory module (DIMM) on which the stacked BOC package is mounted. A bottom surface of a first semiconductor chip faces a bottom surface of a second semiconductor chip. An interposer electrically connects first and second packages, respectively comprising the first and second semiconductor chips, to each other. The DIMM is obtained by electrically connecting BOC packages to each other on upper and lower substrates of a printed circuit board. Since a height of the stacked BOC packages is greater than a height of a conventional stacked BOC package, the DIMM has a minimum stub length and an optimal topology. Hence, the DIMM can have a signal with excellent fidelity by reducing a load upon a signal line, and installation or wiring of components within the DIMM 300 requires less effort.
摘要翻译：本发明的实施例包括具有镜像结构的堆叠板上芯片（BOC）封装和其上安装有堆叠的BOC封装的双列直插存储器模块（DIMM）。第一半导体芯片的底面朝向第二半导体芯片的底面。插入器将分别包括第一和第二半导体芯片的第一和第二封装彼此电连接。通过在印刷电路板的上下基板上将BOC封装彼此电连接来获得DIMM。由于堆叠的BOC封装的高度大于常规堆叠BOC封装的高度，所以DIMM具有最小的短截线长度和最佳拓扑。因此，通过减少信号线上的负载，DIMM可以具有出色的保真度的信号，并且DIMM 300内的组件的安装或接线需要较少的努力。

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