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    • 4. 发明授权
    • Semiconductor memory device, memory device support and memory module
    • 半导体存储器件,存储器件支持和存储器模块
    • US07738277B2
    • 2010-06-15
    • US11905675
    • 2007-10-03
    • Sungjoo ParkKi-Hyun KoYoung YunSookyung Kim
    • Sungjoo ParkKi-Hyun KoYoung YunSookyung Kim
    • G11C5/06
    • H01L25/0657G11C5/04H01L2225/06513H01L2225/06541H01L2924/0002H01L2924/00
    • In one embodiment, the semiconductor memory device includes at least a first semiconductor memory die, and a surface of the semiconductor memory device includes a plurality of connectors. At least one of the plurality of connectors is electrically connected to the first semiconductor memory die. The plurality of connectors include at least first and second control signal connectors. The first control signal connector is for a first control signal of a first type, the second control signal connector is for a second control signal of the first type, and the first and second control signal connectors are disposed in different areas of the surface. For example, the first type may be a chip select signal, a clock enable signal, or an on die termination enable signal.
    • 在一个实施例中,半导体存储器件至少包括第一半导体存储器管芯,并且半导体存储器件的表面包括多个连接器。 多个连接器中的至少一个电连接到第一半导体存储器管芯。 多个连接器包括至少第一和第二控制信号连接器。 第一控制信号连接器用于第一类型的第一控制信号,第二控制信号连接器用于第一类型的第二控制信号,并且第一和第二控制信号连接器设置在表面的不同区域中。 例如,第一类型可以是芯片选择信号,时钟使能信号或芯片上终止使能信号。
    • 5. 发明授权
    • Memory module and signal line arrangement method thereof
    • 存储模块及其信号线排列方法
    • US07390973B2
    • 2008-06-24
    • US11357500
    • 2006-02-17
    • Chil-Nam YoonKwang-Seop KimDo-Hyung KimJae-Jun LeeKi-Hyun Ko
    • Chil-Nam YoonKwang-Seop KimDo-Hyung KimJae-Jun LeeKi-Hyun Ko
    • H05K1/16
    • H05K1/181G11C5/025G11C5/04H05K1/112H05K2201/10159H05K2201/10545Y02P70/611Y10T29/49128Y10T29/49155
    • The pesent invention discloses a memory module and a signal line arrangement method thereof. The memory module includes memory chips mounted on both sidees in a mirror form; and a printed circuit board (PCB) having same signal applying contact pads arranged on both sodes which same signal applying balls of the memory chips contact in the mirror form, wherein a via is formed at a location close to the same signal applying contact pad of one side among the same signal applying contact pads arranged on both sides in the mirror form, the via connecting the other side to the signal line of one side, and a signal transmitted from the other side is connected to a contact junction, the contact junction is connected to the same signal applying contact pad of the other side, the contact junction is connected to the via of the other side, and the via of one side is connected to the same signal applying contact pad of one side.
    • 本发明公开了一种存储模块及其信号线排列方法。 存储器模块包括以镜子形式安装在两侧的存储器芯片; 以及具有相同信号的印刷电路板(PCB),其施加布置在两个信号线上的接触焊盘,所述存储器芯片的相同信号施加球以镜子形式接触,其中通孔形成在接近相同信号的位置处,施加接触焊盘 在相同的信号中,以镜面形式设置在两侧的接触焊盘的一侧,将另一侧连接到一侧的信号线的通孔,并且从另一侧传输的信号连接到接触接点,接触接点 连接到另一侧的相同信号施加接触焊盘,接触点连接到另一侧的通孔,并且一侧的通孔连接到施加一侧接触焊盘的相同信号。
    • 7. 发明授权
    • Memory board structure having stub resistor on main board
    • 内存板结构在主板上具有短路电阻
    • US08144481B2
    • 2012-03-27
    • US12632853
    • 2009-12-08
    • Sung-Joo ParkKi-Hyun KoMyung-Hee Sung
    • Sung-Joo ParkKi-Hyun KoMyung-Hee Sung
    • H01R9/00
    • H05K1/0246H05K1/14H05K1/181H05K2201/044H05K2201/09254H05K2201/10022H05K2201/10159
    • A memory system includes; a main board having memory bus with a wiring line communicating a signal from a memory controller mounted on the main board, first and second module sockets mounted on the main board and connecting the wiring line to first and second memory modules respectively inserted into the first and second module sockets, where the first memory module includes a first electrode connected to the wiring line and the second memory module includes a second electrode connected to the wiring line, and first and second stub resistors disposed on the main board and arranged as primary dual-branching stub resistors forming a T-branch connection structure between the first and second electrodes and a branching node connected to the wiring line.
    • 存储系统包括: 具有存储器总线的主板,具有用于传送来自安装在主板上的存储器控​​制器的信号的布线的布线;安装在主板上的第一和第二模块插槽,并将布线连接到分别插入第一和第二存储器模块的第一和第二存储器模块; 第二模块插座,其中第一存储器模块包括连接到布线的第一电极,并且第二存储器模块包括连接到布线的第二电极,以及设置在主板上并被布置为主要双绞线的第一和第二短截线电阻器, 在第一和第二电极之间形成T分支连接结构的分支短截线电阻器和连接到布线的分支节点。